MFC: r342634 (partial)

o Don't allocate resources for SDMA in sdhci(4) if the controller or the
front-end doesn't support SDMA or the latter implements a platform-
specific transfer method instead. While at it, factor out allocation
and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to
keep the code more readable when adding support for ADMA variants.

o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum
of 512 KiB instead of using a fixed 4-KiB-buffer. With the default
MAXPHYS of 128 KiB and depending on the controller and medium, this
reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on
sequential reads while an increase of throughput of up to ~84 % was
seen.

Front-ends for broken controllers that only support an SDMA buffer
boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY
and supply a size via struct sdhci_slot. According to Linux, only -
unsupported in stable/10 anyway - Qualcomm MSM-type SDHCI controllers
are affected by this, though.

Requested by: Shreyank Amartya (unconditional bump to 512 KiB)

o Introduce a SDHCI_DEPEND macro for specifying the dependency of the
front-end modules on the sdhci(4) one and bump the module version
of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order
to ensure that all components are in sync WRT struct sdhci_slot.

o In sdhci(4):
- Make pointers const were applicable, and
- replace a few device_printf(9) calls with slot_printf() for
consistency.

Apply the other half of merges to sdhci_imx(4) and sdhci_fsl(4) that
somehow stayed local when committing r318198, probably due to the
associated tree conflicts.

While at it, register the dependency of sdhci_fsl(4) on sdhci(4) and
allow the former to be built.

MFC: r292180 (partial), r297127 (partial), r311911, r311923, r312939,
r313250, r313712, r314811 (partial), r314887 (partial), r315430,
r317981, r315466

o Move the DRIVER_MODULE() statements that declare mmc(4) to be a child
of the various bridge drivers out of dev/mmc.c and into the bridge
drivers.

o Add ACPI platform support for SDHCI driver.

o Fix some overly long lines, whitespace and other bugs according to
style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4).

o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method,
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.

o Trim/adjust includes.

o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
as kernel drivers and their dependency onto mmc(4).

o Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)

Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.

CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.

o Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications.

o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter have been added to ports as sysutils/mmc-utils.
Among others, the `mmc` tool of mmc-utils allows for partitioning
eMMC devices (tested working).

o For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.

o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.

MFC r292419, r294237:

Fix the clock divisor calc for imx6 sdcard bus speed.

Quick exit after setting the clock control register.

MFC r291149, r291367:

Update the imx5/imx6 cpu_reset() implementation based on a new understanding
of the SRS (software reset) bit in the watchdog control register. Despite
what the manual seems to imply, this bit DOES trigger an immediate reset, as
opposed to simply flagging the type of reset as software-triggered.

Rename sysctl node hw.imx6 to hw.imx. Move its definition to imx_machdep.c
so that code shared between imx5 and imx6 can work with OIDs under that node.

Add last_reset_status (integer) and last_reset_reason (string) OIDs that
provide info about the last chip reset (power-on, software reset, watchdog
timeout).

MFC r281828, r289083, r289084, r289091, r289093, r289095, r289097, r289098,
r289104, r289105, r289118: various i2c fixes...

Fix numerous issues in iic(4) and iicbus(4):
--Allow multiple open iic fds by storing addressing state in cdevpriv
--Fix, as much as possible, the baked-in race conditions in the iic
ioctl interface by requesting bus ownership on I2CSTART, releasing it on
I2CSTOP/I2CRSTCARD, and requiring bus ownership by the current cdevpriv
to use the I/O ioctls
--Reduce internal iic buffer size and remove 1K read/write limit by
iteratively calling iicbus_read/iicbus_write
--Eliminate dynamic allocation in I2CWRITE/I2CREAD
--Move handling of I2CRDWR to separate function and improve error handling
--Add new I2CSADDR ioctl to store address in current cdevpriv so that
I2CSTART is not needed for read(2)/write(2) to work
--Redesign iicbus_request_bus() and iicbus_release_bus():
--iicbus_request_bus() no longer falls through if the bus is already
owned by the requesting device. Multiple threads on the same device may
want exclusive access. Also, iicbus_release_bus() was never
device-recursive anyway.
--Previously, if IICBUS_CALLBACK failed in iicbus_release_bus(), but
the following iicbus_poll() call succeeded, IICBUS_CALLBACK would not be
issued again
--Do not hold iicbus mtx during IICBUS_CALLBACK call. There are
several drivers that may sleep in IICBUS_CALLBACK, if IIC_WAIT is passed.
--Do not loop in iicbus_request_bus if IICBUS_CALLBACK returns
EWOULDBLOCK; instead pass that to the caller so that it can retry if so
desired.

Bugfix: Exit the transfer loop if any read or write operation fails. Also,
perform a stop operation on the bus if there was an error, otherwise the
bus will remain hung forever. Consistantly use 'if (error != 0)' style in
the function.

Mostly rewrite the imx i2c driver. This started out as an attempt to fix
one specific problem: the driver didn't check for ACK/NAK after writing a
slave address byte to the bus, and some slaves signal that they are busy
(such as when completing an internal write to flash memory) by sending a
NAK in response to being addressed.

Use IIC_EBUSBSY and IIC_BUSERR status values consistantly across all drivers.
Make it clearer what each one means in the comments that define them.

Add iic2errno(), a helper function to translate IIC_Exxxxx status values to
errno values that are at least vaguely equivelent. Also add a new status
value, IIC_ERESOURCE, to indicate a failure to acquire memory or other
required resources to complete a transaction.

Return only IIC_Exxxx status values from iicbus-layer functions. Most of
these functions are thin wrappers around calling the hardware-layer driver,
but some of them do sanity checks and return an error.

Add a short name, IIC_INTRWAIT, for the common case (IIC_INTR | IIC_WAIT).

Replace a local sx lock that allowed only one client at a time to access
an eeprom device with iicbus_request/release_bus(), which achieves the
same effect and also keeps other i2c slave drivers from clashing on the bus.

MFC r286942, r286943, r286944: imx watchdog fixes...

Add compatible strings for all the hardware this driver works with.

Also, move the READ/WRITE bus space access macros from the header into the
source file, and rename them to RD2/WR2 to make it clear they're 16-bit
accessors. (READ/WRITE just don't seem like good names to be in a public
header file.)

Make the imx watchdog actually work, by setting WDOG_CR_WDE (enable bit).
Also, follow the rules from watchdog(9) about what values to return in
various situations (especially, don't touch *error when asked to set a
non-zero timeout that isn't achievable on the hardware).

Enable the watchdog driver on imx6, now that it works.

MFC r282516:

Add the code necessary to run the imx6 chip at its lowest clock/power
operating point (396MHz/950mV).

MFC r268838, r277644:

Add support for Toradex Apalis i.MX6 development board.

Add support for imx6 audio transmitting, include drivers for:
o Digital Audio Multiplexer (AUDMUX)
o Smart Direct Memory Access Controller (SDMA)
o Synchronous Serial Interface (SSI)

MFC r279723, r279724:

Define new linker set, UART_FDT_CLASS_AND_DEVICE, for registering full
(class and device) FDT UART. Define second one, UART_FDT_CLASS, for UART
class only.

Move the uart_class definitions and fdt compat data into the individual
uart implementations, and export them using the new linker-set mechanism.

MFC r274670, r274671, r276168:

Moves all the duplicate code to a single function.

Verify for invalid modes and unwanted flags before pass the new flags to
driver.

Make gpio_default_map_gpios() static. No functional changes.

Improves the GPIO API description a little bit.

gpio_pin_max must return the maximum supported pin number and not the total
number of pins on the system.

MFC r273799:

Make the GPIO children attach to the first unit available and not only to
unit 0.

This fix a bug where a GPIO controller could fail to attach its children
(gpioc and gpiobus) if another GPIO driver attach first.

MFC r277555, r277568:

Enable all sd device clocks on imx6.

Add imx5/6 pinmux driver support for encoded input register configs.

MFC r277454, r277460, r277465, r277466, r277467, r277469, r277470, r277471,
r277472, r277473, r277474, r277475, r277476, r277477, r277478, r277479,
r277480, r277512, r277516:

Add inline implementations of arm bus_space_read/write_N().

Revise the arm bus_space implementation to avoid dereferencing the tag on
every operation to retrieve the bs_cookie value almost nothing actually uses.

Use the explicit member initializer style to init the bus_space struct.

Use arm/bus_space-v6.c for all armv6 systems

Consolidate many identical implementations of bus_space to a single
common tag and implementation shared by armv4 and armv6.

Micro-optimize the new arm inline bus_space implementation by grouping all
the data the inline functions access together at the start of the bus_space
struct so that they all fit in a single cache line.

MFC r257740, r257739: Switch to using common armv6 bus_space tag.

MFC r276047: Add -march=armv7a to the kernel compile for all v7a ARM systems.

MFC r266969 and r276717:
Add 64-bit DMA support in the XHCI controller driver.
- Fix some comments and whitespaces while at it.
- Add support for PAE.

MFC r274641, r274644, r274822, r276049:

Allow i2c bus speed to be configured via hints, FDT data, and sysctl.

Implement bus speed setting for OMAP4, AM335x, and imx5/6.

Fix the i2c bus speed divisors for TI OMAP4 and AM335x to give the
advertised 100, 400, and 1000 KHz speeds.

PR: 195009

MFC r274412, r274413, r274414: Bugfixes for imx5/6 pinctrl driver.

MFC r273561:

Install a temporary workaround to avoid problems in fdt data with linux's
workaround for an imx6 chip erratum by using gpio1_6 as an interrupt.

MFC r273353, r273514:

Attach the imx6 CCM driver during BUS_PASS_CPU.

Unconditionally enable the clocks for all imx6 devices that we have drivers
for, or that are required to run the chip (such as busses).

MFC r273352: Ask for the fastest available clock for the GTP timecounter.

MFC r273283:

Attach this driver during BUS_PASS_BUS and move the cpu init code to a
bus_new_pass() handler so it doesn't happen until BUS_PASS_CPU. This allows
the anatop driver to outbid the generic simplebus driver (which the FDT
data describes as compatible).

MFC r271595, r271601, r271607, r271630:

Add compat strings for all the flavors of GIC this driver should support.
Also allow the driver to attach to ofwbus as well as simplebus, some FDT
data puts the root interrupt controller on the root bus.

Add a common routine for parsing FDT data describing an ARM GIC interrupt.

Use gic_decode_fdt() rather than a local routine to parse fdt interrupt
properties. Move fdt_pic_table and fdt_fixup_table into imx6_machdep.c,
which means imx6 doesn't need imx_common.c anymore.

The private peripheral interrupts start at offset 16, not 0. Also, use
names rather than inline mystery constants for these offsets.

MFC r271550, r271591:

Replace the imx5 and imx6 iomux drivers with a single common driver that
uses the new fdt_pinctrl interface.

MFC r271097, r271100, r271101, r271102, r271124:

- Add a basic iomux driver for imx6.
- Implement the same public interface in imx51 and imx6 iomux
- The iomux driver is no longer optional, remove it from kernel configs.
- Implement the imx_iomux_get/set_gpr() interface for imx6.
- Stop setting the iomux device status to disabled, now that we have a driver.

MFC r268973, r268977: Rename i.MX I2C driver file, enable it on imx6.

MFC r268834, r268835:

o Enable GPIO device driver for i.MX6.
It was originally written for i.MX5 and compatible with newer chip.
o Extend device tree information
o style(9) fixes
o Rename gpio driver file.

MFC r271055, r271084, r271094:

Add a function to get the frequency of the AHB bus. Another stopgap
function until we have full clock support for imx6.

The imx5x and imx6 chips have an onboard IOMUX device which also contains a
few "general purpose registers" whose values control chip behavior in ways
that have nothing to do with IO pin mux control. Define a simple API that
other soc-specific code can use to read and write the registers, and provide
the imx51 implementation of them.

Fix a typo.

MFC r270955,r270956: make the imx6 octop and anatop drivers early attachers.

MFC r270945:

Rename OF_xref_phandle() to OF_node_from_xref() and add a new function
that provides the inverse translation, OF_xref_from_node().

MFC r270065:

Move the imx6 sysctl temperature info to hw.imx6 where all the other
soc-wide info lives. It was under dev.imx6_anatop.0.

Approved by: re(gjb)

MFC: r270885, r270948

- Nuke unused sdhci_softc.
- Static'ize sdhci_debug local to sdhci.c.
- Const'ify PCI device description strings.
- Nuke redundant resource ID members from sdhci_pci_softc.
- Nuke unused hw.sdhci_pci.debug tunable.
- Add support for using MSI instead of INTx, controllable via the tunable
hw.sdhci.enable_msi (defaulting to on) and tested with a RICOH R5CE823 SD
controller.
- Use NULL instead of 0 for pointers.

vt(4): Colors are indexed against a console palette, not a VGA palette

Rename vt_generate_vga_palette() to vt_generate_cons_palette() and
change it to build a palette where the color index is the same than in
terminal escape codes, not the VGA index. That's what TCHAR_CREATE()
uses and passes to vt(4).

The main differences between both orders are:
o Blue and red are swapped (1 <-> 4)
o Yellow and cyan are swapped (3 <-> 6)

The problem remained unnoticed, because the RGB bit indexes passed to
vt_generate_vga_palette() were reversed. This inversion was cancelled
by the colors inversions in the generated palette. For instance, red
(0xff0000) and blue (0x0000ff) have bytes in opposite order, but were
swapped in the palette. But after changing the value of blue (see last
paragraph), the modified color was in fact the red one.

While here, tune the palette to better match console colors and improve
the readability (especially the dark blue).

This is an MFC of r269783 and r269791.

MFC r269607, r269698:

Cache the imx6 SoC type in a static var so that it only has to be figured
out by sniffing hardware registers once.

Add a missing clock register definition.

MFC r268401, r268495:

Pending interrupt status is cleared by writing to the ISR, not the data reg.

Use named constant rather than '0' to access the reset controller register.

MFC 265440, 265441, 265444, 265445, 265446, 265447:

Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits. Use DEVMETHOD_END.

Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.

Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.

Add defines for the bits in the PL310 debug control register.

Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.

Enable PL310 power-saving modes and tune the cache ram latencies for imx6.

MFC 265035: Move duplicated code to print l2 config into the common code.

MFC 264977:

Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead
define a few imx_ccm_foo() functions that are implemented by the imx51
or imx6 ccm code.

MFC 264251: Updates to i.MX53:

* Define support for the SDHCI driver, although it doesn't work yet
* Fix the memory mappings for IPU

MFC 264180, 264181, 264182:

Follow files.imx51 and add vt support for imx53.

Add fsl,imx53 compatible string.

Need to include machine/fdt.h in vt_early_fb.c

MFC 264052, 264057, 264065, 264094, 264103, 264120

Actually save the mpcore clock frequency retrieved from fdt data.

imx6..
- Don't call sdhci_init_slot() until after handling the FDT properties
related to detecting card presence.
- Flag several sysctl variables as tunables.
- Rework the cpu frequency management code for imx6 to add "operating
points" and min/max frequency controls.

generic timer...
- Setup both secure and non-secure timer IRQs.
We don't know our ARM security state, so one of them will operate.
- Don't set frequency, since it's unpossible in non-secure state.
Only rely on DTS clock-frequency value or get clock from timer.

MFC 264054, 264056

Switch imx6 to using the mpcore per-cpu event timers, but continue to use
the GPT timer, which is fixed-frequency, as a timecounter.

Change NO_EVENTTIMERS from an arm-specific to an MI option, so that it can
be used in MI code.

MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,
263030, 263033, 263034, 263056, 263057,

Remove all the redundant external declarations of exception vectors and
runtime setting of the pointers that's scattered around various places.

Remove all traces of support for ARM chips prior to the arm9 series.

Make the default exception handler vectors point to where I thought they
were already pointing: the default handlers (not a panic that says there
is no default handler).

Eliminate irq_dispatch.S. Move the data items it contained into
arm/intr.c and the functionality it provided into arm/exception.S.

Move the exception vector table (so-called "page0" data) into exception.S
and eliminate vectors.S.

Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.

Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros.

Now that the PUSHFRAME and PULLFRAME macros are used only in the swi
entry/exit code, they don't need to be macros. Except that didn't work
and the whole change was reverted.

Remove some unnecessary indirection and jump right to the handler functions.

Use panic rather than printf to "handle" an arm26 address exception
(should never happen on arm32).

Remove the unreferenced DATA() macro.

Remove #include <machine/asmacros.h> from files that don't need it.

MFC 257774, 256760, 262916, 262905, 262918, 262919, 262920, 262921, 262924,
262925, 262929, 262932, 262935, 262940, 262941, 262942, 262948, 262949,
262950

Strip arm/conf/DEFAULTS down to just items that are mandatory for running
the architecture.

Move all the files named foo/common.c to foo/foo_common.c

Initial cut for DTS on the hl201 board.

Add commented out dts for sam9260ek as well as early printf support.

Make clock optional on uart nodes, then back it out ("I don't know what I
was thinking, but it is lame.")

Set the baud rate if it isn't 0

Make at91_soc_id() public.

Properly round at91 resource on unmapping.

Move AT91 AIC related stuff to own file.

Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in
LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32.

Follow r262916 with one more config file that references a renamed common.c

Remove bogus AT91 define that causes compile errors. Most of the defines
for SAM9X are going away soonish anyway (once FDT works), but until
then...

Remove all dregs of a per-thread undefined-exception-mode stack.

Rework the VFP code that handles demand-based save and restore of state.

Always call vfp_discard() on thread death.

When a thread begins life it doesn't own the VFP hardware state on any cpu.

Make undefined exception entry MP-safe.

MFC 262695, 262708, 262709, 262710, 262711, 262728, 262870, 262877, 262880,
262885, 262891, 262903,

imx6: Add a tunable to set the number of active cores, enable SMP by default.

ffec: Fix multicast filtering.

Allwinner a10/a20...
- Add gpio and clock bits for A10/A20's EMAC ethernet controller driver
- EMAC gpio configuration
- EMAC clock activation
- Add Static Random Access Memory controller driver for A10/A20.
A10/A20's SRAM is used by devices, such as CPU, EMAC,
for extra fast memory or as cache.
- Add EMAC 10/100 Ethernet controller driver for A10/A20.
It is available mostly in A10 devices like Hackberry, Marsboard,
Mele A1000, A2000, A100 HTPC, cubieboard1 and A20 device
like cubieboard2.
TX performance can be improved using both channels 0 and 1.
RX performance is poor and needs improvement with the assistance of
external DMA controller in case there
- Add EMAC and SRAM controller entries to FDT.
- Add EMAC device to kernel config files and enable EMAC, SRAM drivers.

OMAP: When calculating the MPU freq, make sure not to overflow.

Vybrid:
- Add driver for Port control and interrupts (PORT).
- Export panel info to DTS
- Reset all the layers before setup first one
- Enable display

nandfs: Slight code reordering to make error branch last.

Add option TMPFS to arm/conf/DEFAULTS, remove it from the few configs
that have it individually. Concensus on freebsd-arm@ is that it should
be included in all ARM kernels.

Fix the arm sys_sigreturn(): its argument is a struct ucontext, not a
struct sigframe containing the struct ucontext.

MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,
r262585, r262587, r262696, r262712

Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c.

aicasm: Don't complain about missing prototypes to ease bootstrap issues.

Vybrid: Add driver for Inter-Integrated Circuit (I2C).

imx6: Initialize the Low Power Mode bits to keep the ARM cores running
during WFI.

All our current ARM multi-core systems have all cores in one package with
a shared L2 cache, reflect that in the common cpu_topo() routine.

mpcore timer: Supply a DELAY() implementation via weak linkage, so that
SoC-specific code can supply a better implementation.

imx6: Add some rudimentary voltage control.

Add an armv7 implementation of cpu_sleep().

Add __used attribute so that the DELAY implementation doesn't get
optimized away as unreferenced, causing linker errors when trying to
resolve the weak reference to the missing function.

MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,
r262482, r262483, r262531,

Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files.

If the L2 cache type is PIPT, pass a physical address for a flush.

Actually set the proper bit to indicate TTB shared memory.

Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support.

Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.

Add the bits needed to run SMP on imx6.

Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.

Minor tweaks to the imx GPT timer

Vybrid enhancements...
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
- Add support for Quartz Module.
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock

MFC r261982, r261987, r262123, r262244, r262278, r262280, r262353, r262354,
r262355, r262419,

Add Vybrid driver for Synchronous Audio Interface (SAI).

Decrease SAI buffer size. Handle eDMA interrupt on running channel only.

Give the physmem fdt helper routines static linkage since no global
definition of them is provided anywhere.

Add imx6 early printf support, wrapped in #if 0 because it's rarely needed.

Add basic cpu frequency control and temperature monitoring to imx6_anatop.

Add the FREEBSD_BOOT_LOADER option so that a loaded DTB passed in from
ubldr will actually get used.

Create a generic IMX6 kernel config, then fix it to have an ident line.

Don't force imx6 bootverbose on anymore, it can be set from ubldr now.

MFC r261938, r261939, r261940, r261944, r261945, r261946, r261947, r261956, r261957, r261983, r261094,
r261955, r261958,

Add a driver to provide access to imx6 on-chip one-time-programmble data.

Make it possible to access the ocotp registers before the ocotp device
is attached, by establishing a temporary mapping of the registers when
necessary.

It turns out Freescale cleverly made the ocotp device compatible across
several different families of SoCs, so move it to the freescale directory
and prefix everything with fsl rather than imx6.

Convert the imx6 sdhci "R1B fix" from a busy-loop in the interrupt handler
to a callout.

Increase the wait time for acquiring the SD bus from 10 to 250ms.

If no compatible cards were found after probing the SD bus, say so.

Add timeout logic to sdhci, separate from the timeouts done by the hardware.

After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA
rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing
any possibility of recovering from the error.

Add a helper routine to depth-search the device tree for a node with a
matching 'compatible' property.

MFC r261803, r261808, r261814, r261815, r261816, r261817, r261818, r261826,
r261848, r261855

On armv6 and later, use the WriteNotRead bit of the fault status register
to decide what protections are required by the faulting access.

Use the right symbols for determining arm architecture. Include the
necessary header file which has the new FAULT_WNR symbol defined in it.

Allow the kernel to be loaded at any 1MiB address. This requirement is
because we use the 1MiB section maps as they only need a single pagetable.

Add function for configuring Vybrid PLL4 (Audio) clock frequency output.

imx6 changes ...

- Fix the definition of the SDHCI_STATE_DAT and SDHCI_STATE_CMD fields,
and add SDHCI_RETUNE_REQUEST. None of these are actually used in the
code yet.

- Write translation code for the SDHCI_PRESENT_STATE register.
Freescale moved some bits around in their version of the register,
adjust things so that the sdhci code sees the standard layout.

- Add standard non-removable and cd-gpios properties to the usdhc
devices. That generates references to gpio devices, so uncomment them
even though there isn't a gpio driver to do anything with them yet.

- Add handling of standard "non-removable" property, and also some
workaround code so that if card detect is wired to a gpio pin, for now
we just treat it the same as non-removable (because there isn't a gpio
driver yet).

- Enable both sdcard slots, but not the sdio-based wifi that we don't
yet have a driver for.

- Remove a couple obsolete function declarations.

MFC r261616, r261639

Remove FreeBSD 6 support from atmel usb controllers.

Add Vybrid drivers for:
- Enhanced Direct Memory Access Controller (eDMA)
- Direct Memory Access Multiplexer (DMAMUX)

MFC r259270

After r266105 ofw_iicbuc.c will be built by default for any kernel which
includes options 'iicbus' and 'fdt'. Remove the (now) unnecessary entries.

MFC r261423, r261424, r261516, r261513, r261562, r261563, r261564, r261565,
r261596, r261606

Add the imx sdhci controller.

Move Open Firmware device root on PowerPC, ARM, and MIPS systems to
a sub-node of nexus (ofwbus) rather than direct attach under nexus. This
fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier.
SPARC is unchanged.

Add the missing ')' at end of sentence. Reword it to use a more common idiom.

Pass the kernel physical address to initarm through the boot param struct.

Make functions only used in vfp.c static, and remove vfp_enable.

Fix __syscall on armeb EABI. As it returns a 64-bit value it needs to
place 32-bit data in r1, not r0. 64-bit data is already packed correctly.

Use abp_physaddr for the physical address over KERNPHYSADDR. This helps us
remove the need to load the kernel at a fixed address.

Remove references to PHYSADDR where it's used only in debugging output.

Dynamically generate the page table. This will allow us to detect the
physical address we are loaded at to change the mapping.

MFC r261411, r261413, r261416:

Add support for Colibri VF50 Evaluation Board.

Add driver for Display Control Unit (DCU4).

Add prototype for tcon_bypass() used by dcu4.
Add register definition.

MFC r261410

Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

MFC r261406, r261409: enhance Vybrid support...

o Expand device tree information
o Export iomuxc (pins) configuration to DTS
o Allow devices to assign clocks in DTS
o Split kernel configuration to chip common and board specific parts.

MFC r261252, r261279, r261304, r261305, r261322, r261336, r261337, r261338,
r261353

Fix the name of the dts file for the HL201...

When mapping an address, the bsh needs the same offset we do for other things.

Add explicit depends on bus_if.h and device_if.h to avoid a
chicken and egg problem in some compilation environments.

Switch to using PAs rather than VAs for the addresses we map for
devices. This is a nop, except for what's reported by atmelbus for the
resources.

Comment cleanups. Move things around for diff reduction against FDT work.

MFC r259728, r260752

Add Freescale i.MX515 vt(9) driver.

MFC r256839, r256948, r256950, r257299, r257414, r258057, r259090

Add configuration for the Freescale i.MX53 Quick Start Board.

Add the Raspberry Pi BSC (I2C compliant) controller driver.

Add Radxa Rock board (by radxa.com) support.

Digi-CCWMX53: enable ffec and uart, USB.

Add support for Freescale Vybrid Family VF600

Move and rename dwc otg driver to more generic one as it appears to work
for rk3188 SoC based board too.

MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,
r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373,
r260374, r260375

Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs.
Correct license statements to reflect the fact that these files were all
derived from sys/arm/mv/bus_space.c.

In pmap_unmapdev(), remember the size, and use that as an argument to
kva_free(), or we'd end up always passing it a size of 0

In pmap_mapdev(), first check whether a static mapping exists,

Convert TI static device mapping to use the new arm_devmap_add_entry(),

Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy.

Eliminate use of fdt_immr_addr(), it's not needed for tegra

Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make
static device mappings.

Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.

Add #include <machine/fdt.h> to a few files that used to get it via pollution

Enable the mv cesa security/crypto device by providing the required property
in the dts source, and adding the right devices to the kernel config.

Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs,
related to setting up static device mappings. Since it was only used by
arm/mv/mv_pci.c, it's now just static functions within that file, plus
one public function that gets called only from arm/mv/mv_machdep.c.

Switch RPi to using arm_devmap_add_entry() to set up static device mapping.

Allow 'no static device mappings' to potentially work.

Don't try to find a static mapping before calling pmap_mapdev(), that logic
is now part of pmap_mapdev() and doesn't need to be duplicated here.

Switch a10 to using arm_devmap_add_entry() to set up static device mapping.

MFC r257702, r257745, r257746, r257747, r257751, r257791, r257793,
r257794, r257795, r257992

Teach nexus(4) about Open Firmware (e.g. FDT) on ARM and MIPS, retiring
fdtbus in most cases.

Make OF_nextprop() work correctly for FDT by using the libfdt
fdt_next_property_offset() API.

Do not panic if pmap_mincore() is called.

An addendum: it is possible, though of questionable utility, for a node
to have no properties at all.
Add definition for the Atheros 8021 gigabit PHY.

Consolidate Apple firmware hacks and improve them by switching on the
presence of mac-io devices in the tree, which uniquely identifies Apple
hardware.

Allow OF_decode_addr() to also be able to map resources on big-endian
devices.

Make tsec work with the device tree present on the RB800.

Be more flexible about which compatible strings to accept. This brings up
the PCI Express bus on the RB800 using the firmware device tree.

Rename the "bare" platform "mpc85xx", which is what it actually is, and
add actual platform probing based on PVR.

MFC r262393 (by ian):

Fix a typo _IMX51_TZICRREG_H_ -> _IMX51_TZICREG_H_ (extra R)

MFC r258779,r258780,r258787,r258822:

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.

Similar to the (1 << 31) case it is not defined to do (2 << 30).

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

MFC r257924:

Apparently with "const uint32_t foo = 0x60;" gcc doesn't consider 'foo'
to be a constant integer suitable for use in a case label, so use #defines.

MFC r257669, r257672, r257673, r257676, r257678:

Call initarm_lastaddr() later in the init sequence, after establishing
static device mappings, rather than as the first of the initializations
that a platform can hook into. This allows a platform to allocate KVA
from the top of the address space downwards for things like static device
mapping, and return the final "last usable address" result after that and
other early init work is done.

Because some platforms were doing work in initarm_lastaddr() that needs to
be done early, add a new initarm_early_init() routine and move the early
init code to that routine on those platforms.

Make PTE_DEVICE a synonym for PTE_NOCACHE on armv4, to make it easier to
share the same code on both architectures.

Add new helper routines for arm static device mapping. The new code
allocates kva space from the top down for the device mappings and builds
entries in an internal table which is automatically used later by
arm_devmap_bootstrap(). The platform code just calls the new
arm_devmap_add_entry() function as many times as it needs to (up to 32
entries allowed; most platforms use 2 or 3 at most).

Remove imx local devmap code and use the essentially identical common
code that got moved from imx_machdep.c to arm/devmap.c.

MFC r257648, r257649, r257660:

Begin reducing code duplication in arm pmap.c and pmap-v6.c by factoring
out common code related to mapping device memory into a new devmap.c file.

Remove the growing duplication of code that used pmap_devmap_find_pa() and
then did some math with the returned results to generate a virtual address,
and likewise in reverse to get a physical address. Now there are a pair
of functions, arm_devmap_vtop() and arm_devmap_ptov(), to do that. The
bus_space_map() implementations are rewritten in terms of these.

Move remaining code and data related to static device mapping into the
new devmap.[ch] files. Emphasize the MD nature of these things by using
the prefix arm_devmap_ on the function and type names (already a few of
these things found their way into MI code, hopefully it will be harder to
do by accident in the future).

MFC r257595: Comments and style(9) only, no functional changes.

MFC r257561:

Bugfix: the attach routine needs to use the same table of fdt compat
strings that the probe routine used.

MFC r257557: Add a missing register definition.

MFC r257483, r257486, r257489:

Add the Soc- / machine-dependent parts of imx6 support.
Add dts source for imx6 SoCs and for Wandboard boards.
Add kernel config for Wandboard.

MFC r257476, r257478:

Revamp the SoC identity numbering scheme to be more in line with the way
Freescale numbers the chips in the ID registers.

Add definitions for the register and data that describes the SoC type.

MFC r257454: Add sdhci driver glue for imx family SoCs.

MFC r257453: Add stubbed-out imx6 support for clocks and power management.

MFC r257452: Add support for the USB PHY on imx6 SoCs.

MFC r257418:

Don't iterate through the bits of the pending interrupt register if the
whole register is zero. Most of the registers will be zero most of the time.

MFC r257413:

Reset the timer interrupt status register at the top rather than bottom of
the interrupt handler. If the event callback starts a new short timeout,
the timer can fire before returning from the event callback, and clearing
the interrupt status after that loses the interrupt and hangs until the
counter wraps. Fixing all of this removes the need for the do-nothing
loop at the top of the handler which really just waited for the counter to
roll over and reach the one-shot count again.

Also add a missing return(0) in the periodic timer start case.

MFC r257407:

Expand the list of compatible devices this driver works with. Increase
the target frequency from 1 to 10 MHz because these SoCs are plenty fast
enough to benefit from the extra event timer resolution.

MFC r257383, r257384:

Add some bare-bones support for enabling usb and usbphy clocks.

Add a "no-op" USB PHY driver for imx-family SoCs.

MFC r257199, r257200, r257217:

Remove all #include <machine/pmap.h> from arm code. It's already
included by vm/pmap.h, which is a prerequisite for arm/machine/pmap.h
so there's no reason to ever include it directly.

Remove #include <machine/frame.h> from all the arm code that doesn't
really need it. That would be almost everywhere it was included. Add
it in a couple files that really do need it and were previously getting
it by accident via another header.

Remove the last dregs of trapframe_t. It turns out only arm was using
this type, so remove it to make arm code more consistant with other
platforms.

MFC r257197:

Maximize available kva space by doing static device mapping from the top
of the address space downwards, and then returning the lowest mapped
device address from initarm_lastaddr(). Premap most of the device's
on-chip peripherals.

MFC r256806, r256919, r257167:

Add a driver for the Freescale Fast Ethernet Controller found on various
Freescale SoCs including the i.MX series. This also works for the newer
SoCs with the ENET gigabit controller, but doesn't use any of the new
hardware features other than enabling gigabit speed.

Mask out non-address bits in the mac address register, for proper
detection of an all-zeroes address. Also remove a misplaced return.

Switch to using ofw_bus_search_compatible() table-driven compat lookup.
Add compat strings for Freescale Vybrid family SoCs.

MFC r256804:

Switch to using the standard uart console driver instead of the special
driver for early boot debugging.

MFC r256774:

Clock divisors 0-3 correspond to dividing by 1-4, so add 1 before dividing.

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Revert accidental commit.

Initial support for the Digi ConnectCore(c) i.MX53 / Wi-i.MX53 boards.

There are many drivers missing, but we can reach single user mode now.

Hardware graciously donated by Douglas Beattie.

Rename imx_machdep.c to imx51_machdep.c, because it contains hardware
addresses which are specific to the imx51 chips.

Add imx6 compatibility and make the driver work for any clock frequency.

There are still a couple references to imx51 ccm driver functions that will
need to be changed after an imx6 ccm driver is written.

Reviewed by: ray

Tweak the imx debug console code so that it works with multiple SoCs.

Instead of hard-coding the uart register addresses for the imx51, use
a variable that defaults to the imx51 address. When debugging another
imx-family SoC, the variable can be set early in initarm() to provide
full console/printf support for debugging early boot.

Rename the existing std.imx and imx.files to std.imx51 and files.imx51, to
pave the way for adding imx6 support.

Update copyright date.

Fix undefined behaviour in several gpio_pin_setflags() routines (under
sys/arm and sys/mips), squelching the clang 3.3 warnings about this.

Noticed by: tinderbox and many irate spectators
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
PR: kern/177759
MFC after: 3 days

Integrate Efika MX project back to home.

Sponsored by: The FreeBSD Foundation