vf_dcu4.c revision 266155
180708Sjake/*- 280708Sjake * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3223126Smarius * All rights reserved. 480708Sjake * 580708Sjake * Redistribution and use in source and binary forms, with or without 680708Sjake * modification, are permitted provided that the following conditions 780708Sjake * are met: 880708Sjake * 1. Redistributions of source code must retain the above copyright 980708Sjake * notice, this list of conditions and the following disclaimer. 1080708Sjake * 2. Redistributions in binary form must reproduce the above copyright 1180708Sjake * notice, this list of conditions and the following disclaimer in the 1280708Sjake * documentation and/or other materials provided with the distribution. 1380708Sjake * 1480708Sjake * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1581334Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1680708Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1780708Sjake * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1881334Sobrien * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1980708Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2080708Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2180708Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2280708Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2380708Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2480708Sjake * SUCH DAMAGE. 2580708Sjake */ 2680708Sjake 2780708Sjake/* 2880708Sjake * Vybrid Family Display Control Unit (DCU4) 2980708Sjake * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013 3080708Sjake */ 3180708Sjake 3280708Sjake#include <sys/cdefs.h> 33183142Smarius__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/vybrid/vf_dcu4.c 266155 2014-05-15 16:23:24Z ian $"); 34183142Smarius 35182730Smarius#include <sys/param.h> 36182730Smarius#include <sys/systm.h> 37182730Smarius#include <sys/bus.h> 38182730Smarius#include <sys/kernel.h> 3989051Sjake#include <sys/module.h> 4089051Sjake#include <sys/malloc.h> 4189051Sjake#include <sys/rman.h> 42222813Sattilio#include <sys/timeet.h> 43209695Smarius#include <sys/timetc.h> 44209695Smarius#include <sys/watchdog.h> 45245850Smarius#include <sys/fbio.h> 46209695Smarius#include <sys/consio.h> 4791157Sjake#include <sys/eventhandler.h> 48169730Skan 4991617Sjake#include <dev/fdt/fdt_common.h> 5091157Sjake#include <dev/ofw/openfirm.h> 51170846Smarius#include <dev/ofw/ofw_bus.h> 52170846Smarius#include <dev/ofw/ofw_bus_subr.h> 53170846Smarius 54170846Smarius#include <dev/vt/vt.h> 55170846Smarius#include <dev/vt/colors/vt_termcolors.h> 56170846Smarius 5789051Sjake#include <machine/bus.h> 58169796Smarius#include <machine/fdt.h> 59170846Smarius#include <machine/cpu.h> 60169796Smarius#include <machine/intr.h> 6189051Sjake 6289051Sjake#include "fb_if.h" 63178048Smarius 64210601Smav#include <arm/freescale/vybrid/vf_common.h> 6589051Sjake 66196196Sattilio#define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */ 6789051Sjake#define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */ 68135943Skensmith#define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */ 6989051Sjake#define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */ 7089051Sjake#define DCU_DCU_MODE 0x010 /* DCU4 Mode */ 7191783Sjake#define DCU_MODE_M 0x3 7289051Sjake#define DCU_MODE_S 0 7389051Sjake#define DCU_MODE_NORMAL 0x1 7491783Sjake#define DCU_MODE_TEST 0x2 7591617Sjake#define DCU_MODE_COLBAR 0x3 76182730Smarius#define RASTER_EN (1 << 14) /* Raster scan of pixel data */ 7791617Sjake#define DCU_BGND 0x014 /* Background */ 7891617Sjake#define DCU_DISP_SIZE 0x018 /* Display Size */ 7989051Sjake#define DELTA_M 0x7ff 8089051Sjake#define DELTA_Y_S 16 8197001Sjake#define DELTA_X_S 0 82222813Sattilio#define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */ 83113238Sjake#define BP_H_SHIFT 22 8497001Sjake#define PW_H_SHIFT 11 8597001Sjake#define FP_H_SHIFT 0 86211071Smarius#define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */ 87222813Sattilio#define BP_V_SHIFT 22 88211071Smarius#define PW_V_SHIFT 11 89211071Smarius#define FP_V_SHIFT 0 90211071Smarius#define DCU_SYNPOL 0x024 /* Synchronize Polarity */ 9189051Sjake#define INV_HS (1 << 0) 92222813Sattilio#define INV_VS (1 << 1) 9391783Sjake#define DCU_THRESHOLD 0x028 /* Threshold */ 9489051Sjake#define LS_BF_VS_SHIFT 16 9589051Sjake#define OUT_BUF_HIGH_SHIFT 8 9689051Sjake#define OUT_BUF_LOW_SHIFT 0 9789051Sjake#define DCU_INT_STATUS 0x02C /* Interrupt Status */ 9889051Sjake#define DCU_INT_MASK 0x030 /* Interrupt Mask */ 9989051Sjake#define DCU_COLBAR_1 0x034 /* COLBAR_1 */ 10089051Sjake#define DCU_COLBAR_2 0x038 /* COLBAR_2 */ 101152022Sjhb#define DCU_COLBAR_3 0x03C /* COLBAR_3 */ 102152022Sjhb#define DCU_COLBAR_4 0x040 /* COLBAR_4 */ 10389051Sjake#define DCU_COLBAR_5 0x044 /* COLBAR_5 */ 10492199Sjake#define DCU_COLBAR_6 0x048 /* COLBAR_6 */ 10589051Sjake#define DCU_COLBAR_7 0x04C /* COLBAR_7 */ 106222813Sattilio#define DCU_COLBAR_8 0x050 /* COLBAR_8 */ 107170846Smarius#define DCU_DIV_RATIO 0x054 /* Divide Ratio */ 108211050Smarius#define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */ 109211050Smarius#define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */ 11089051Sjake#define DCU_CRC_VAL 0x060 /* CRC Value */ 111204152Smarius#define DCU_PDI_STATUS 0x064 /* PDI Status */ 11291617Sjake#define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */ 113108187Sjake#define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */ 114211071Smarius#define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */ 115108187Sjake#define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */ 11689051Sjake#define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */ 11791617Sjake#define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */ 11891617Sjake#define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */ 11991617Sjake#define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */ 12091617Sjake#define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */ 12191617Sjake#define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */ 12291617Sjake#define DCU_LUMA_COMP 0x0A0 /* LUMA Component */ 12391617Sjake#define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */ 124112399Sjake#define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */ 125112399Sjake#define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */ 126112399Sjake#define DCU_CRC_POS 0x0B0 /* CRC Position */ 127112399Sjake#define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ 12889051Sjake#define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ 129211071Smarius#define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ 130211071Smarius#define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ 131211071Smarius#define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ 132211071Smarius#define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ 13389051Sjake#define DCU_UPDATE_MODE 0x0CC /* Update Mode */ 13489051Sjake#define READREG (1 << 30) 13589051Sjake#define MODE (1 << 31) 13689051Sjake#define DCU_UNDERRUN 0x0D0 /* Underrun */ 137183142Smarius#define DCU_GLBL_PROTECT 0x100 /* Global Protection */ 138183142Smarius#define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ 139183142Smarius#define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ 140223126Smarius#define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ 14189051Sjake#define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ 142223126Smarius#define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ 143223126Smarius#define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ 144223126Smarius#define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ 145183142Smarius 146183142Smarius/* Control Descriptor */ 147183142Smarius#define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 148222813Sattilio#define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) 149183142Smarius#define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) 150183142Smarius#define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) 151183142Smarius#define TRANS_SHIFT 20 152183142Smarius#define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) 153183142Smarius#define BPP_MASK 0xf /* Bit per pixel Mask */ 154210939Sjhb#define BPP_SHIFT 16 /* Bit per pixel Shift */ 155210939Sjhb#define BPP24 0x5 156210939Sjhb#define EN_LAYER (1 << 31) /* Enable the layer */ 157210939Sjhb#define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) 158211050Smarius#define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) 159210939Sjhb#define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) 160210939Sjhb#define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) 161108187Sjake#define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) 162108187Sjake 16397001Sjake#define DISPLAY_WIDTH 480 164113238Sjake#define DISPLAY_HEIGHT 272 16597001Sjake 16697001Sjakestruct dcu_softc { 16797001Sjake struct resource *res[2]; 16897001Sjake bus_space_tag_t bst; 16997001Sjake bus_space_handle_t bsh; 170209695Smarius void *ih; 17197001Sjake device_t dev; 172239864Smarius device_t sc_fbd; /* fbd child */ 17397001Sjake struct fb_info sc_info; 174223126Smarius}; 17597001Sjake 176223126Smariusstatic struct resource_spec dcu_spec[] = { 17797001Sjake { SYS_RES_MEMORY, 0, RF_ACTIVE }, 17897001Sjake { SYS_RES_IRQ, 0, RF_ACTIVE }, 17997001Sjake { -1, 0 } 18097001Sjake}; 181113238Sjake 18297001Sjakestatic int 18397001Sjakedcu_probe(device_t dev) 18497001Sjake{ 18597001Sjake 18697001Sjake if (!ofw_bus_status_okay(dev)) 187209695Smarius return (ENXIO); 18897001Sjake 189239864Smarius if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4")) 19097001Sjake return (ENXIO); 191223126Smarius 19297001Sjake device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)"); 193223126Smarius return (BUS_PROBE_DEFAULT); 19497001Sjake} 19597001Sjake 19697001Sjakestatic void 19789051Sjakedcu_intr(void *arg) 198211071Smarius{ 199211071Smarius struct dcu_softc *sc; 200211071Smarius int reg; 201211071Smarius 202211071Smarius sc = arg; 203211071Smarius 204211071Smarius /* Ack interrupts */ 205211071Smarius reg = READ4(sc, DCU_INT_STATUS); 206245850Smarius WRITE4(sc, DCU_INT_STATUS, reg); 207223126Smarius 208211071Smarius /* TODO interrupt handler */ 209211071Smarius} 210211071Smarius 211211071Smariusstatic int 212211071Smariusdcu_init(struct dcu_softc *sc) 213211071Smarius{ 21491783Sjake int reg; 21589051Sjake 21689051Sjake /* Configure DCU */ 217222813Sattilio reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 21889051Sjake reg |= (sc->sc_info.fb_width / 16); 21991783Sjake WRITE4(sc, DCU_DISP_SIZE, reg); 22089051Sjake 221209695Smarius /* TODO: export panel info to FDT */ 222222813Sattilio 223223126Smarius reg = (2 << BP_H_SHIFT); 224223126Smarius reg |= (41 << PW_H_SHIFT); 225222813Sattilio reg |= (2 << FP_H_SHIFT); 226209695Smarius WRITE4(sc, DCU_HSYN_PARA, reg); 22791783Sjake 228209695Smarius reg = (2 << BP_V_SHIFT); 22989051Sjake reg |= (10 << PW_V_SHIFT); 230239864Smarius reg |= (2 << FP_V_SHIFT); 231222813Sattilio WRITE4(sc, DCU_VSYN_PARA, reg); 23291783Sjake 23391783Sjake WRITE4(sc, DCU_BGND, 0); 23491783Sjake WRITE4(sc, DCU_DIV_RATIO, 30); 23592199Sjake 23689051Sjake reg = (INV_VS | INV_HS); 23789051Sjake WRITE4(sc, DCU_SYNPOL, reg); 23889051Sjake 239100718Sjake reg = (0x3 << LS_BF_VS_SHIFT); 24089051Sjake reg |= (0x78 << OUT_BUF_HIGH_SHIFT); 24189051Sjake reg |= (0 << OUT_BUF_LOW_SHIFT); 242222813Sattilio WRITE4(sc, DCU_THRESHOLD, reg); 24389051Sjake 24491783Sjake /* Mask all the interrupts */ 24589051Sjake WRITE4(sc, DCU_INT_MASK, 0xffffffff); 246209695Smarius 247222813Sattilio /* Setup first layer */ 248223126Smarius reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 249223126Smarius WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); 250222813Sattilio WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); 251209695Smarius WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase); 25291783Sjake reg = (BPP24 << BPP_SHIFT); 253209695Smarius reg |= EN_LAYER; 25489051Sjake reg |= (0xFF << TRANS_SHIFT); /* completely opaque */ 255239864Smarius WRITE4(sc, DCU_CTRLDESCLn_4(0), reg); 256222813Sattilio WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff); 25791783Sjake WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0); 25889051Sjake WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0); 25991783Sjake WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0); 26092199Sjake WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0); 26189051Sjake 26289051Sjake /* Enable DCU in normal mode */ 26389051Sjake reg = READ4(sc, DCU_DCU_MODE); 26491783Sjake reg &= ~(DCU_MODE_M << DCU_MODE_S); 26589051Sjake reg |= (DCU_MODE_NORMAL << DCU_MODE_S); 26689051Sjake reg |= (RASTER_EN); 267222813Sattilio WRITE4(sc, DCU_DCU_MODE, reg); 26889051Sjake WRITE4(sc, DCU_UPDATE_MODE, READREG); 26991783Sjake 27089051Sjake return (0); 271209695Smarius} 272222813Sattilio 273223126Smariusstatic int 274223126Smariusdcu_attach(device_t dev) 275222813Sattilio{ 276209695Smarius struct dcu_softc *sc; 27791783Sjake int err; 278209695Smarius 27989051Sjake sc = device_get_softc(dev); 280239864Smarius 281222813Sattilio if (bus_alloc_resources(dev, dcu_spec, sc->res)) { 28291783Sjake device_printf(dev, "could not allocate resources\n"); 28389051Sjake return (ENXIO); 28489051Sjake } 285211050Smarius 286211050Smarius /* Memory interface */ 28792199Sjake sc->bst = rman_get_bustag(sc->res[0]); 28889051Sjake sc->bsh = rman_get_bushandle(sc->res[0]); 28989051Sjake 29089051Sjake /* Setup interrupt handler */ 29189051Sjake err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 29289051Sjake NULL, dcu_intr, sc, &sc->ih); 293222813Sattilio if (err) { 29489051Sjake device_printf(dev, "Unable to alloc interrupt resource.\n"); 29592199Sjake return (ENXIO); 296222813Sattilio } 29791617Sjake 298239864Smarius /* Bypass timing control (used for raw lcd panels) */ 299209695Smarius tcon_bypass(); 30089051Sjake 30189051Sjake sc->sc_info.fb_width = DISPLAY_WIDTH; 30289051Sjake sc->sc_info.fb_height = DISPLAY_HEIGHT; 303108187Sjake sc->sc_info.fb_stride = sc->sc_info.fb_width * 3; 30491783Sjake sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24; 305183142Smarius sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 306183142Smarius sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 30789051Sjake M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 30889051Sjake sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 309183142Smarius 310183142Smarius#if 0 31189051Sjake printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 312209695Smarius sc->sc_info.fb_stride); 31397001Sjake printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase); 314169796Smarius#endif 31597001Sjake 31697001Sjake memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size); 31797001Sjake 31897001Sjake dcu_init(sc); 319209695Smarius 32097001Sjake sc->sc_info.fb_name = device_get_nameunit(dev); 321169796Smarius 32297001Sjake /* Ask newbus to attach framebuffer device to me. */ 32397001Sjake sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 32497001Sjake if (sc->sc_fbd == NULL) 32597001Sjake device_printf(dev, "Can't attach fbd device\n"); 326211071Smarius 327211071Smarius if (device_probe_and_attach(sc->sc_fbd) != 0) { 328211071Smarius device_printf(sc->dev, "Failed to attach fbd device\n"); 329211071Smarius } 330211071Smarius 331211071Smarius return (0); 332211071Smarius} 333209695Smarius 33489051Sjakestatic struct fb_info * 335169796Smariusdcu4_fb_getinfo(device_t dev) 33689051Sjake{ 33789051Sjake struct dcu_softc *sc = device_get_softc(dev); 33889051Sjake 33989051Sjake return (&sc->sc_info); 340209695Smarius} 34189051Sjake 342169796Smariusstatic device_method_t dcu_methods[] = { 34389051Sjake DEVMETHOD(device_probe, dcu_probe), 34489051Sjake DEVMETHOD(device_attach, dcu_attach), 34589051Sjake 34689051Sjake /* Framebuffer service methods */ 347209695Smarius DEVMETHOD(fb_getinfo, dcu4_fb_getinfo), 348209695Smarius { 0, 0 } 34989051Sjake}; 350169796Smarius 35189051Sjakestatic driver_t dcu_driver = { 35289051Sjake "fb", 35389051Sjake dcu_methods, 35489051Sjake sizeof(struct dcu_softc), 355239864Smarius}; 35689051Sjake 357169796Smariusstatic devclass_t dcu_devclass; 35889051Sjake 35989051SjakeDRIVER_MODULE(fb, simplebus, dcu_driver, dcu_devclass, 0, 0); 360183142Smarius