imx51_ipuv3_fbd.c revision 266365
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Oleksandr Rybalko 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx51_ipuv3_fbd.c 266365 2014-05-17 22:00:10Z ian $"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bio.h> 37#include <sys/bus.h> 38#include <sys/conf.h> 39#include <sys/endian.h> 40#include <sys/kernel.h> 41#include <sys/kthread.h> 42#include <sys/lock.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/mutex.h> 46#include <sys/queue.h> 47#include <sys/resource.h> 48#include <sys/rman.h> 49#include <sys/time.h> 50#include <sys/timetc.h> 51#include <sys/fbio.h> 52#include <sys/consio.h> 53#include <sys/eventhandler.h> 54 55#include <sys/kdb.h> 56 57#include <machine/bus.h> 58#include <machine/cpu.h> 59#include <machine/cpufunc.h> 60#include <machine/fdt.h> 61#include <machine/resource.h> 62#include <machine/frame.h> 63#include <machine/intr.h> 64 65#include <dev/fdt/fdt_common.h> 66#include <dev/ofw/ofw_bus.h> 67#include <dev/ofw/ofw_bus_subr.h> 68 69#include <dev/vt/vt.h> 70#include <dev/vt/colors/vt_termcolors.h> 71 72#include <arm/freescale/imx/imx51_ccmvar.h> 73 74#include <arm/freescale/imx/imx51_ipuv3reg.h> 75 76#include "fb_if.h" 77 78#define IMX51_IPU_HSP_CLOCK 665000000 79 80struct ipu3sc_softc { 81 device_t dev; 82 device_t sc_fbd; /* fbd child */ 83 struct fb_info sc_info; 84 85 bus_space_tag_t iot; 86 bus_space_handle_t ioh; 87 bus_space_handle_t cm_ioh; 88 bus_space_handle_t dp_ioh; 89 bus_space_handle_t di0_ioh; 90 bus_space_handle_t di1_ioh; 91 bus_space_handle_t dctmpl_ioh; 92 bus_space_handle_t dc_ioh; 93 bus_space_handle_t dmfc_ioh; 94 bus_space_handle_t idmac_ioh; 95 bus_space_handle_t cpmem_ioh; 96}; 97 98static struct ipu3sc_softc *ipu3sc_softc; 99 100#define IPUV3_READ(ipuv3, module, reg) \ 101 bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) 102#define IPUV3_WRITE(ipuv3, module, reg, val) \ 103 bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) 104 105#define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40) 106#define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20) 107#define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000) 108#define IMX_IPU_DP0 0 109#define IMX_IPU_DP1 1 110#define CPMEM_CHANNEL(_dp, _ch, _w) \ 111 (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \ 112 CPMEM_WORD_OFFSET(_w)) 113#define CPMEM_OFFSET(_dp, _ch, _w, _o) \ 114 (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o)) 115 116static int ipu3_fb_probe(device_t); 117static int ipu3_fb_attach(device_t); 118 119static void 120ipu3_fb_init(struct ipu3sc_softc *sc) 121{ 122 uint64_t w0sh96; 123 uint32_t w1sh96; 124 125 /* FW W0[137:125] - 96 = [41:29] */ 126 /* FH W0[149:138] - 96 = [53:42] */ 127 w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16)); 128 w0sh96 <<= 32; 129 w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12)); 130 131 sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1; 132 sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1; 133 134 /* SLY W1[115:102] - 96 = [19:6] */ 135 w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12)); 136 sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1; 137 138 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 139 sc->sc_info.fb_stride); 140 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 141 142 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 143 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 144 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 145 146 /* DP1 + config_ch_23 + word_2 */ 147 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0), 148 (((uint32_t)sc->sc_info.fb_pbase >> 3) | 149 (((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff); 150 151 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4), 152 (((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff); 153 154 /* XXX: fetch or set it from/to IPU. */ 155 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride / 156 sc->sc_info.fb_width * 8; 157} 158 159/* Use own color map, because of different RGB offset. */ 160static int 161ipu3_fb_init_cmap(uint32_t *cmap, int bytespp) 162{ 163 164 switch (bytespp) { 165 case 8: 166 return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 167 0x7, 5, 0x7, 2, 0x3, 0)); 168 case 15: 169 return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 170 0x1f, 10, 0x1f, 5, 0x1f, 0)); 171 case 16: 172 return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 173 0x1f, 11, 0x3f, 5, 0x1f, 0)); 174 case 24: 175 case 32: /* Ignore alpha. */ 176 return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 177 0xff, 16, 0xff, 8, 0xff, 0)); 178 default: 179 return (1); 180 } 181} 182 183static int 184ipu3_fb_probe(device_t dev) 185{ 186 187 if (!ofw_bus_status_okay(dev)) 188 return (ENXIO); 189 190 if (!ofw_bus_is_compatible(dev, "fsl,ipu3")) 191 return (ENXIO); 192 193 device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)"); 194 195 return (BUS_PROBE_DEFAULT); 196} 197 198static int 199ipu3_fb_attach(device_t dev) 200{ 201 struct ipu3sc_softc *sc = device_get_softc(dev); 202 bus_space_tag_t iot; 203 bus_space_handle_t ioh; 204 phandle_t node; 205 pcell_t reg; 206 int err; 207 uintptr_t base; 208 209 ipu3sc_softc = sc; 210 211 if (bootverbose) 212 device_printf(dev, "clock gate status is %d\n", 213 imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); 214 215 sc->dev = dev; 216 217 sc = device_get_softc(dev); 218 sc->iot = iot = fdtbus_bs_tag; 219 220 /* 221 * Retrieve the device address based on the start address in the 222 * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register 223 * address, so we just subtract IPU_CM_BASE to get the offset at which 224 * the IPU device was memory mapped. 225 * On i.MX53, the offset is 0. 226 */ 227 node = ofw_bus_get_node(dev); 228 if ((OF_getprop(node, "reg", ®, sizeof(reg))) <= 0) 229 base = 0; 230 else 231 base = fdt32_to_cpu(reg) - IPU_CM_BASE(0); 232 /* map controller registers */ 233 err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); 234 if (err) 235 goto fail_retarn_cm; 236 sc->cm_ioh = ioh; 237 238 /* map Display Multi FIFO Controller registers */ 239 err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh); 240 if (err) 241 goto fail_retarn_dmfc; 242 sc->dmfc_ioh = ioh; 243 244 /* map Display Interface 0 registers */ 245 err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh); 246 if (err) 247 goto fail_retarn_di0; 248 sc->di0_ioh = ioh; 249 250 /* map Display Interface 1 registers */ 251 err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh); 252 if (err) 253 goto fail_retarn_di1; 254 sc->di1_ioh = ioh; 255 256 /* map Display Processor registers */ 257 err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh); 258 if (err) 259 goto fail_retarn_dp; 260 sc->dp_ioh = ioh; 261 262 /* map Display Controller registers */ 263 err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh); 264 if (err) 265 goto fail_retarn_dc; 266 sc->dc_ioh = ioh; 267 268 /* map Image DMA Controller registers */ 269 err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0, 270 &ioh); 271 if (err) 272 goto fail_retarn_idmac; 273 sc->idmac_ioh = ioh; 274 275 /* map CPMEM registers */ 276 err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0, 277 &ioh); 278 if (err) 279 goto fail_retarn_cpmem; 280 sc->cpmem_ioh = ioh; 281 282 /* map DCTEMPL registers */ 283 err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0, 284 &ioh); 285 if (err) 286 goto fail_retarn_dctmpl; 287 sc->dctmpl_ioh = ioh; 288 289#ifdef notyet 290 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, 291 ipuv3intr, sc); 292 if (sc->ih == NULL) { 293 device_printf(sc->dev, 294 "unable to establish interrupt at irq %d\n", 295 IMX51_INT_IPUV3); 296 return (ENXIO); 297 } 298#endif 299 300 /* 301 * We have to wait until interrupts are enabled. 302 * Mailbox relies on it to get data from VideoCore 303 */ 304 ipu3_fb_init(sc); 305 306 sc->sc_info.fb_name = device_get_nameunit(dev); 307 308 ipu3_fb_init_cmap(sc->sc_info.fb_cmap, sc->sc_info.fb_depth); 309 sc->sc_info.fb_cmsize = 16; 310 311 /* Ask newbus to attach framebuffer device to me. */ 312 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 313 if (sc->sc_fbd == NULL) 314 device_printf(dev, "Can't attach fbd device\n"); 315 316 return (bus_generic_attach(dev)); 317 318fail_retarn_dctmpl: 319 bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); 320fail_retarn_cpmem: 321 bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); 322fail_retarn_idmac: 323 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); 324fail_retarn_dp: 325 bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); 326fail_retarn_dc: 327 bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE); 328fail_retarn_di1: 329 bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); 330fail_retarn_di0: 331 bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); 332fail_retarn_dmfc: 333 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); 334fail_retarn_cm: 335 device_printf(sc->dev, 336 "failed to map registers (errno=%d)\n", err); 337 return (err); 338} 339 340static struct fb_info * 341ipu3_fb_getinfo(device_t dev) 342{ 343 struct ipu3sc_softc *sc = device_get_softc(dev); 344 345 return (&sc->sc_info); 346} 347 348static device_method_t ipu3_fb_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, ipu3_fb_probe), 351 DEVMETHOD(device_attach, ipu3_fb_attach), 352 353 /* Framebuffer service methods */ 354 DEVMETHOD(fb_getinfo, ipu3_fb_getinfo), 355 { 0, 0 } 356}; 357 358static devclass_t ipu3_fb_devclass; 359 360static driver_t ipu3_fb_driver = { 361 "fb", 362 ipu3_fb_methods, 363 sizeof(struct ipu3sc_softc), 364}; 365 366DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0); 367