xhci_pci.c revision 278278 
1/*-
2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/10/sys/dev/usb/controller/xhci_pci.c 278278 2015-02-05 20:03:02Z hselasky $");
28
29#include <sys/stdint.h>
30#include <sys/stddef.h>
31#include <sys/param.h>
32#include <sys/queue.h>
33#include <sys/types.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/module.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/condvar.h>
41#include <sys/sysctl.h>
42#include <sys/sx.h>
43#include <sys/unistd.h>
44#include <sys/callout.h>
45#include <sys/malloc.h>
46#include <sys/priv.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50
51#include <dev/usb/usb_core.h>
52#include <dev/usb/usb_busdma.h>
53#include <dev/usb/usb_process.h>
54#include <dev/usb/usb_util.h>
55
56#include <dev/usb/usb_controller.h>
57#include <dev/usb/usb_bus.h>
58#include <dev/usb/usb_pci.h>
59#include <dev/usb/controller/xhci.h>
60#include <dev/usb/controller/xhcireg.h>
61#include "usb_if.h"
62
63static device_probe_t xhci_pci_probe;
64static device_attach_t xhci_pci_attach;
65static device_detach_t xhci_pci_detach;
66static usb_take_controller_t xhci_pci_take_controller;
67
68static device_method_t xhci_device_methods[] = {
69	/* device interface */
70	DEVMETHOD(device_probe, xhci_pci_probe),
71	DEVMETHOD(device_attach, xhci_pci_attach),
72	DEVMETHOD(device_detach, xhci_pci_detach),
73	DEVMETHOD(device_suspend, bus_generic_suspend),
74	DEVMETHOD(device_resume, bus_generic_resume),
75	DEVMETHOD(device_shutdown, bus_generic_shutdown),
76	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
77
78	DEVMETHOD_END
79};
80
81static driver_t xhci_driver = {
82	.name = "xhci",
83	.methods = xhci_device_methods,
84	.size = sizeof(struct xhci_softc),
85};
86
87static devclass_t xhci_devclass;
88
89DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, 0, 0);
90MODULE_DEPEND(xhci, usb, 1, 1, 1);
91
92
93static const char *
94xhci_pci_match(device_t self)
95{
96	uint32_t device_id = pci_get_devid(self);
97
98	switch (device_id) {
99	case 0x01941033:
100		return ("NEC uPD720200 USB 3.0 controller");
101
102	case 0x10421b21:
103		return ("ASMedia ASM1042 USB 3.0 controller");
104
105	case 0x0f358086:
106		return ("Intel Intel BayTrail USB 3.0 controller");
107	case 0x9c318086:
108	case 0x1e318086:
109		return ("Intel Panther Point USB 3.0 controller");
110	case 0x8c318086:
111		return ("Intel Lynx Point USB 3.0 controller");
112	case 0x8cb18086:
113		return ("Intel Wildcat Point USB 3.0 controller");
114
115	default:
116		break;
117	}
118
119	if ((pci_get_class(self) == PCIC_SERIALBUS)
120	    && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
121	    && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
122		return ("XHCI (generic) USB 3.0 controller");
123	}
124	return (NULL);			/* dunno */
125}
126
127static int
128xhci_pci_probe(device_t self)
129{
130	const char *desc = xhci_pci_match(self);
131
132	if (desc) {
133		device_set_desc(self, desc);
134		return (0);
135	} else {
136		return (ENXIO);
137	}
138}
139
140static int xhci_use_msi = 1;
141TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
142
143static void
144xhci_interrupt_poll(void *_sc)
145{
146	struct xhci_softc *sc = _sc;
147	USB_BUS_UNLOCK(&sc->sc_bus);
148	xhci_interrupt(sc);
149	USB_BUS_LOCK(&sc->sc_bus);
150	usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
151}
152
153static int
154xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
155{
156	uint32_t temp;
157	uint32_t usb3_mask;
158	uint32_t usb2_mask;
159
160	temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
161	    pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
162
163	temp |= set;
164	temp &= ~clear;
165
166	/* Don't set bits which the hardware doesn't support */
167	usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
168	usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
169
170	pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
171	pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
172
173	device_printf(self, "Port routing mask set to 0x%08x\n", temp);
174
175	return (0);
176}
177
178static int
179xhci_pci_attach(device_t self)
180{
181	struct xhci_softc *sc = device_get_softc(self);
182	int count, err, rid;
183
184	rid = PCI_XHCI_CBMEM;
185	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
186	    RF_ACTIVE);
187	if (!sc->sc_io_res) {
188		device_printf(self, "Could not map memory\n");
189		return (ENOMEM);
190	}
191	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
192	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
193	sc->sc_io_size = rman_get_size(sc->sc_io_res);
194
195	if (xhci_init(sc, self)) {
196		device_printf(self, "Could not initialize softc\n");
197		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
198		    sc->sc_io_res);
199		return (ENXIO);
200	}
201
202	pci_enable_busmaster(self);
203
204	usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
205
206	rid = 0;
207	if (xhci_use_msi) {
208		count = 1;
209		if (pci_alloc_msi(self, &count) == 0) {
210			if (bootverbose)
211				device_printf(self, "MSI enabled\n");
212			rid = 1;
213		}
214	}
215	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
216	    RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
217	if (sc->sc_irq_res == NULL) {
218		pci_release_msi(self);
219		device_printf(self, "Could not allocate IRQ\n");
220		/* goto error; FALLTHROUGH - use polling */
221	}
222	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
223	if (sc->sc_bus.bdev == NULL) {
224		device_printf(self, "Could not add USB device\n");
225		goto error;
226	}
227	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
228
229	sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
230
231	if (sc->sc_irq_res != NULL) {
232		err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
233		    NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
234		if (err != 0) {
235			bus_release_resource(self, SYS_RES_IRQ,
236			    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
237			sc->sc_irq_res = NULL;
238			pci_release_msi(self);
239			device_printf(self, "Could not setup IRQ, err=%d\n", err);
240			sc->sc_intr_hdl = NULL;
241		}
242	}
243	if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
244		if (xhci_use_polling() != 0) {
245			device_printf(self, "Interrupt polling at %dHz\n", hz);
246			USB_BUS_LOCK(&sc->sc_bus);
247			xhci_interrupt_poll(sc);
248			USB_BUS_UNLOCK(&sc->sc_bus);
249		} else
250			goto error;
251	}
252
253	/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
254	switch (pci_get_devid(self)) {
255	case 0x0f358086:	/* BayTrail */
256	case 0x9c318086:	/* Panther Point */
257	case 0x1e318086:	/* Panther Point */
258	case 0x8c318086:	/* Lynx Point */
259	case 0x8cb18086:	/* Wildcat Point */
260		sc->sc_port_route = &xhci_pci_port_route;
261		sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
262		break;
263	default:
264		break;
265	}
266
267	xhci_pci_take_controller(self);
268
269	err = xhci_halt_controller(sc);
270
271	if (err == 0)
272		err = xhci_start_controller(sc);
273
274	if (err == 0)
275		err = device_probe_and_attach(sc->sc_bus.bdev);
276
277	if (err) {
278		device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
279		goto error;
280	}
281	return (0);
282
283error:
284	xhci_pci_detach(self);
285	return (ENXIO);
286}
287
288static int
289xhci_pci_detach(device_t self)
290{
291	struct xhci_softc *sc = device_get_softc(self);
292	device_t bdev;
293
294	if (sc->sc_bus.bdev != NULL) {
295		bdev = sc->sc_bus.bdev;
296		device_detach(bdev);
297		device_delete_child(self, bdev);
298	}
299	/* during module unload there are lots of children leftover */
300	device_delete_children(self);
301
302	usb_callout_drain(&sc->sc_callout);
303	xhci_halt_controller(sc);
304
305	pci_disable_busmaster(self);
306
307	if (sc->sc_irq_res && sc->sc_intr_hdl) {
308		bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
309		sc->sc_intr_hdl = NULL;
310	}
311	if (sc->sc_irq_res) {
312		bus_release_resource(self, SYS_RES_IRQ,
313		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
314		sc->sc_irq_res = NULL;
315		pci_release_msi(self);
316	}
317	if (sc->sc_io_res) {
318		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
319		    sc->sc_io_res);
320		sc->sc_io_res = NULL;
321	}
322
323	xhci_uninit(sc);
324
325	return (0);
326}
327
328static int
329xhci_pci_take_controller(device_t self)
330{
331	struct xhci_softc *sc = device_get_softc(self);
332	uint32_t cparams;
333	uint32_t eecp;
334	uint32_t eec;
335	uint16_t to;
336	uint8_t bios_sem;
337
338	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
339
340	eec = -1;
341
342	/* Synchronise with the BIOS if it owns the controller. */
343	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
344	    eecp += XHCI_XECP_NEXT(eec) << 2) {
345		eec = XREAD4(sc, capa, eecp);
346
347		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
348			continue;
349		bios_sem = XREAD1(sc, capa, eecp +
350		    XHCI_XECP_BIOS_SEM);
351		if (bios_sem == 0)
352			continue;
353		device_printf(sc->sc_bus.bdev, "waiting for BIOS "
354		    "to give up control\n");
355		XWRITE1(sc, capa, eecp +
356		    XHCI_XECP_OS_SEM, 1);
357		to = 500;
358		while (1) {
359			bios_sem = XREAD1(sc, capa, eecp +
360			    XHCI_XECP_BIOS_SEM);
361			if (bios_sem == 0)
362				break;
363
364			if (--to == 0) {
365				device_printf(sc->sc_bus.bdev,
366				    "timed out waiting for BIOS\n");
367				break;
368			}
369			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
370		}
371	}
372	return (0);
373}
374