imx_sdhci.c revision 266200
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx_sdhci.c 266200 2014-05-15 22:35:04Z ian $"); 29 30/* 31 * SDHCI driver glue for Freescale i.MX SoC family. 32 * 33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/types.h> 39#include <sys/bus.h> 40#include <sys/callout.h> 41#include <sys/kernel.h> 42#include <sys/lock.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/mutex.h> 46#include <sys/resource.h> 47#include <sys/rman.h> 48#include <sys/taskqueue.h> 49#include <sys/time.h> 50 51#include <machine/bus.h> 52#include <machine/resource.h> 53#include <machine/intr.h> 54 55#include <arm/freescale/imx/imx51_ccmvar.h> 56 57#include <dev/ofw/ofw_bus.h> 58#include <dev/ofw/ofw_bus_subr.h> 59 60#include <dev/mmc/bridge.h> 61#include <dev/mmc/mmcreg.h> 62#include <dev/mmc/mmcbrvar.h> 63 64#include <dev/sdhci/sdhci.h> 65#include "sdhci_if.h" 66 67struct imx_sdhci_softc { 68 device_t dev; 69 struct resource * mem_res; 70 struct resource * irq_res; 71 void * intr_cookie; 72 struct sdhci_slot slot; 73 struct callout r1bfix_callout; 74 sbintime_t r1bfix_timeout_at; 75 uint32_t baseclk_hz; 76 uint32_t sdclockreg_freq_bits; 77 uint32_t cmd_and_mode; 78 uint32_t r1bfix_intmask; 79 uint8_t r1bfix_type; 80 uint8_t hwtype; 81 boolean_t force_card_present; 82}; 83 84#define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 85#define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 86#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 87 88#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 89#define HWTYPE_ESDHC 1 /* imx5x and earlier. */ 90#define HWTYPE_USDHC 2 /* imx6. */ 91 92#define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 93#define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 94#define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 95#define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 96#define SDHC_VEND_IPGEN (1 << 11) 97#define SDHC_VEND_HCKEN (1 << 12) 98#define SDHC_VEND_PEREN (1 << 13) 99 100#define SDHC_PRES_STATE 0x24 101#define SDHC_PRES_CIHB (1 << 0) 102#define SDHC_PRES_CDIHB (1 << 1) 103#define SDHC_PRES_DLA (1 << 2) 104#define SDHC_PRES_SDSTB (1 << 3) 105#define SDHC_PRES_IPGOFF (1 << 4) 106#define SDHC_PRES_HCKOFF (1 << 5) 107#define SDHC_PRES_PEROFF (1 << 6) 108#define SDHC_PRES_SDOFF (1 << 7) 109#define SDHC_PRES_WTA (1 << 8) 110#define SDHC_PRES_RTA (1 << 9) 111#define SDHC_PRES_BWEN (1 << 10) 112#define SDHC_PRES_BREN (1 << 11) 113#define SDHC_PRES_RTR (1 << 12) 114#define SDHC_PRES_CINST (1 << 16) 115#define SDHC_PRES_CDPL (1 << 18) 116#define SDHC_PRES_WPSPL (1 << 19) 117#define SDHC_PRES_CLSL (1 << 23) 118#define SDHC_PRES_DLSL_SHIFT 24 119#define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) 120 121#define SDHC_PROT_CTRL 0x28 122#define SDHC_PROT_LED (1 << 0) 123#define SDHC_PROT_WIDTH_1BIT (0 << 1) 124#define SDHC_PROT_WIDTH_4BIT (1 << 1) 125#define SDHC_PROT_WIDTH_8BIT (2 << 1) 126#define SDHC_PROT_WIDTH_MASK (3 << 1) 127#define SDHC_PROT_D3CD (1 << 3) 128#define SDHC_PROT_EMODE_BIG (0 << 4) 129#define SDHC_PROT_EMODE_HALF (1 << 4) 130#define SDHC_PROT_EMODE_LITTLE (2 << 4) 131#define SDHC_PROT_EMODE_MASK (3 << 4) 132#define SDHC_PROT_SDMA (0 << 8) 133#define SDHC_PROT_ADMA1 (1 << 8) 134#define SDHC_PROT_ADMA2 (2 << 8) 135#define SDHC_PROT_ADMA264 (3 << 8) 136#define SDHC_PROT_DMA_MASK (3 << 8) 137#define SDHC_PROT_CDTL (1 << 6) 138#define SDHC_PROT_CDSS (1 << 7) 139 140#define SDHC_INT_STATUS 0x30 141 142#define SDHC_CLK_IPGEN (1 << 0) 143#define SDHC_CLK_HCKEN (1 << 1) 144#define SDHC_CLK_PEREN (1 << 2) 145#define SDHC_CLK_DIVISOR_MASK 0x000000f0 146#define SDHC_CLK_DIVISOR_SHIFT 4 147#define SDHC_CLK_PRESCALE_MASK 0x0000ff00 148#define SDHC_CLK_PRESCALE_SHIFT 8 149 150static struct ofw_compat_data compat_data[] = { 151 {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 152 {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 153 {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 154 {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 155 {NULL, HWTYPE_NONE}, 156};; 157 158static void imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable); 159static void imx_sdhci_r1bfix_func(void *arg); 160 161static inline uint32_t 162RD4(struct imx_sdhci_softc *sc, bus_size_t off) 163{ 164 165 return (bus_read_4(sc->mem_res, off)); 166} 167 168static inline void 169WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val) 170{ 171 172 bus_write_4(sc->mem_res, off, val); 173} 174 175static uint8_t 176imx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 177{ 178 struct imx_sdhci_softc *sc = device_get_softc(dev); 179 uint32_t val32, wrk32; 180 181 /* 182 * Most of the things in the standard host control register are in the 183 * hardware's wider protocol control register, but some of the bits are 184 * moved around. 185 */ 186 if (off == SDHCI_HOST_CONTROL) { 187 wrk32 = RD4(sc, SDHC_PROT_CTRL); 188 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 189 SDHCI_CTRL_FORCE_CARD); 190 switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 191 case SDHC_PROT_WIDTH_1BIT: 192 /* Value is already 0. */ 193 break; 194 case SDHC_PROT_WIDTH_4BIT: 195 val32 |= SDHCI_CTRL_4BITBUS; 196 break; 197 case SDHC_PROT_WIDTH_8BIT: 198 val32 |= SDHCI_CTRL_8BITBUS; 199 break; 200 } 201 switch (wrk32 & SDHC_PROT_DMA_MASK) { 202 case SDHC_PROT_SDMA: 203 /* Value is already 0. */ 204 break; 205 case SDHC_PROT_ADMA1: 206 /* This value is deprecated, should never appear. */ 207 break; 208 case SDHC_PROT_ADMA2: 209 val32 |= SDHCI_CTRL_ADMA2; 210 break; 211 case SDHC_PROT_ADMA264: 212 val32 |= SDHCI_CTRL_ADMA264; 213 break; 214 } 215 return val32; 216 } 217 218 /* 219 * XXX can't find the bus power on/off knob. For now we have to say the 220 * power is always on and always set to the same voltage. 221 */ 222 if (off == SDHCI_POWER_CONTROL) { 223 return (SDHCI_POWER_ON | SDHCI_POWER_300); 224 } 225 226 227 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 228} 229 230static uint16_t 231imx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 232{ 233 struct imx_sdhci_softc *sc = device_get_softc(dev); 234 uint32_t val32, wrk32; 235 236 if (sc->hwtype == HWTYPE_USDHC) { 237 /* 238 * The USDHC hardware has nothing in the version register, but 239 * it's v3 compatible with all our translation code. 240 */ 241 if (off == SDHCI_HOST_VERSION) { 242 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 243 } 244 /* 245 * The USDHC hardware moved the transfer mode bits to the mixed 246 * control register, fetch them from there. 247 */ 248 if (off == SDHCI_TRANSFER_MODE) 249 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 250 251 } else if (sc->hwtype == HWTYPE_ESDHC) { 252 253 /* 254 * The ESDHC hardware has the typical 32-bit combined "command 255 * and mode" register that we have to cache so that command 256 * isn't written until after mode. On a read, just retrieve the 257 * cached values last written. 258 */ 259 if (off == SDHCI_TRANSFER_MODE) { 260 return (sc->cmd_and_mode >> 16); 261 } else if (off == SDHCI_COMMAND_FLAGS) { 262 return (sc->cmd_and_mode & 0x0000ffff); 263 } 264 } 265 266 /* 267 * This hardware only manages one slot. Synthesize a slot interrupt 268 * status register... if there are any enabled interrupts active they 269 * must be coming from our one and only slot. 270 */ 271 if (off == SDHCI_SLOT_INT_STATUS) { 272 val32 = RD4(sc, SDHCI_INT_STATUS); 273 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 274 return (val32 ? 1 : 0); 275 } 276 277 /* 278 * The clock enable bit is in the vendor register and the clock-stable 279 * bit is in the present state register. Transcribe them as if they 280 * were in the clock control register where they should be. 281 * XXX Is it important that we distinguish between "internal" and "card" 282 * clocks? Probably not; transcribe the card clock status to both bits. 283 */ 284 if (off == SDHCI_CLOCK_CONTROL) { 285 val32 = 0; 286 wrk32 = RD4(sc, SDHC_VEND_SPEC); 287 if (wrk32 & SDHC_VEND_FRC_SDCLK_ON) 288 val32 |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN; 289 wrk32 = RD4(sc, SDHC_PRES_STATE); 290 if (wrk32 & SDHC_PRES_SDSTB) 291 val32 |= SDHCI_CLOCK_INT_STABLE; 292 val32 |= sc->sdclockreg_freq_bits; 293 return (val32); 294 } 295 296 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 297} 298 299static uint32_t 300imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 301{ 302 struct imx_sdhci_softc *sc = device_get_softc(dev); 303 uint32_t val32, wrk32; 304 305 val32 = RD4(sc, off); 306 307 /* 308 * The hardware leaves the base clock frequency out of the capabilities 309 * register; fill it in. The timeout clock is the same as the active 310 * output sdclock; we indicate that with a quirk setting so don't 311 * populate the timeout frequency bits. 312 * 313 * XXX Turn off (for now) features the hardware can do but this driver 314 * doesn't yet handle (1.8v, suspend/resume, etc). 315 */ 316 if (off == SDHCI_CAPABILITIES) { 317 val32 &= ~SDHCI_CAN_VDD_180; 318 val32 &= ~SDHCI_CAN_DO_SUSPEND; 319 val32 |= SDHCI_CAN_DO_8BITBUS; 320 val32 |= (sc->baseclk_hz / 1000000) << SDHCI_CLOCK_BASE_SHIFT; 321 return (val32); 322 } 323 324 /* 325 * The hardware moves bits around in the present state register to make 326 * room for all 8 data line state bits. To translate, mask out all the 327 * bits which are not in the same position in both registers (this also 328 * masks out some freescale-specific bits in locations defined as 329 * reserved by sdhci), then shift the data line and retune request bits 330 * down to their standard locations. 331 */ 332 if (off == SDHCI_PRESENT_STATE) { 333 wrk32 = val32; 334 val32 &= 0x000F0F07; 335 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 336 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; 337 if (sc->force_card_present) 338 val32 |= SDHCI_CARD_PRESENT; 339 return (val32); 340 } 341 342 /* 343 * imx_sdhci_intr() can synthesize a DATA_END interrupt following a 344 * command with an R1B response, mix it into the hardware status. 345 */ 346 if (off == SDHCI_INT_STATUS) { 347 return (val32 | sc->r1bfix_intmask); 348 } 349 350 return val32; 351} 352 353static void 354imx_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 355 uint32_t *data, bus_size_t count) 356{ 357 struct imx_sdhci_softc *sc = device_get_softc(dev); 358 359 bus_read_multi_4(sc->mem_res, off, data, count); 360} 361 362static void 363imx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 364{ 365 struct imx_sdhci_softc *sc = device_get_softc(dev); 366 uint32_t val32; 367 368 /* 369 * Most of the things in the standard host control register are in the 370 * hardware's wider protocol control register, but some of the bits are 371 * moved around. 372 */ 373 if (off == SDHCI_HOST_CONTROL) { 374 val32 = RD4(sc, SDHC_PROT_CTRL); 375 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 376 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 377 val32 |= (val & SDHCI_CTRL_LED); 378 if (val & SDHCI_CTRL_8BITBUS) 379 val32 |= SDHC_PROT_WIDTH_8BIT; 380 else 381 val32 |= (val & SDHCI_CTRL_4BITBUS); 382 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 383 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 384 WR4(sc, SDHC_PROT_CTRL, val32); 385 return; 386 } 387 388 /* XXX I can't find the bus power on/off knob; do nothing. */ 389 if (off == SDHCI_POWER_CONTROL) { 390 return; 391 } 392 393 val32 = RD4(sc, off & ~3); 394 val32 &= ~(0xff << (off & 3) * 8); 395 val32 |= (val << (off & 3) * 8); 396 397 WR4(sc, off & ~3, val32); 398} 399 400static void 401imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 402{ 403 struct imx_sdhci_softc *sc = device_get_softc(dev); 404 uint32_t val32; 405 406 /* The USDHC hardware moved the transfer mode bits to mixed control. */ 407 if (sc->hwtype == HWTYPE_USDHC) { 408 if (off == SDHCI_TRANSFER_MODE) { 409 val32 = RD4(sc, USDHC_MIX_CONTROL); 410 val32 &= ~0x3f; 411 val32 |= val & 0x37; 412 // XXX acmd23 not supported here (or by sdhci driver) 413 WR4(sc, USDHC_MIX_CONTROL, val32); 414 return; 415 } 416 } 417 418 /* 419 * The clock control stuff is complex enough to have its own routine 420 * that can both change speeds and en/disable the clock output. Also, 421 * save the register bits in SDHCI format so that we can play them back 422 * in the read2 routine without complex decoding. 423 */ 424 if (off == SDHCI_CLOCK_CONTROL) { 425 sc->sdclockreg_freq_bits = val & 0xffc0; 426 if (val & SDHCI_CLOCK_CARD_EN) { 427 imx_sdhc_set_clock(sc, true); 428 } else { 429 imx_sdhc_set_clock(sc, false); 430 } 431 } 432 433 /* 434 * Figure out whether we need to check the DAT0 line for busy status at 435 * interrupt time. The controller should be doing this, but for some 436 * reason it doesn't. There are two cases: 437 * - R1B response with no data transfer should generate a DATA_END (aka 438 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 439 * there's no data transfer there's no DATA_END interrupt. This is 440 * documented; they seem to think it's a feature. 441 * - R1B response after Auto-CMD12 appears to not work, even though 442 * there's a control bit for it (bit 3) in the vendor register. 443 * When we're starting a command that needs a manual DAT0 line check at 444 * interrupt time, we leave ourselves a note in r1bfix_type so that we 445 * can do the extra work in imx_sdhci_intr(). 446 */ 447 if (off == SDHCI_COMMAND_FLAGS) { 448 if (val & SDHCI_CMD_DATA) { 449 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 450 val32 = RD4(sc, USDHC_MIX_CONTROL); 451 if ((val32 & MBAUTOCMD) == MBAUTOCMD) 452 sc->r1bfix_type = R1BFIX_AC12; 453 } else { 454 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 455 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 456 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 457 sc->r1bfix_type = R1BFIX_NODATA; 458 } 459 } 460 } 461 462 val32 = RD4(sc, off & ~3); 463 val32 &= ~(0xffff << (off & 3) * 8); 464 val32 |= ((val & 0xffff) << (off & 3) * 8); 465 WR4(sc, off & ~3, val32); 466} 467 468static void 469imx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 470{ 471 struct imx_sdhci_softc *sc = device_get_softc(dev); 472 473 /* Clear synthesized interrupts, then pass the value to the hardware. */ 474 if (off == SDHCI_INT_STATUS) { 475 sc->r1bfix_intmask &= ~val; 476 } 477 478 WR4(sc, off, val); 479} 480 481static void 482imx_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 483 uint32_t *data, bus_size_t count) 484{ 485 struct imx_sdhci_softc *sc = device_get_softc(dev); 486 487 bus_write_multi_4(sc->mem_res, off, data, count); 488} 489 490static void 491imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable) 492{ 493 uint32_t divisor, enable_bits, enable_reg, freq, prescale, val32; 494 495 if (sc->hwtype == HWTYPE_ESDHC) { 496 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) & 497 SDHCI_DIVIDER_MASK; 498 enable_reg = SDHCI_CLOCK_CONTROL; 499 enable_bits = SDHC_CLK_IPGEN | SDHC_CLK_HCKEN | 500 SDHC_CLK_PEREN; 501 } else { 502 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) & 503 SDHCI_DIVIDER_MASK; 504 divisor |= ((sc->sdclockreg_freq_bits >> 505 SDHCI_DIVIDER_HI_SHIFT) & 506 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 507 enable_reg = SDHCI_CLOCK_CONTROL; 508 enable_bits = SDHC_VEND_IPGEN | SDHC_VEND_HCKEN | 509 SDHC_VEND_PEREN; 510 } 511 512 WR4(sc, SDHC_VEND_SPEC, 513 RD4(sc, SDHC_VEND_SPEC) & ~SDHC_VEND_FRC_SDCLK_ON); 514 WR4(sc, enable_reg, RD4(sc, enable_reg) & ~enable_bits); 515 516 if (!enable) 517 return; 518 519 if (divisor == 0) 520 freq = sc->baseclk_hz; 521 else 522 freq = sc->baseclk_hz / (2 * divisor); 523 524 for (prescale = 2; prescale < freq / prescale / 16;) 525 prescale <<= 1; 526 527 for (divisor = 1; freq < freq / prescale / divisor;) 528 ++divisor; 529 530 prescale >>= 1; 531 divisor -= 1; 532 533 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 534 val32 &= ~SDHC_CLK_DIVISOR_MASK; 535 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 536 val32 &= ~SDHC_CLK_PRESCALE_MASK; 537 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 538 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 539 540 WR4(sc, enable_reg, RD4(sc, enable_reg) | enable_bits); 541 WR4(sc, SDHC_VEND_SPEC, 542 RD4(sc, SDHC_VEND_SPEC) | SDHC_VEND_FRC_SDCLK_ON); 543} 544 545static boolean_t 546imx_sdhci_r1bfix_is_wait_done(struct imx_sdhci_softc *sc) 547{ 548 uint32_t inhibit; 549 550 mtx_assert(&sc->slot.mtx, MA_OWNED); 551 552 /* 553 * Check the DAT0 line status using both the DLA (data line active) and 554 * CDIHB (data inhibit) bits in the present state register. In theory 555 * just DLA should do the trick, but in practice it takes both. If the 556 * DAT0 line is still being held and we're not yet beyond the timeout 557 * point, just schedule another callout to check again later. 558 */ 559 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); 560 561 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { 562 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, 563 imx_sdhci_r1bfix_func, sc, 0); 564 return (false); 565 } 566 567 /* 568 * If we reach this point with the inhibit bits still set, we've got a 569 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 570 * line has been released, and we synthesize a DATA_END, and if the type 571 * of fix needed was on a command-without-data we also now add in the 572 * original INT_RESPONSE that we suppressed earlier. 573 */ 574 if (inhibit) 575 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; 576 else { 577 sc->r1bfix_intmask |= SDHCI_INT_DATA_END; 578 if (sc->r1bfix_type == R1BFIX_NODATA) 579 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; 580 } 581 582 sc->r1bfix_type = R1BFIX_NONE; 583 return (true); 584} 585 586static void 587imx_sdhci_r1bfix_func(void * arg) 588{ 589 struct imx_sdhci_softc *sc = arg; 590 boolean_t r1bwait_done; 591 592 mtx_lock(&sc->slot.mtx); 593 r1bwait_done = imx_sdhci_r1bfix_is_wait_done(sc); 594 mtx_unlock(&sc->slot.mtx); 595 if (r1bwait_done) 596 sdhci_generic_intr(&sc->slot); 597} 598 599static void 600imx_sdhci_intr(void *arg) 601{ 602 struct imx_sdhci_softc *sc = arg; 603 uint32_t intmask; 604 605 mtx_lock(&sc->slot.mtx); 606 607 /* 608 * Manually check the DAT0 line for R1B response types that the 609 * controller fails to handle properly. The controller asserts the done 610 * interrupt while the card is still asserting busy with the DAT0 line. 611 * 612 * We check DAT0 immediately because most of the time, especially on a 613 * read, the card will actually be done by time we get here. If it's 614 * not, then the wait_done routine will schedule a callout to re-check 615 * periodically until it is done. In that case we clear the interrupt 616 * out of the hardware now so that we can present it later when the DAT0 617 * line is released. 618 * 619 * If we need to wait for the the DAT0 line to be released, we set up a 620 * timeout point 250ms in the future. This number comes from the SD 621 * spec, which allows a command to take that long. In the real world, 622 * cards tend to take 10-20ms for a long-running command such as a write 623 * or erase that spans two pages. 624 */ 625 switch (sc->r1bfix_type) { 626 case R1BFIX_NODATA: 627 intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_RESPONSE; 628 break; 629 case R1BFIX_AC12: 630 intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_DATA_END; 631 break; 632 default: 633 intmask = 0; 634 break; 635 } 636 if (intmask) { 637 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; 638 if (!imx_sdhci_r1bfix_is_wait_done(sc)) { 639 WR4(sc, SDHC_INT_STATUS, intmask); 640 bus_barrier(sc->mem_res, SDHC_INT_STATUS, 4, 641 BUS_SPACE_BARRIER_WRITE); 642 } 643 } 644 645 mtx_unlock(&sc->slot.mtx); 646 sdhci_generic_intr(&sc->slot); 647} 648 649static int 650imx_sdhci_get_ro(device_t bus, device_t child) 651{ 652 653 return (false); 654} 655 656static int 657imx_sdhci_detach(device_t dev) 658{ 659 660 return (EBUSY); 661} 662 663static int 664imx_sdhci_attach(device_t dev) 665{ 666 struct imx_sdhci_softc *sc = device_get_softc(dev); 667 int rid, err; 668 phandle_t node; 669 670 sc->dev = dev; 671 672 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 673 if (sc->hwtype == HWTYPE_NONE) 674 panic("Impossible: not compatible in imx_sdhci_attach()"); 675 676 rid = 0; 677 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 678 RF_ACTIVE); 679 if (!sc->mem_res) { 680 device_printf(dev, "cannot allocate memory window\n"); 681 err = ENXIO; 682 goto fail; 683 } 684 685 rid = 0; 686 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 687 RF_ACTIVE); 688 if (!sc->irq_res) { 689 device_printf(dev, "cannot allocate interrupt\n"); 690 err = ENXIO; 691 goto fail; 692 } 693 694 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 695 NULL, imx_sdhci_intr, sc, &sc->intr_cookie)) { 696 device_printf(dev, "cannot setup interrupt handler\n"); 697 err = ENXIO; 698 goto fail; 699 } 700 701 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 702 703 /* 704 * DMA is not really broken, I just haven't implemented it yet. 705 */ 706 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 707 708 /* 709 * Set the buffer watermark level to 128 words (512 bytes) for both read 710 * and write. The hardware has a restriction that when the read or 711 * write ready status is asserted, that means you can read exactly the 712 * number of words set in the watermark register before you have to 713 * re-check the status and potentially wait for more data. The main 714 * sdhci driver provides no hook for doing status checking on less than 715 * a full block boundary, so we set the watermark level to be a full 716 * block. Reads and writes where the block size is less than the 717 * watermark size will work correctly too, no need to change the 718 * watermark for different size blocks. However, 128 is the maximum 719 * allowed for the watermark, so PIO is limitted to 512 byte blocks 720 * (which works fine for SD cards, may be a problem for SDIO some day). 721 * 722 * XXX need named constants for this stuff. 723 */ 724 WR4(sc, SDHC_WTMK_LVL, 0x08800880); 725 726 /* XXX get imx6 clock frequency from CCM */ 727 if (sc->hwtype == HWTYPE_USDHC) { 728 sc->baseclk_hz = 200000000; 729 } else if (sc->hwtype == HWTYPE_ESDHC) { 730 sc->baseclk_hz = imx51_get_clock(IMX51CLK_PERCLK_ROOT); 731 } 732 733 sdhci_init_slot(dev, &sc->slot, 0); 734 callout_init(&sc->r1bfix_callout, true); 735 736 /* 737 * If the slot is flagged with the non-removable property, set our flag 738 * to always force the SDHCI_CARD_PRESENT bit on. 739 * 740 * XXX Workaround for gpio-based card detect... 741 * 742 * We don't have gpio support yet. If there's a cd-gpios property just 743 * force the SDHCI_CARD_PRESENT bit on for now. If there isn't really a 744 * card there it will fail to probe at the mmc layer and nothing bad 745 * happens except instantiating an mmcN device for an empty slot. 746 */ 747 node = ofw_bus_get_node(dev); 748 if (OF_hasprop(node, "non-removable")) 749 sc->force_card_present = true; 750 else if (OF_hasprop(node, "cd-gpios")) { 751 /* XXX put real gpio hookup here. */ 752 sc->force_card_present = true; 753 } 754 755 bus_generic_probe(dev); 756 bus_generic_attach(dev); 757 758 sdhci_start_slot(&sc->slot); 759 760 return (0); 761 762fail: 763 if (sc->intr_cookie) 764 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 765 if (sc->irq_res) 766 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 767 if (sc->mem_res) 768 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 769 770 return (err); 771} 772 773static int 774imx_sdhci_probe(device_t dev) 775{ 776 777 if (!ofw_bus_status_okay(dev)) 778 return (ENXIO); 779 780 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 781 case HWTYPE_ESDHC: 782 device_set_desc(dev, "Freescale eSDHC controller"); 783 return (BUS_PROBE_DEFAULT); 784 case HWTYPE_USDHC: 785 device_set_desc(dev, "Freescale uSDHC controller"); 786 return (BUS_PROBE_DEFAULT); 787 default: 788 break; 789 } 790 return (ENXIO); 791} 792 793static device_method_t imx_sdhci_methods[] = { 794 /* Device interface */ 795 DEVMETHOD(device_probe, imx_sdhci_probe), 796 DEVMETHOD(device_attach, imx_sdhci_attach), 797 DEVMETHOD(device_detach, imx_sdhci_detach), 798 799 /* Bus interface */ 800 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 801 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 802 DEVMETHOD(bus_print_child, bus_generic_print_child), 803 804 /* MMC bridge interface */ 805 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 806 DEVMETHOD(mmcbr_request, sdhci_generic_request), 807 DEVMETHOD(mmcbr_get_ro, imx_sdhci_get_ro), 808 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 809 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 810 811 /* SDHCI registers accessors */ 812 DEVMETHOD(sdhci_read_1, imx_sdhci_read_1), 813 DEVMETHOD(sdhci_read_2, imx_sdhci_read_2), 814 DEVMETHOD(sdhci_read_4, imx_sdhci_read_4), 815 DEVMETHOD(sdhci_read_multi_4, imx_sdhci_read_multi_4), 816 DEVMETHOD(sdhci_write_1, imx_sdhci_write_1), 817 DEVMETHOD(sdhci_write_2, imx_sdhci_write_2), 818 DEVMETHOD(sdhci_write_4, imx_sdhci_write_4), 819 DEVMETHOD(sdhci_write_multi_4, imx_sdhci_write_multi_4), 820 821 { 0, 0 } 822}; 823 824static devclass_t imx_sdhci_devclass; 825 826static driver_t imx_sdhci_driver = { 827 "sdhci_imx", 828 imx_sdhci_methods, 829 sizeof(struct imx_sdhci_softc), 830}; 831 832DRIVER_MODULE(sdhci_imx, simplebus, imx_sdhci_driver, imx_sdhci_devclass, 0, 0); 833MODULE_DEPEND(sdhci_imx, sdhci, 1, 1, 1); 834 835