imx6_anatop.c revision 283500
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx6_anatop.c 283500 2015-05-24 18:59:45Z ian $"); 30 31/* 32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs. 33 * Also, temperature montoring and cpu frequency control. It was Freescale who 34 * kitchen-sinked this device, not us. :) 35 * 36 * We don't really do anything with analog PLLs, but the registers for 37 * controlling them belong to the same block as the power regulator registers. 38 * Since the newbus hierarchy makes it hard for anyone other than us to get at 39 * them, we just export a couple public functions to allow the imx6 CCM clock 40 * driver to read and write those registers. 41 * 42 * We also don't do anything about power regulation yet, but when the need 43 * arises, this would be the place for that code to live. 44 * 45 * I have no idea where the "anatop" name comes from. It's in the standard DTS 46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes 47 * from Freescale, but it's not in the SoC manual. 48 * 49 * Note that temperature values throughout this code are handled in two types of 50 * units. Items with '_cnt' in the name use the hardware temperature count 51 * units (higher counts are lower temperatures). Items with '_val' in the name 52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl 53 * handlers (dK is the standard unit for temperature in sysctl). 54 */ 55 56#include <sys/param.h> 57#include <sys/systm.h> 58#include <sys/callout.h> 59#include <sys/kernel.h> 60#include <sys/limits.h> 61#include <sys/sysctl.h> 62#include <sys/module.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/ofw/ofw_bus.h> 67#include <dev/ofw/ofw_bus_subr.h> 68 69#include <machine/bus.h> 70#include <machine/fdt.h> 71 72#include <arm/arm/mpcore_timervar.h> 73#include <arm/freescale/fsl_ocotpreg.h> 74#include <arm/freescale/fsl_ocotpvar.h> 75#include <arm/freescale/imx/imx6_anatopreg.h> 76#include <arm/freescale/imx/imx6_anatopvar.h> 77 78static SYSCTL_NODE(_hw, OID_AUTO, imx6, CTLFLAG_RW, NULL, "i.MX6 container"); 79 80static struct resource_spec imx6_anatop_spec[] = { 81 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 82 { SYS_RES_IRQ, 0, RF_ACTIVE }, 83 { -1, 0 } 84}; 85#define MEMRES 0 86#define IRQRES 1 87 88struct imx6_anatop_softc { 89 device_t dev; 90 struct resource *res[2]; 91 struct intr_config_hook 92 intr_setup_hook; 93 uint32_t cpu_curmhz; 94 uint32_t cpu_curmv; 95 uint32_t cpu_minmhz; 96 uint32_t cpu_minmv; 97 uint32_t cpu_maxmhz; 98 uint32_t cpu_maxmv; 99 uint32_t cpu_maxmhz_hw; 100 boolean_t cpu_overclock_enable; 101 boolean_t cpu_init_done; 102 uint32_t refosc_mhz; 103 void *temp_intrhand; 104 uint32_t temp_high_val; 105 uint32_t temp_high_cnt; 106 uint32_t temp_last_cnt; 107 uint32_t temp_room_cnt; 108 struct callout temp_throttle_callout; 109 sbintime_t temp_throttle_delay; 110 uint32_t temp_throttle_reset_cnt; 111 uint32_t temp_throttle_trigger_cnt; 112 uint32_t temp_throttle_val; 113}; 114 115static struct imx6_anatop_softc *imx6_anatop_sc; 116 117/* 118 * Table of "operating points". 119 * These are combinations of frequency and voltage blessed by Freescale. 120 */ 121static struct oppt { 122 uint32_t mhz; 123 uint32_t mv; 124} imx6_oppt_table[] = { 125/* { 396, 925}, XXX: need functional ccm code for this speed */ 126 { 792, 1150}, 127 { 852, 1225}, 128 { 996, 1225}, 129 {1200, 1275}, 130}; 131 132/* 133 * Table of CPU max frequencies. This is used to translate the max frequency 134 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked 135 * up in the operating points table. 136 */ 137static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200}; 138 139#define TZ_ZEROC 2732 /* deci-Kelvin <-> deci-Celcius offset. */ 140 141uint32_t 142imx6_anatop_read_4(bus_size_t offset) 143{ 144 145 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL")); 146 147 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset)); 148} 149 150void 151imx6_anatop_write_4(bus_size_t offset, uint32_t value) 152{ 153 154 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL")); 155 156 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); 157} 158 159static void 160vdd_set(struct imx6_anatop_softc *sc, int mv) 161{ 162 int newtarg, oldtarg; 163 uint32_t delay, pmureg; 164 static boolean_t init_done = false; 165 166 /* 167 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM 168 * can't be more than 50mV above or 200mV below them. For now to keep 169 * things simple we set all three to the same value. 170 */ 171 172 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); 173 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; 174 175 /* Convert mV to target value. Clamp target to valid range. */ 176 if (mv < 725) 177 newtarg = 0x00; 178 else if (mv > 1450) 179 newtarg = 0x1F; 180 else 181 newtarg = (mv - 700) / 25; 182 183 /* 184 * The first time through the 3 voltages might not be equal so use a 185 * long conservative delay. After that we need to delay 3uS for every 186 * 25mV step upward. No need to delay at all when lowering. 187 */ 188 if (init_done) { 189 if (newtarg == oldtarg) 190 return; 191 else if (newtarg > oldtarg) 192 delay = (newtarg - oldtarg) * 3; 193 else 194 delay = 0; 195 } else { 196 delay = 700 / 25 * 3; 197 init_done = true; 198 } 199 200 /* 201 * Make the change and wait for it to take effect. 202 */ 203 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | 204 IMX6_ANALOG_PMU_REG1_TARG_MASK | 205 IMX6_ANALOG_PMU_REG2_TARG_MASK); 206 207 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; 208 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; 209 pmureg |= newtarg << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; 210 211 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); 212 DELAY(delay); 213 sc->cpu_curmv = newtarg * 25 + 700; 214} 215 216static inline uint32_t 217cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t div) 218{ 219 220 return (sc->refosc_mhz * (div / 2)); 221} 222 223static inline uint32_t 224cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 225{ 226 227 return (cpu_mhz / (sc->refosc_mhz / 2)); 228} 229 230static inline uint32_t 231cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 232{ 233 234 return (cpufreq_mhz_from_div(sc, cpufreq_mhz_to_div(sc, cpu_mhz))); 235} 236 237static struct oppt * 238cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz) 239{ 240 int d, diff, i, nearest; 241 242 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable) 243 cpu_newmhz = sc->cpu_maxmhz_hw; 244 245 diff = INT_MAX; 246 nearest = 0; 247 for (i = 0; i < nitems(imx6_oppt_table); ++i) { 248 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); 249 if (diff > d) { 250 diff = d; 251 nearest = i; 252 } 253 } 254 return (&imx6_oppt_table[nearest]); 255} 256 257static void 258cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op) 259{ 260 uint32_t timeout, wrk32; 261 262 /* If increasing the frequency, we must first increase the voltage. */ 263 if (op->mhz > sc->cpu_curmhz) { 264 vdd_set(sc, op->mv); 265 } 266 267 /* 268 * I can't find a documented procedure for changing the ARM PLL divisor, 269 * but some trial and error came up with this: 270 * - Set the bypass clock source to REF_CLK_24M (source #0). 271 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. 272 * - Change the divisor. 273 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. 274 * - Turn off bypass mode; cpu should now be running at the new speed. 275 */ 276 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 277 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK); 278 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET, 279 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 280 281 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM); 282 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 283 wrk32 |= cpufreq_mhz_to_div(sc, op->mhz); 284 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32); 285 286 timeout = 10000; 287 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 288 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0) 289 if (--timeout == 0) 290 panic("imx6_set_cpu_clock(): PLL never locked"); 291 292 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 293 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 294 295 /* If lowering the frequency, it is now safe to lower the voltage. */ 296 if (op->mhz < sc->cpu_curmhz) 297 vdd_set(sc, op->mv); 298 sc->cpu_curmhz = op->mhz; 299 300 /* Tell the mpcore timer that its frequency has changed. */ 301 arm_tmr_change_frequency( 302 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2); 303} 304 305static int 306cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS) 307{ 308 struct imx6_anatop_softc *sc; 309 struct oppt * op; 310 uint32_t temp; 311 int err; 312 313 sc = arg1; 314 315 temp = sc->cpu_minmhz; 316 err = sysctl_handle_int(oidp, &temp, 0, req); 317 if (err != 0 || req->newptr == NULL) 318 return (err); 319 320 op = cpufreq_nearest_oppt(sc, temp); 321 if (op->mhz > sc->cpu_maxmhz) 322 return (ERANGE); 323 else if (op->mhz == sc->cpu_minmhz) 324 return (0); 325 326 /* 327 * Value changed, update softc. If the new min is higher than the 328 * current speed, raise the current speed to match. 329 */ 330 sc->cpu_minmhz = op->mhz; 331 if (sc->cpu_minmhz > sc->cpu_curmhz) { 332 cpufreq_set_clock(sc, op); 333 } 334 return (err); 335} 336 337static int 338cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS) 339{ 340 struct imx6_anatop_softc *sc; 341 struct oppt * op; 342 uint32_t temp; 343 int err; 344 345 sc = arg1; 346 347 temp = sc->cpu_maxmhz; 348 err = sysctl_handle_int(oidp, &temp, 0, req); 349 if (err != 0 || req->newptr == NULL) 350 return (err); 351 352 op = cpufreq_nearest_oppt(sc, temp); 353 if (op->mhz < sc->cpu_minmhz) 354 return (ERANGE); 355 else if (op->mhz == sc->cpu_maxmhz) 356 return (0); 357 358 /* 359 * Value changed, update softc and hardware. The hardware update is 360 * unconditional. We always try to run at max speed, so any change of 361 * the max means we need to change the current speed too, regardless of 362 * whether it is higher or lower than the old max. 363 */ 364 sc->cpu_maxmhz = op->mhz; 365 cpufreq_set_clock(sc, op); 366 367 return (err); 368} 369 370static void 371cpufreq_initialize(struct imx6_anatop_softc *sc) 372{ 373 uint32_t cfg3speed; 374 struct oppt * op; 375 376 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 377 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0, 378 "CPU frequency"); 379 380 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 381 OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0, 382 cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency"); 383 384 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 385 OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0, 386 cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency"); 387 388 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 389 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0, 390 "Maximum CPU frequency allowed by hardware"); 391 392 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 393 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN, 394 &sc->cpu_overclock_enable, 0, 395 "Allow setting CPU frequency higher than cpu_maxmhz_hw"); 396 397 /* 398 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm 399 * (even though in the real world it will always be 24mhz). Oh wait a 400 * sec, I never wrote imx6_ccm. 401 */ 402 sc->refosc_mhz = 24; 403 404 /* 405 * Get the maximum speed this cpu can be set to. The values in the 406 * OCOTP CFG3 register are not documented in the reference manual. 407 * The following info was in an archived email found via web search: 408 * - 2b'11: 1200000000Hz; 409 * - 2b'10: 996000000Hz; 410 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 411 * - 2b'00: 792000000Hz; 412 * The default hardware max speed can be overridden by a tunable. 413 */ 414 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) & 415 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; 416 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed]; 417 sc->cpu_maxmhz = sc->cpu_maxmhz_hw; 418 419 TUNABLE_INT_FETCH("hw.imx6.cpu_overclock_enable", 420 &sc->cpu_overclock_enable); 421 422 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz); 423 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz); 424 sc->cpu_minmhz = op->mhz; 425 sc->cpu_minmv = op->mv; 426 427 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz); 428 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz); 429 sc->cpu_maxmhz = op->mhz; 430 sc->cpu_maxmv = op->mv; 431 432 /* 433 * Set the CPU to maximum speed. 434 * 435 * We won't have thermal throttling until interrupts are enabled, but we 436 * want to run at full speed through all the device init stuff. This 437 * basically assumes that a single core can't overheat before interrupts 438 * are enabled; empirical testing shows that to be a safe assumption. 439 */ 440 cpufreq_set_clock(sc, op); 441} 442 443static inline uint32_t 444temp_from_count(struct imx6_anatop_softc *sc, uint32_t count) 445{ 446 447 return (((sc->temp_high_val - (count - sc->temp_high_cnt) * 448 (sc->temp_high_val - 250) / 449 (sc->temp_room_cnt - sc->temp_high_cnt)))); 450} 451 452static inline uint32_t 453temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp) 454{ 455 456 return ((sc->temp_room_cnt - sc->temp_high_cnt) * 457 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) + 458 sc->temp_high_cnt); 459} 460 461static void 462temp_update_count(struct imx6_anatop_softc *sc) 463{ 464 uint32_t val; 465 466 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0); 467 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID)) 468 return; 469 sc->temp_last_cnt = 470 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> 471 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; 472} 473 474static int 475temp_sysctl_handler(SYSCTL_HANDLER_ARGS) 476{ 477 struct imx6_anatop_softc *sc = arg1; 478 uint32_t t; 479 480 temp_update_count(sc); 481 482 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC; 483 484 return (sysctl_handle_int(oidp, &t, 0, req)); 485} 486 487static int 488temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS) 489{ 490 struct imx6_anatop_softc *sc = arg1; 491 int err; 492 uint32_t temp; 493 494 temp = sc->temp_throttle_val + TZ_ZEROC; 495 err = sysctl_handle_int(oidp, &temp, 0, req); 496 if (temp < TZ_ZEROC) 497 return (ERANGE); 498 temp -= TZ_ZEROC; 499 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val) 500 return (err); 501 502 /* Value changed, update counts in softc and hardware. */ 503 sc->temp_throttle_val = temp; 504 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); 505 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100); 506 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR, 507 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK); 508 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET, 509 (sc->temp_throttle_trigger_cnt << 510 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)); 511 return (err); 512} 513 514static void 515tempmon_gofast(struct imx6_anatop_softc *sc) 516{ 517 518 if (sc->cpu_curmhz < sc->cpu_maxmhz) { 519 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz)); 520 } 521} 522 523static void 524tempmon_goslow(struct imx6_anatop_softc *sc) 525{ 526 527 if (sc->cpu_curmhz > sc->cpu_minmhz) { 528 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz)); 529 } 530} 531 532static int 533tempmon_intr(void *arg) 534{ 535 struct imx6_anatop_softc *sc = arg; 536 537 /* 538 * XXX Note that this code doesn't currently run (for some mysterious 539 * reason we just never get an interrupt), so the real monitoring is 540 * done by tempmon_throttle_check(). 541 */ 542 tempmon_goslow(sc); 543 /* XXX Schedule callout to speed back up eventually. */ 544 return (FILTER_HANDLED); 545} 546 547static void 548tempmon_throttle_check(void *arg) 549{ 550 struct imx6_anatop_softc *sc = arg; 551 552 /* Lower counts are higher temperatures. */ 553 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt) 554 tempmon_goslow(sc); 555 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt)) 556 tempmon_gofast(sc); 557 558 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 559 0, tempmon_throttle_check, sc, 0); 560 561} 562 563static void 564initialize_tempmon(struct imx6_anatop_softc *sc) 565{ 566 uint32_t cal; 567 568 /* 569 * Fetch calibration data: a sensor count at room temperature (25C), 570 * a sensor count at a high temperature, and that temperature 571 */ 572 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1); 573 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20; 574 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8; 575 sc->temp_high_val = (cal & 0x000000FF) * 10; 576 577 /* 578 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and 579 * reset back to max cpu freq at 5C below the trigger. 580 */ 581 sc->temp_throttle_val = sc->temp_high_val - 100; 582 sc->temp_throttle_trigger_cnt = 583 temp_to_count(sc, sc->temp_throttle_val); 584 sc->temp_throttle_reset_cnt = 585 temp_to_count(sc, sc->temp_throttle_val - 50); 586 587 /* 588 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set 589 * the throttle count, and begin making measurements. 590 */ 591 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800); 592 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0, 593 (sc->temp_throttle_trigger_cnt << 594 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) | 595 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE); 596 597 /* 598 * XXX Note that the alarm-interrupt feature isn't working yet, so 599 * we'll use a callout handler to check at 10Hz. Make sure we have an 600 * initial temperature reading before starting up the callouts so we 601 * don't get a bogus reading of zero. 602 */ 603 while (sc->temp_last_cnt == 0) 604 temp_update_count(sc); 605 sc->temp_throttle_delay = 100 * SBT_1MS; 606 callout_init(&sc->temp_throttle_callout, 0); 607 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 608 0, tempmon_throttle_check, sc, 0); 609 610 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 611 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0, 612 temp_sysctl_handler, "IK", "Current die temperature"); 613 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 614 OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc, 615 0, temp_throttle_sysctl_handler, "IK", 616 "Throttle CPU when exceeding this temperature"); 617} 618 619static void 620intr_setup(void *arg) 621{ 622 struct imx6_anatop_softc *sc; 623 624 sc = arg; 625 bus_setup_intr(sc->dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE, 626 tempmon_intr, NULL, sc, &sc->temp_intrhand); 627 config_intrhook_disestablish(&sc->intr_setup_hook); 628} 629 630static void 631imx6_anatop_new_pass(device_t dev) 632{ 633 struct imx6_anatop_softc *sc; 634 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE; 635 636 /* 637 * We attach during BUS_PASS_BUS (because some day we will be a 638 * simplebus that has regulator devices as children), but some of our 639 * init work cannot be done until BUS_PASS_CPU (we rely on other devices 640 * that attach on the CPU pass). 641 */ 642 sc = device_get_softc(dev); 643 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) { 644 sc->cpu_init_done = true; 645 cpufreq_initialize(sc); 646 initialize_tempmon(sc); 647 if (bootverbose) { 648 device_printf(sc->dev, "CPU %uMHz @ %umV\n", 649 sc->cpu_curmhz, sc->cpu_curmv); 650 } 651 } 652 bus_generic_new_pass(dev); 653} 654 655static int 656imx6_anatop_detach(device_t dev) 657{ 658 659 /* This device can never detach. */ 660 return (EBUSY); 661} 662 663static int 664imx6_anatop_attach(device_t dev) 665{ 666 struct imx6_anatop_softc *sc; 667 int err; 668 669 sc = device_get_softc(dev); 670 sc->dev = dev; 671 672 /* Allocate bus_space resources. */ 673 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) { 674 device_printf(dev, "Cannot allocate resources\n"); 675 err = ENXIO; 676 goto out; 677 } 678 679 sc->intr_setup_hook.ich_func = intr_setup; 680 sc->intr_setup_hook.ich_arg = sc; 681 config_intrhook_establish(&sc->intr_setup_hook); 682 683 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), 684 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 685 OID_AUTO, "cpu_voltage", CTLFLAG_RD, 686 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); 687 688 imx6_anatop_sc = sc; 689 690 /* 691 * Other code seen on the net sets this SELFBIASOFF flag around the same 692 * time the temperature sensor is set up, although it's unclear how the 693 * two are related (if at all). 694 */ 695 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET, 696 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF); 697 698 /* 699 * Some day, when we're ready to deal with the actual anatop regulators 700 * that are described in fdt data as children of this "bus", this would 701 * be the place to invoke a simplebus helper routine to instantiate the 702 * children from the fdt data. 703 */ 704 705 err = 0; 706 707out: 708 709 if (err != 0) { 710 bus_release_resources(dev, imx6_anatop_spec, sc->res); 711 } 712 713 return (err); 714} 715 716uint32_t 717pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 718{ 719 int reg; 720 721 /* 722 * Audio PLL (PLL4). 723 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM) 724 */ 725 726 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE); 727 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \ 728 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 729 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 730 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg); 731 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn); 732 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd); 733 734 return (0); 735} 736 737static int 738imx6_anatop_probe(device_t dev) 739{ 740 741 if (!ofw_bus_status_okay(dev)) 742 return (ENXIO); 743 744 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0) 745 return (ENXIO); 746 747 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power"); 748 749 return (BUS_PROBE_DEFAULT); 750} 751 752uint32_t 753imx6_get_cpu_clock() 754{ 755 uint32_t div; 756 757 div = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 758 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 759 return (cpufreq_mhz_from_div(imx6_anatop_sc, div)); 760} 761 762static device_method_t imx6_anatop_methods[] = { 763 /* Device interface */ 764 DEVMETHOD(device_probe, imx6_anatop_probe), 765 DEVMETHOD(device_attach, imx6_anatop_attach), 766 DEVMETHOD(device_detach, imx6_anatop_detach), 767 768 /* Bus interface */ 769 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass), 770 771 DEVMETHOD_END 772}; 773 774static driver_t imx6_anatop_driver = { 775 "imx6_anatop", 776 imx6_anatop_methods, 777 sizeof(struct imx6_anatop_softc) 778}; 779 780static devclass_t imx6_anatop_devclass; 781 782EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, 783 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 784EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, 785 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 786 787