r300_reg.h revision 261455
1251599Sdas/* 2141296Sdas * Copyright 2005 Nicolai Haehnle et al. 3141296Sdas * Copyright 2008 Advanced Micro Devices, Inc. 42116Sjkh * Copyright 2009 Jerome Glisse. 52116Sjkh * 62116Sjkh * Permission is hereby granted, free of charge, to any person obtaining a 72116Sjkh * copy of this software and associated documentation files (the "Software"), 8141296Sdas * to deal in the Software without restriction, including without limitation 92116Sjkh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10141296Sdas * and/or sell copies of the Software, and to permit persons to whom the 112116Sjkh * Software is furnished to do so, subject to the following conditions: 122116Sjkh * 13141296Sdas * The above copyright notice and this permission notice shall be included in 142116Sjkh * all copies or substantial portions of the Software. 152116Sjkh * 16176451Sdas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17176451Sdas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 182116Sjkh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19251599Sdas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20251599Sdas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 212116Sjkh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22251599Sdas * OTHER DEALINGS IN THE SOFTWARE. 23251599Sdas * 242116Sjkh * Authors: Nicolai Haehnle 252116Sjkh * Jerome Glisse 26251599Sdas */ 27251599Sdas#ifndef _R300_REG_H_ 28251599Sdas#define _R300_REG_H_ 29251599Sdas 30251599Sdas#include <sys/cdefs.h> 31251599Sdas__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/r300_reg.h 261455 2014-02-04 03:36:42Z eadler $"); 322116Sjkh 332116Sjkh#define R300_SURF_TILE_MACRO (1<<16) 342116Sjkh#define R300_SURF_TILE_MICRO (2<<16) 35251599Sdas#define R300_SURF_TILE_BOTH (3<<16) 36251599Sdas 37251599Sdas 38251599Sdas#define R300_MC_INIT_MISC_LAT_TIMER 0x180 39251599Sdas# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 40251599Sdas# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 41251599Sdas# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 42251599Sdas# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 43251599Sdas# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 44251599Sdas# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 45251599Sdas# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 46251599Sdas# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 47251599Sdas 48251599Sdas#define R300_MC_INIT_GFX_LAT_TIMER 0x154 49251599Sdas# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 50251599Sdas# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 518870Srgrimes# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 52251599Sdas# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 532116Sjkh# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 54251599Sdas# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 55251599Sdas# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 56251599Sdas# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 57251599Sdas 58251599Sdas/* 59251599Sdas * This file contains registers and constants for the R300. They have been 60251599Sdas * found mostly by examining command buffers captured using glxtest, as well 61251599Sdas * as by extrapolating some known registers and constants from the R200. 62251599Sdas * I am fairly certain that they are correct unless stated otherwise 63251599Sdas * in comments. 64251599Sdas */ 65251599Sdas 66251599Sdas#define R300_SE_VPORT_XSCALE 0x1D98 678870Srgrimes#define R300_SE_VPORT_XOFFSET 0x1D9C 68251599Sdas#define R300_SE_VPORT_YSCALE 0x1DA0 69251599Sdas#define R300_SE_VPORT_YOFFSET 0x1DA4 70251599Sdas#define R300_SE_VPORT_ZSCALE 0x1DA8 71251599Sdas#define R300_SE_VPORT_ZOFFSET 0x1DAC 72251599Sdas 73251599Sdas 74251599Sdas/* 75251599Sdas * Vertex Array Processing (VAP) Control 76251599Sdas * Stolen from r200 code from Christoph Brill (It's a guess!) 77251599Sdas */ 78141296Sdas#define R300_VAP_CNTL 0x2080 79251599Sdas 80251599Sdas/* This register is written directly and also starts data section 81251599Sdas * in many 3d CP_PACKET3's 82251599Sdas */ 832116Sjkh#define R300_VAP_VF_CNTL 0x2084 84251599Sdas# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 852116Sjkh# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) 862116Sjkh# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) 87251599Sdas# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) 882116Sjkh# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) 892116Sjkh# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) 90# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) 91# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) 92# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) 93# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) 94# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) 95# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) 96 97# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 98 /* State based - direct writes to registers trigger vertex 99 generation */ 100# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) 101# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) 102# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) 103# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) 104 105 /* I don't think I saw these three used.. */ 106# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 107# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 108# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 109 110 /* index size - when not set the indices are assumed to be 16 bit */ 111# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) 112 /* number of vertices */ 113# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 114 115/* BEGIN: Wild guesses */ 116#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 117# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) 118# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) 119# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ 120# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ 121# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ 122# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ 123 124#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 125 /* each of the following is 3 bits wide, specifies number 126 of components */ 127# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 128# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 129# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 130# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 131# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 132# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 133# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 134# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 135/* END: Wild guesses */ 136 137#define R300_SE_VTE_CNTL 0x20b0 138# define R300_VPORT_X_SCALE_ENA 0x00000001 139# define R300_VPORT_X_OFFSET_ENA 0x00000002 140# define R300_VPORT_Y_SCALE_ENA 0x00000004 141# define R300_VPORT_Y_OFFSET_ENA 0x00000008 142# define R300_VPORT_Z_SCALE_ENA 0x00000010 143# define R300_VPORT_Z_OFFSET_ENA 0x00000020 144# define R300_VTX_XY_FMT 0x00000100 145# define R300_VTX_Z_FMT 0x00000200 146# define R300_VTX_W0_FMT 0x00000400 147# define R300_VTX_W0_NORMALIZE 0x00000800 148# define R300_VTX_ST_DENORMALIZED 0x00001000 149 150/* BEGIN: Vertex data assembly - lots of uncertainties */ 151 152/* gap */ 153 154#define R300_VAP_CNTL_STATUS 0x2140 155# define R300_VC_NO_SWAP (0 << 0) 156# define R300_VC_16BIT_SWAP (1 << 0) 157# define R300_VC_32BIT_SWAP (2 << 0) 158# define R300_VAP_TCL_BYPASS (1 << 8) 159 160/* gap */ 161 162/* Where do we get our vertex data? 163 * 164 * Vertex data either comes either from immediate mode registers or from 165 * vertex arrays. 166 * There appears to be no mixed mode (though we can force the pitch of 167 * vertex arrays to 0, effectively reusing the same element over and over 168 * again). 169 * 170 * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure 171 * if these registers influence vertex array processing. 172 * 173 * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. 174 * 175 * In both cases, vertex attributes are then passed through INPUT_ROUTE. 176 * 177 * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data 178 * into the vertex processor's input registers. 179 * The first word routes the first input, the second word the second, etc. 180 * The corresponding input is routed into the register with the given index. 181 * The list is ended by a word with INPUT_ROUTE_END set. 182 * 183 * Always set COMPONENTS_4 in immediate mode. 184 */ 185 186#define R300_VAP_INPUT_ROUTE_0_0 0x2150 187# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) 188# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) 189# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) 190# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) 191# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ 192# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 193# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ 194# define R300_VAP_INPUT_ROUTE_END (1 << 13) 195# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ 196# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ 197# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ 198# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ 199#define R300_VAP_INPUT_ROUTE_0_1 0x2154 200#define R300_VAP_INPUT_ROUTE_0_2 0x2158 201#define R300_VAP_INPUT_ROUTE_0_3 0x215C 202#define R300_VAP_INPUT_ROUTE_0_4 0x2160 203#define R300_VAP_INPUT_ROUTE_0_5 0x2164 204#define R300_VAP_INPUT_ROUTE_0_6 0x2168 205#define R300_VAP_INPUT_ROUTE_0_7 0x216C 206 207/* gap */ 208 209/* Notes: 210 * - always set up to produce at least two attributes: 211 * if vertex program uses only position, fglrx will set normal, too 212 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. 213 */ 214#define R300_VAP_INPUT_CNTL_0 0x2180 215# define R300_INPUT_CNTL_0_COLOR 0x00000001 216#define R300_VAP_INPUT_CNTL_1 0x2184 217# define R300_INPUT_CNTL_POS 0x00000001 218# define R300_INPUT_CNTL_NORMAL 0x00000002 219# define R300_INPUT_CNTL_COLOR 0x00000004 220# define R300_INPUT_CNTL_TC0 0x00000400 221# define R300_INPUT_CNTL_TC1 0x00000800 222# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ 223# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ 224# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ 225# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ 226# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ 227# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ 228 229/* gap */ 230 231/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 232 * are set to a swizzling bit pattern, other words are 0. 233 * 234 * In immediate mode, the pattern is always set to xyzw. In vertex array 235 * mode, the swizzling pattern is e.g. used to set zw components in texture 236 * coordinates with only tweo components. 237 */ 238#define R300_VAP_INPUT_ROUTE_1_0 0x21E0 239# define R300_INPUT_ROUTE_SELECT_X 0 240# define R300_INPUT_ROUTE_SELECT_Y 1 241# define R300_INPUT_ROUTE_SELECT_Z 2 242# define R300_INPUT_ROUTE_SELECT_W 3 243# define R300_INPUT_ROUTE_SELECT_ZERO 4 244# define R300_INPUT_ROUTE_SELECT_ONE 5 245# define R300_INPUT_ROUTE_SELECT_MASK 7 246# define R300_INPUT_ROUTE_X_SHIFT 0 247# define R300_INPUT_ROUTE_Y_SHIFT 3 248# define R300_INPUT_ROUTE_Z_SHIFT 6 249# define R300_INPUT_ROUTE_W_SHIFT 9 250# define R300_INPUT_ROUTE_ENABLE (15 << 12) 251#define R300_VAP_INPUT_ROUTE_1_1 0x21E4 252#define R300_VAP_INPUT_ROUTE_1_2 0x21E8 253#define R300_VAP_INPUT_ROUTE_1_3 0x21EC 254#define R300_VAP_INPUT_ROUTE_1_4 0x21F0 255#define R300_VAP_INPUT_ROUTE_1_5 0x21F4 256#define R300_VAP_INPUT_ROUTE_1_6 0x21F8 257#define R300_VAP_INPUT_ROUTE_1_7 0x21FC 258 259/* END: Vertex data assembly */ 260 261/* gap */ 262 263/* BEGIN: Upload vertex program and data */ 264 265/* 266 * The programmable vertex shader unit has a memory bank of unknown size 267 * that can be written to in 16 byte units by writing the address into 268 * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). 269 * 270 * Pointers into the memory bank are always in multiples of 16 bytes. 271 * 272 * The memory bank is divided into areas with fixed meaning. 273 * 274 * Starting at address UPLOAD_PROGRAM: Vertex program instructions. 275 * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), 276 * whereas the difference between known addresses suggests size 512. 277 * 278 * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. 279 * Native reported limits and the VPI layout suggest size 256, whereas 280 * difference between known addresses suggests size 512. 281 * 282 * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the 283 * floating point pointsize. The exact purpose of this state is uncertain, 284 * as there is also the R300_RE_POINTSIZE register. 285 * 286 * Multiple vertex programs and parameter sets can be loaded at once, 287 * which could explain the size discrepancy. 288 */ 289#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 290# define R300_PVS_UPLOAD_PROGRAM 0x00000000 291# define R300_PVS_UPLOAD_PARAMETERS 0x00000200 292# define R300_PVS_UPLOAD_POINTSIZE 0x00000406 293 294/* gap */ 295 296#define R300_VAP_PVS_UPLOAD_DATA 0x2208 297 298/* END: Upload vertex program and data */ 299 300/* gap */ 301 302/* I do not know the purpose of this register. However, I do know that 303 * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL 304 * for normal rendering. 305 */ 306#define R300_VAP_UNKNOWN_221C 0x221C 307# define R300_221C_NORMAL 0x00000000 308# define R300_221C_CLEAR 0x0001C000 309 310/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first 311 * plane is per-pixel and the second plane is per-vertex. 312 * 313 * This was determined by experimentation alone but I believe it is correct. 314 * 315 * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. 316 */ 317#define R300_VAP_CLIP_X_0 0x2220 318#define R300_VAP_CLIP_X_1 0x2224 319#define R300_VAP_CLIP_Y_0 0x2228 320#define R300_VAP_CLIP_Y_1 0x2230 321 322/* gap */ 323 324/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between 325 * rendering commands and overwriting vertex program parameters. 326 * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and 327 * avoids bugs caused by still running shaders reading bad data from memory. 328 */ 329#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 330 331/* Absolutely no clue what this register is about. */ 332#define R300_VAP_UNKNOWN_2288 0x2288 333# define R300_2288_R300 0x00750000 /* -- nh */ 334# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ 335 336/* gap */ 337 338/* Addresses are relative to the vertex program instruction area of the 339 * memory bank. PROGRAM_END points to the last instruction of the active 340 * program 341 * 342 * The meaning of the two UNKNOWN fields is obviously not known. However, 343 * experiments so far have shown that both *must* point to an instruction 344 * inside the vertex program, otherwise the GPU locks up. 345 * 346 * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and 347 * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to 348 * position takes place. 349 * 350 * Most likely this is used to ignore rest of the program in cases 351 * where group of verts arent visible. For some reason this "section" 352 * is sometimes accepted other instruction that have no relationship with 353 * position calculations. 354 */ 355#define R300_VAP_PVS_CNTL_1 0x22D0 356# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 357# define R300_PVS_CNTL_1_POS_END_SHIFT 10 358# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 359/* Addresses are relative the the vertex program parameters area. */ 360#define R300_VAP_PVS_CNTL_2 0x22D4 361# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 362# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 363#define R300_VAP_PVS_CNTL_3 0x22D8 364# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10 365# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 366 367/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for 368 * immediate vertices 369 */ 370#define R300_VAP_VTX_COLOR_R 0x2464 371#define R300_VAP_VTX_COLOR_G 0x2468 372#define R300_VAP_VTX_COLOR_B 0x246C 373#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ 374#define R300_VAP_VTX_POS_0_Y_1 0x2494 375#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ 376#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ 377#define R300_VAP_VTX_POS_0_Y_2 0x24A4 378#define R300_VAP_VTX_POS_0_Z_2 0x24A8 379/* write 0 to indicate end of packet? */ 380#define R300_VAP_VTX_END_OF_PKT 0x24AC 381 382/* gap */ 383 384/* These are values from r300_reg/r300_reg.h - they are known to be correct 385 * and are here so we can use one register file instead of several 386 * - Vladimir 387 */ 388#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 389# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) 390# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) 391# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) 392# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) 393# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) 394# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) 395# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) 396 397#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 398 /* each of the following is 3 bits wide, specifies number 399 of components */ 400# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 401# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 402# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 403# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 404# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 405# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 406# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 407# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 408 409/* UNK30 seems to enables point to quad transformation on textures 410 * (or something closely related to that). 411 * This bit is rather fatal at the time being due to lackings at pixel 412 * shader side 413 */ 414#define R300_GB_ENABLE 0x4008 415# define R300_GB_POINT_STUFF_ENABLE (1<<0) 416# define R300_GB_LINE_STUFF_ENABLE (1<<1) 417# define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) 418# define R300_GB_STENCIL_AUTO_ENABLE (1<<4) 419# define R300_GB_UNK31 (1<<31) 420 /* each of the following is 2 bits wide */ 421#define R300_GB_TEX_REPLICATE 0 422#define R300_GB_TEX_ST 1 423#define R300_GB_TEX_STR 2 424# define R300_GB_TEX0_SOURCE_SHIFT 16 425# define R300_GB_TEX1_SOURCE_SHIFT 18 426# define R300_GB_TEX2_SOURCE_SHIFT 20 427# define R300_GB_TEX3_SOURCE_SHIFT 22 428# define R300_GB_TEX4_SOURCE_SHIFT 24 429# define R300_GB_TEX5_SOURCE_SHIFT 26 430# define R300_GB_TEX6_SOURCE_SHIFT 28 431# define R300_GB_TEX7_SOURCE_SHIFT 30 432 433/* MSPOS - positions for multisample antialiasing (?) */ 434#define R300_GB_MSPOS0 0x4010 435 /* shifts - each of the fields is 4 bits */ 436# define R300_GB_MSPOS0__MS_X0_SHIFT 0 437# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 438# define R300_GB_MSPOS0__MS_X1_SHIFT 8 439# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 440# define R300_GB_MSPOS0__MS_X2_SHIFT 16 441# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 442# define R300_GB_MSPOS0__MSBD0_Y 24 443# define R300_GB_MSPOS0__MSBD0_X 28 444 445#define R300_GB_MSPOS1 0x4014 446# define R300_GB_MSPOS1__MS_X3_SHIFT 0 447# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 448# define R300_GB_MSPOS1__MS_X4_SHIFT 8 449# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 450# define R300_GB_MSPOS1__MS_X5_SHIFT 16 451# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 452# define R300_GB_MSPOS1__MSBD1 24 453 454 455#define R300_GB_TILE_CONFIG 0x4018 456# define R300_GB_TILE_ENABLE (1<<0) 457# define R300_GB_TILE_PIPE_COUNT_RV300 0 458# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) 459# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) 460# define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1) 461# define R300_GB_TILE_SIZE_8 0 462# define R300_GB_TILE_SIZE_16 (1<<4) 463# define R300_GB_TILE_SIZE_32 (2<<4) 464# define R300_GB_SUPER_SIZE_1 (0<<6) 465# define R300_GB_SUPER_SIZE_2 (1<<6) 466# define R300_GB_SUPER_SIZE_4 (2<<6) 467# define R300_GB_SUPER_SIZE_8 (3<<6) 468# define R300_GB_SUPER_SIZE_16 (4<<6) 469# define R300_GB_SUPER_SIZE_32 (5<<6) 470# define R300_GB_SUPER_SIZE_64 (6<<6) 471# define R300_GB_SUPER_SIZE_128 (7<<6) 472# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ 473# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ 474# define R300_GB_SUPER_TILE_A 0 475# define R300_GB_SUPER_TILE_B (1<<15) 476# define R300_GB_SUBPIXEL_1_12 0 477# define R300_GB_SUBPIXEL_1_16 (1<<16) 478 479#define R300_GB_FIFO_SIZE 0x4024 480 /* each of the following is 2 bits wide */ 481#define R300_GB_FIFO_SIZE_32 0 482#define R300_GB_FIFO_SIZE_64 1 483#define R300_GB_FIFO_SIZE_128 2 484#define R300_GB_FIFO_SIZE_256 3 485# define R300_SC_IFIFO_SIZE_SHIFT 0 486# define R300_SC_TZFIFO_SIZE_SHIFT 2 487# define R300_SC_BFIFO_SIZE_SHIFT 4 488 489# define R300_US_OFIFO_SIZE_SHIFT 12 490# define R300_US_WFIFO_SIZE_SHIFT 14 491 /* the following use the same constants as above, but meaning is 492 is times 2 (i.e. instead of 32 words it means 64 */ 493# define R300_RS_TFIFO_SIZE_SHIFT 6 494# define R300_RS_CFIFO_SIZE_SHIFT 8 495# define R300_US_RAM_SIZE_SHIFT 10 496 /* watermarks, 3 bits wide */ 497# define R300_RS_HIGHWATER_COL_SHIFT 16 498# define R300_RS_HIGHWATER_TEX_SHIFT 19 499# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ 500# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 501 502#define R300_GB_SELECT 0x401C 503# define R300_GB_FOG_SELECT_C0A 0 504# define R300_GB_FOG_SELECT_C1A 1 505# define R300_GB_FOG_SELECT_C2A 2 506# define R300_GB_FOG_SELECT_C3A 3 507# define R300_GB_FOG_SELECT_1_1_W 4 508# define R300_GB_FOG_SELECT_Z 5 509# define R300_GB_DEPTH_SELECT_Z 0 510# define R300_GB_DEPTH_SELECT_1_1_W (1<<3) 511# define R300_GB_W_SELECT_1_W 0 512# define R300_GB_W_SELECT_1 (1<<4) 513 514#define R300_GB_AA_CONFIG 0x4020 515# define R300_AA_DISABLE 0x00 516# define R300_AA_ENABLE 0x01 517# define R300_AA_SUBSAMPLES_2 0 518# define R300_AA_SUBSAMPLES_3 (1<<1) 519# define R300_AA_SUBSAMPLES_4 (2<<1) 520# define R300_AA_SUBSAMPLES_6 (3<<1) 521 522/* gap */ 523 524/* Zero to flush caches. */ 525#define R300_TX_INVALTAGS 0x4100 526#define R300_TX_FLUSH 0x0 527 528/* The upper enable bits are guessed, based on fglrx reported limits. */ 529#define R300_TX_ENABLE 0x4104 530# define R300_TX_ENABLE_0 (1 << 0) 531# define R300_TX_ENABLE_1 (1 << 1) 532# define R300_TX_ENABLE_2 (1 << 2) 533# define R300_TX_ENABLE_3 (1 << 3) 534# define R300_TX_ENABLE_4 (1 << 4) 535# define R300_TX_ENABLE_5 (1 << 5) 536# define R300_TX_ENABLE_6 (1 << 6) 537# define R300_TX_ENABLE_7 (1 << 7) 538# define R300_TX_ENABLE_8 (1 << 8) 539# define R300_TX_ENABLE_9 (1 << 9) 540# define R300_TX_ENABLE_10 (1 << 10) 541# define R300_TX_ENABLE_11 (1 << 11) 542# define R300_TX_ENABLE_12 (1 << 12) 543# define R300_TX_ENABLE_13 (1 << 13) 544# define R300_TX_ENABLE_14 (1 << 14) 545# define R300_TX_ENABLE_15 (1 << 15) 546 547/* The pointsize is given in multiples of 6. The pointsize can be 548 * enormous: Clear() renders a single point that fills the entire 549 * framebuffer. 550 */ 551#define R300_RE_POINTSIZE 0x421C 552# define R300_POINTSIZE_Y_SHIFT 0 553# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ 554# define R300_POINTSIZE_X_SHIFT 16 555# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ 556# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) 557 558/* The line width is given in multiples of 6. 559 * In default mode lines are classified as vertical lines. 560 * HO: horizontal 561 * VE: vertical or horizontal 562 * HO & VE: no classification 563 */ 564#define R300_RE_LINE_CNT 0x4234 565# define R300_LINESIZE_SHIFT 0 566# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ 567# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) 568# define R300_LINE_CNT_HO (1 << 16) 569# define R300_LINE_CNT_VE (1 << 17) 570 571/* Some sort of scale or clamp value for texcoordless textures. */ 572#define R300_RE_UNK4238 0x4238 573 574/* Something shade related */ 575#define R300_RE_SHADE 0x4274 576 577#define R300_RE_SHADE_MODEL 0x4278 578# define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa 579# define R300_RE_SHADE_MODEL_FLAT 0x39595 580 581/* Dangerous */ 582#define R300_RE_POLYGON_MODE 0x4288 583# define R300_PM_ENABLED (1 << 0) 584# define R300_PM_FRONT_POINT (0 << 0) 585# define R300_PM_BACK_POINT (0 << 0) 586# define R300_PM_FRONT_LINE (1 << 4) 587# define R300_PM_FRONT_FILL (1 << 5) 588# define R300_PM_BACK_LINE (1 << 7) 589# define R300_PM_BACK_FILL (1 << 8) 590 591/* Fog parameters */ 592#define R300_RE_FOG_SCALE 0x4294 593#define R300_RE_FOG_START 0x4298 594 595/* Not sure why there are duplicate of factor and constant values. 596 * My best guess so far is that there are separate zbiases for test and write. 597 * Ordering might be wrong. 598 * Some of the tests indicate that fgl has a fallback implementation of zbias 599 * via pixel shaders. 600 */ 601#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */ 602#define R300_RE_ZBIAS_T_FACTOR 0x42A4 603#define R300_RE_ZBIAS_T_CONSTANT 0x42A8 604#define R300_RE_ZBIAS_W_FACTOR 0x42AC 605#define R300_RE_ZBIAS_W_CONSTANT 0x42B0 606 607/* This register needs to be set to (1<<1) for RV350 to correctly 608 * perform depth test (see --vb-triangles in r300_demo) 609 * Don't know about other chips. - Vladimir 610 * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. 611 * My guess is that there are two bits for each zbias primitive 612 * (FILL, LINE, POINT). 613 * One to enable depth test and one for depth write. 614 * Yet this doesn't explain why depth writes work ... 615 */ 616#define R300_RE_OCCLUSION_CNTL 0x42B4 617# define R300_OCCLUSION_ON (1<<1) 618 619#define R300_RE_CULL_CNTL 0x42B8 620# define R300_CULL_FRONT (1 << 0) 621# define R300_CULL_BACK (1 << 1) 622# define R300_FRONT_FACE_CCW (0 << 2) 623# define R300_FRONT_FACE_CW (1 << 2) 624 625 626/* BEGIN: Rasterization / Interpolators - many guesses */ 627 628/* 0_UNKNOWN_18 has always been set except for clear operations. 629 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends 630 * on the vertex program, *not* the fragment program) 631 */ 632#define R300_RS_CNTL_0 0x4300 633# define R300_RS_CNTL_TC_CNT_SHIFT 2 634# define R300_RS_CNTL_TC_CNT_MASK (7 << 2) 635 /* number of color interpolators used */ 636# define R300_RS_CNTL_CI_CNT_SHIFT 7 637# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) 638 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n 639 register. */ 640#define R300_RS_CNTL_1 0x4304 641 642/* gap */ 643 644/* Only used for texture coordinates. 645 * Use the source field to route texture coordinate input from the 646 * vertex program to the desired interpolator. Note that the source 647 * field is relative to the outputs the vertex program *actually* 648 * writes. If a vertex program only writes texcoord[1], this will 649 * be source index 0. 650 * Set INTERP_USED on all interpolators that produce data used by 651 * the fragment program. INTERP_USED looks like a swizzling mask, 652 * but I haven't seen it used that way. 653 * 654 * Note: The _UNKNOWN constants are always set in their respective 655 * register. I don't know if this is necessary. 656 */ 657#define R300_RS_INTERP_0 0x4310 658#define R300_RS_INTERP_1 0x4314 659# define R300_RS_INTERP_1_UNKNOWN 0x40 660#define R300_RS_INTERP_2 0x4318 661# define R300_RS_INTERP_2_UNKNOWN 0x80 662#define R300_RS_INTERP_3 0x431C 663# define R300_RS_INTERP_3_UNKNOWN 0xC0 664#define R300_RS_INTERP_4 0x4320 665#define R300_RS_INTERP_5 0x4324 666#define R300_RS_INTERP_6 0x4328 667#define R300_RS_INTERP_7 0x432C 668# define R300_RS_INTERP_SRC_SHIFT 2 669# define R300_RS_INTERP_SRC_MASK (7 << 2) 670# define R300_RS_INTERP_USED 0x00D10000 671 672/* These DWORDs control how vertex data is routed into fragment program 673 * registers, after interpolators. 674 */ 675#define R300_RS_ROUTE_0 0x4330 676#define R300_RS_ROUTE_1 0x4334 677#define R300_RS_ROUTE_2 0x4338 678#define R300_RS_ROUTE_3 0x433C /* GUESS */ 679#define R300_RS_ROUTE_4 0x4340 /* GUESS */ 680#define R300_RS_ROUTE_5 0x4344 /* GUESS */ 681#define R300_RS_ROUTE_6 0x4348 /* GUESS */ 682#define R300_RS_ROUTE_7 0x434C /* GUESS */ 683# define R300_RS_ROUTE_SOURCE_INTERP_0 0 684# define R300_RS_ROUTE_SOURCE_INTERP_1 1 685# define R300_RS_ROUTE_SOURCE_INTERP_2 2 686# define R300_RS_ROUTE_SOURCE_INTERP_3 3 687# define R300_RS_ROUTE_SOURCE_INTERP_4 4 688# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ 689# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ 690# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ 691# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ 692# define R300_RS_ROUTE_DEST_SHIFT 6 693# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ 694 695/* Special handling for color: When the fragment program uses color, 696 * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the 697 * color register index. 698 * 699 * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any 700 * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state. 701 * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly 702 * correct or not. - Oliver. 703 */ 704# define R300_RS_ROUTE_0_COLOR (1 << 14) 705# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 706# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ 707/* As above, but for secondary color */ 708# define R300_RS_ROUTE_1_COLOR1 (1 << 14) 709# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 710# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) 711# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 712/* END: Rasterization / Interpolators - many guesses */ 713 714/* Hierarchical Z Enable */ 715#define R300_SC_HYPERZ 0x43a4 716# define R300_SC_HYPERZ_DISABLE (0 << 0) 717# define R300_SC_HYPERZ_ENABLE (1 << 0) 718# define R300_SC_HYPERZ_MIN (0 << 1) 719# define R300_SC_HYPERZ_MAX (1 << 1) 720# define R300_SC_HYPERZ_ADJ_256 (0 << 2) 721# define R300_SC_HYPERZ_ADJ_128 (1 << 2) 722# define R300_SC_HYPERZ_ADJ_64 (2 << 2) 723# define R300_SC_HYPERZ_ADJ_32 (3 << 2) 724# define R300_SC_HYPERZ_ADJ_16 (4 << 2) 725# define R300_SC_HYPERZ_ADJ_8 (5 << 2) 726# define R300_SC_HYPERZ_ADJ_4 (6 << 2) 727# define R300_SC_HYPERZ_ADJ_2 (7 << 2) 728# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) 729# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) 730# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) 731# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) 732 733#define R300_SC_EDGERULE 0x43a8 734 735/* BEGIN: Scissors and cliprects */ 736 737/* There are four clipping rectangles. Their corner coordinates are inclusive. 738 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending 739 * on whether the pixel is inside cliprects 0-3, respectively. For example, 740 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned 741 * the number 3 (binary 0011). 742 * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, 743 * the pixel is rasterized. 744 * 745 * In addition to this, there is a scissors rectangle. Only pixels inside the 746 * scissors rectangle are drawn. (coordinates are inclusive) 747 * 748 * For some reason, the top-left corner of the framebuffer is at (1440, 1440) 749 * for the purpose of clipping and scissors. 750 */ 751#define R300_RE_CLIPRECT_TL_0 0x43B0 752#define R300_RE_CLIPRECT_BR_0 0x43B4 753#define R300_RE_CLIPRECT_TL_1 0x43B8 754#define R300_RE_CLIPRECT_BR_1 0x43BC 755#define R300_RE_CLIPRECT_TL_2 0x43C0 756#define R300_RE_CLIPRECT_BR_2 0x43C4 757#define R300_RE_CLIPRECT_TL_3 0x43C8 758#define R300_RE_CLIPRECT_BR_3 0x43CC 759# define R300_CLIPRECT_OFFSET 1440 760# define R300_CLIPRECT_MASK 0x1FFF 761# define R300_CLIPRECT_X_SHIFT 0 762# define R300_CLIPRECT_X_MASK (0x1FFF << 0) 763# define R300_CLIPRECT_Y_SHIFT 13 764# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) 765#define R300_RE_CLIPRECT_CNTL 0x43D0 766# define R300_CLIP_OUT (1 << 0) 767# define R300_CLIP_0 (1 << 1) 768# define R300_CLIP_1 (1 << 2) 769# define R300_CLIP_10 (1 << 3) 770# define R300_CLIP_2 (1 << 4) 771# define R300_CLIP_20 (1 << 5) 772# define R300_CLIP_21 (1 << 6) 773# define R300_CLIP_210 (1 << 7) 774# define R300_CLIP_3 (1 << 8) 775# define R300_CLIP_30 (1 << 9) 776# define R300_CLIP_31 (1 << 10) 777# define R300_CLIP_310 (1 << 11) 778# define R300_CLIP_32 (1 << 12) 779# define R300_CLIP_320 (1 << 13) 780# define R300_CLIP_321 (1 << 14) 781# define R300_CLIP_3210 (1 << 15) 782 783/* gap */ 784 785#define R300_RE_SCISSORS_TL 0x43E0 786#define R300_RE_SCISSORS_BR 0x43E4 787# define R300_SCISSORS_OFFSET 1440 788# define R300_SCISSORS_X_SHIFT 0 789# define R300_SCISSORS_X_MASK (0x1FFF << 0) 790# define R300_SCISSORS_Y_SHIFT 13 791# define R300_SCISSORS_Y_MASK (0x1FFF << 13) 792/* END: Scissors and cliprects */ 793 794/* BEGIN: Texture specification */ 795 796/* 797 * The texture specification dwords are grouped by meaning and not by texture 798 * unit. This means that e.g. the offset for texture image unit N is found in 799 * register TX_OFFSET_0 + (4*N) 800 */ 801#define R300_TX_FILTER_0 0x4400 802# define R300_TX_REPEAT 0 803# define R300_TX_MIRRORED 1 804# define R300_TX_CLAMP 4 805# define R300_TX_CLAMP_TO_EDGE 2 806# define R300_TX_CLAMP_TO_BORDER 6 807# define R300_TX_WRAP_S_SHIFT 0 808# define R300_TX_WRAP_S_MASK (7 << 0) 809# define R300_TX_WRAP_T_SHIFT 3 810# define R300_TX_WRAP_T_MASK (7 << 3) 811# define R300_TX_WRAP_Q_SHIFT 6 812# define R300_TX_WRAP_Q_MASK (7 << 6) 813# define R300_TX_MAG_FILTER_NEAREST (1 << 9) 814# define R300_TX_MAG_FILTER_LINEAR (2 << 9) 815# define R300_TX_MAG_FILTER_MASK (3 << 9) 816# define R300_TX_MIN_FILTER_NEAREST (1 << 11) 817# define R300_TX_MIN_FILTER_LINEAR (2 << 11) 818# define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) 819# define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) 820# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) 821# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) 822 823/* NOTE: NEAREST doesn't seem to exist. 824 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all 825 * anisotropy modes because that would void selected mag filter 826 */ 827# define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13) 828# define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13) 829# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13) 830# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13) 831# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) 832# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) 833# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) 834# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) 835# define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) 836# define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) 837# define R300_TX_MAX_ANISO_MASK (14 << 21) 838 839#define R300_TX_FILTER1_0 0x4440 840# define R300_CHROMA_KEY_MODE_DISABLE 0 841# define R300_CHROMA_KEY_FORCE 1 842# define R300_CHROMA_KEY_BLEND 2 843# define R300_MC_ROUND_NORMAL (0<<2) 844# define R300_MC_ROUND_MPEG4 (1<<2) 845# define R300_LOD_BIAS_MASK 0x1fff 846# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) 847# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) 848# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) 849# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) 850# define R300_TX_TRI_PERF_0_8 (0<<15) 851# define R300_TX_TRI_PERF_1_8 (1<<15) 852# define R300_TX_TRI_PERF_1_4 (2<<15) 853# define R300_TX_TRI_PERF_3_8 (3<<15) 854# define R300_ANISO_THRESHOLD_MASK (7<<17) 855 856#define R300_TX_SIZE_0 0x4480 857# define R300_TX_WIDTHMASK_SHIFT 0 858# define R300_TX_WIDTHMASK_MASK (2047 << 0) 859# define R300_TX_HEIGHTMASK_SHIFT 11 860# define R300_TX_HEIGHTMASK_MASK (2047 << 11) 861# define R300_TX_UNK23 (1 << 23) 862# define R300_TX_MAX_MIP_LEVEL_SHIFT 26 863# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26) 864# define R300_TX_SIZE_PROJECTED (1<<30) 865# define R300_TX_SIZE_TXPITCH_EN (1<<31) 866#define R300_TX_FORMAT_0 0x44C0 867 /* The interpretation of the format word by Wladimir van der Laan */ 868 /* The X, Y, Z and W refer to the layout of the components. 869 They are given meanings as R, G, B and Alpha by the swizzle 870 specification */ 871# define R300_TX_FORMAT_X8 0x0 872# define R300_TX_FORMAT_X16 0x1 873# define R300_TX_FORMAT_Y4X4 0x2 874# define R300_TX_FORMAT_Y8X8 0x3 875# define R300_TX_FORMAT_Y16X16 0x4 876# define R300_TX_FORMAT_Z3Y3X2 0x5 877# define R300_TX_FORMAT_Z5Y6X5 0x6 878# define R300_TX_FORMAT_Z6Y5X5 0x7 879# define R300_TX_FORMAT_Z11Y11X10 0x8 880# define R300_TX_FORMAT_Z10Y11X11 0x9 881# define R300_TX_FORMAT_W4Z4Y4X4 0xA 882# define R300_TX_FORMAT_W1Z5Y5X5 0xB 883# define R300_TX_FORMAT_W8Z8Y8X8 0xC 884# define R300_TX_FORMAT_W2Z10Y10X10 0xD 885# define R300_TX_FORMAT_W16Z16Y16X16 0xE 886# define R300_TX_FORMAT_DXT1 0xF 887# define R300_TX_FORMAT_DXT3 0x10 888# define R300_TX_FORMAT_DXT5 0x11 889# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ 890# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ 891# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ 892# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ 893 /* 0x16 - some 16 bit green format.. ?? */ 894# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ 895# define R300_TX_FORMAT_CUBIC_MAP (1 << 26) 896 897 /* gap */ 898 /* Floating point formats */ 899 /* Note - hardware supports both 16 and 32 bit floating point */ 900# define R300_TX_FORMAT_FL_I16 0x18 901# define R300_TX_FORMAT_FL_I16A16 0x19 902# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A 903# define R300_TX_FORMAT_FL_I32 0x1B 904# define R300_TX_FORMAT_FL_I32A32 0x1C 905# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D 906# define R300_TX_FORMAT_ATI2N 0x1F 907 /* alpha modes, convenience mostly */ 908 /* if you have alpha, pick constant appropriate to the 909 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ 910# define R300_TX_FORMAT_ALPHA_1CH 0x000 911# define R300_TX_FORMAT_ALPHA_2CH 0x200 912# define R300_TX_FORMAT_ALPHA_4CH 0x600 913# define R300_TX_FORMAT_ALPHA_NONE 0xA00 914 /* Swizzling */ 915 /* constants */ 916# define R300_TX_FORMAT_X 0 917# define R300_TX_FORMAT_Y 1 918# define R300_TX_FORMAT_Z 2 919# define R300_TX_FORMAT_W 3 920# define R300_TX_FORMAT_ZERO 4 921# define R300_TX_FORMAT_ONE 5 922 /* 2.0*Z, everything above 1.0 is set to 0.0 */ 923# define R300_TX_FORMAT_CUT_Z 6 924 /* 2.0*W, everything above 1.0 is set to 0.0 */ 925# define R300_TX_FORMAT_CUT_W 7 926 927# define R300_TX_FORMAT_B_SHIFT 18 928# define R300_TX_FORMAT_G_SHIFT 15 929# define R300_TX_FORMAT_R_SHIFT 12 930# define R300_TX_FORMAT_A_SHIFT 9 931 /* Convenience macro to take care of layout and swizzling */ 932# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ 933 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ 934 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ 935 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ 936 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ 937 | (R300_TX_FORMAT_##FMT) \ 938 ) 939 /* These can be ORed with result of R300_EASY_TX_FORMAT() 940 We don't really know what they do. Take values from a 941 constant color ? */ 942# define R300_TX_FORMAT_CONST_X (1<<5) 943# define R300_TX_FORMAT_CONST_Y (2<<5) 944# define R300_TX_FORMAT_CONST_Z (4<<5) 945# define R300_TX_FORMAT_CONST_W (8<<5) 946 947# define R300_TX_FORMAT_YUV_MODE 0x00800000 948 949#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */ 950#define R300_TX_OFFSET_0 0x4540 951 /* BEGIN: Guess from R200 */ 952# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) 953# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) 954# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) 955# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 956# define R300_TXO_MACRO_TILE (1 << 2) 957# define R300_TXO_MICRO_TILE (1 << 3) 958# define R300_TXO_MICRO_TILE_SQUARE (2 << 3) 959# define R300_TXO_OFFSET_MASK 0xffffffe0 960# define R300_TXO_OFFSET_SHIFT 5 961 /* END: Guess from R200 */ 962 963/* 32 bit chroma key */ 964#define R300_TX_CHROMA_KEY_0 0x4580 965/* ff00ff00 == { 0, 1.0, 0, 1.0 } */ 966#define R300_TX_BORDER_COLOR_0 0x45C0 967 968/* END: Texture specification */ 969 970/* BEGIN: Fragment program instruction set */ 971 972/* Fragment programs are written directly into register space. 973 * There are separate instruction streams for texture instructions and ALU 974 * instructions. 975 * In order to synchronize these streams, the program is divided into up 976 * to 4 nodes. Each node begins with a number of TEX operations, followed 977 * by a number of ALU operations. 978 * The first node can have zero TEX ops, all subsequent nodes must have at 979 * least 980 * one TEX ops. 981 * All nodes must have at least one ALU op. 982 * 983 * The index of the last node is stored in PFS_CNTL_0: A value of 0 means 984 * 1 node, a value of 3 means 4 nodes. 985 * The total amount of instructions is defined in PFS_CNTL_2. The offsets are 986 * offsets into the respective instruction streams, while *_END points to the 987 * last instruction relative to this offset. 988 */ 989#define R300_PFS_CNTL_0 0x4600 990# define R300_PFS_CNTL_LAST_NODES_SHIFT 0 991# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) 992# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) 993#define R300_PFS_CNTL_1 0x4604 994/* There is an unshifted value here which has so far always been equal to the 995 * index of the highest used temporary register. 996 */ 997#define R300_PFS_CNTL_2 0x4608 998# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 999# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) 1000# define R300_PFS_CNTL_ALU_END_SHIFT 6 1001# define R300_PFS_CNTL_ALU_END_MASK (63 << 6) 1002# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 1003# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ 1004# define R300_PFS_CNTL_TEX_END_SHIFT 18 1005# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ 1006 1007/* gap */ 1008 1009/* Nodes are stored backwards. The last active node is always stored in 1010 * PFS_NODE_3. 1011 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The 1012 * first node is stored in NODE_2, the second node is stored in NODE_3. 1013 * 1014 * Offsets are relative to the master offset from PFS_CNTL_2. 1015 */ 1016#define R300_PFS_NODE_0 0x4610 1017#define R300_PFS_NODE_1 0x4614 1018#define R300_PFS_NODE_2 0x4618 1019#define R300_PFS_NODE_3 0x461C 1020# define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 1021# define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) 1022# define R300_PFS_NODE_ALU_END_SHIFT 6 1023# define R300_PFS_NODE_ALU_END_MASK (63 << 6) 1024# define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 1025# define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) 1026# define R300_PFS_NODE_TEX_END_SHIFT 17 1027# define R300_PFS_NODE_TEX_END_MASK (31 << 17) 1028# define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) 1029# define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) 1030 1031/* TEX 1032 * As far as I can tell, texture instructions cannot write into output 1033 * registers directly. A subsequent ALU instruction is always necessary, 1034 * even if it's just MAD o0, r0, 1, 0 1035 */ 1036#define R300_PFS_TEXI_0 0x4620 1037# define R300_FPITX_SRC_SHIFT 0 1038# define R300_FPITX_SRC_MASK (31 << 0) 1039 /* GUESS */ 1040# define R300_FPITX_SRC_CONST (1 << 5) 1041# define R300_FPITX_DST_SHIFT 6 1042# define R300_FPITX_DST_MASK (31 << 6) 1043# define R300_FPITX_IMAGE_SHIFT 11 1044 /* GUESS based on layout and native limits */ 1045# define R300_FPITX_IMAGE_MASK (15 << 11) 1046/* Unsure if these are opcodes, or some kind of bitfield, but this is how 1047 * they were set when I checked 1048 */ 1049# define R300_FPITX_OPCODE_SHIFT 15 1050# define R300_FPITX_OP_TEX 1 1051# define R300_FPITX_OP_KIL 2 1052# define R300_FPITX_OP_TXP 3 1053# define R300_FPITX_OP_TXB 4 1054# define R300_FPITX_OPCODE_MASK (7 << 15) 1055 1056/* ALU 1057 * The ALU instructions register blocks are enumerated according to the order 1058 * in which fglrx. I assume there is space for 64 instructions, since 1059 * each block has space for a maximum of 64 DWORDs, and this matches reported 1060 * native limits. 1061 * 1062 * The basic functional block seems to be one MAD for each color and alpha, 1063 * and an adder that adds all components after the MUL. 1064 * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands 1065 * - DP4: Use OUTC_DP4, OUTA_DP4 1066 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands 1067 * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands 1068 * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1 1069 * - CMP: If ARG2 < 0, return ARG1, else return ARG0 1070 * - FLR: use FRC+MAD 1071 * - XPD: use MAD+MAD 1072 * - SGE, SLT: use MAD+CMP 1073 * - RSQ: use ABS modifier for argument 1074 * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation 1075 * (e.g. RCP) into color register 1076 * - apparently, there's no quick DST operation 1077 * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" 1078 * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" 1079 * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" 1080 * 1081 * Operand selection 1082 * First stage selects three sources from the available registers and 1083 * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). 1084 * fglrx sorts the three source fields: Registers before constants, 1085 * lower indices before higher indices; I do not know whether this is 1086 * necessary. 1087 * 1088 * fglrx fills unused sources with "read constant 0" 1089 * According to specs, you cannot select more than two different constants. 1090 * 1091 * Second stage selects the operands from the sources. This is defined in 1092 * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants 1093 * zero and one. 1094 * Swizzling and negation happens in this stage, as well. 1095 * 1096 * Important: Color and alpha seem to be mostly separate, i.e. their sources 1097 * selection appears to be fully independent (the register storage is probably 1098 * physically split into a color and an alpha section). 1099 * However (because of the apparent physical split), there is some interaction 1100 * WRT swizzling. If, for example, you want to load an R component into an 1101 * Alpha operand, this R component is taken from a *color* source, not from 1102 * an alpha source. The corresponding register doesn't even have to appear in 1103 * the alpha sources list. (I hope this all makes sense to you) 1104 * 1105 * Destination selection 1106 * The destination register index is in FPI1 (color) and FPI3 (alpha) 1107 * together with enable bits. 1108 * There are separate enable bits for writing into temporary registers 1109 * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* 1110 * /DSTA_OUTPUT). You can write to both at once, or not write at all (the 1111 * same index must be used for both). 1112 * 1113 * Note: There is a special form for LRP 1114 * - Argument order is the same as in ARB_fragment_program. 1115 * - Operation is MAD 1116 * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP 1117 * - Set FPI0/FPI2_SPECIAL_LRP 1118 * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD 1119 */ 1120#define R300_PFS_INSTR1_0 0x46C0 1121# define R300_FPI1_SRC0C_SHIFT 0 1122# define R300_FPI1_SRC0C_MASK (31 << 0) 1123# define R300_FPI1_SRC0C_CONST (1 << 5) 1124# define R300_FPI1_SRC1C_SHIFT 6 1125# define R300_FPI1_SRC1C_MASK (31 << 6) 1126# define R300_FPI1_SRC1C_CONST (1 << 11) 1127# define R300_FPI1_SRC2C_SHIFT 12 1128# define R300_FPI1_SRC2C_MASK (31 << 12) 1129# define R300_FPI1_SRC2C_CONST (1 << 17) 1130# define R300_FPI1_SRC_MASK 0x0003ffff 1131# define R300_FPI1_DSTC_SHIFT 18 1132# define R300_FPI1_DSTC_MASK (31 << 18) 1133# define R300_FPI1_DSTC_REG_MASK_SHIFT 23 1134# define R300_FPI1_DSTC_REG_X (1 << 23) 1135# define R300_FPI1_DSTC_REG_Y (1 << 24) 1136# define R300_FPI1_DSTC_REG_Z (1 << 25) 1137# define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26 1138# define R300_FPI1_DSTC_OUTPUT_X (1 << 26) 1139# define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) 1140# define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) 1141 1142#define R300_PFS_INSTR3_0 0x47C0 1143# define R300_FPI3_SRC0A_SHIFT 0 1144# define R300_FPI3_SRC0A_MASK (31 << 0) 1145# define R300_FPI3_SRC0A_CONST (1 << 5) 1146# define R300_FPI3_SRC1A_SHIFT 6 1147# define R300_FPI3_SRC1A_MASK (31 << 6) 1148# define R300_FPI3_SRC1A_CONST (1 << 11) 1149# define R300_FPI3_SRC2A_SHIFT 12 1150# define R300_FPI3_SRC2A_MASK (31 << 12) 1151# define R300_FPI3_SRC2A_CONST (1 << 17) 1152# define R300_FPI3_SRC_MASK 0x0003ffff 1153# define R300_FPI3_DSTA_SHIFT 18 1154# define R300_FPI3_DSTA_MASK (31 << 18) 1155# define R300_FPI3_DSTA_REG (1 << 23) 1156# define R300_FPI3_DSTA_OUTPUT (1 << 24) 1157# define R300_FPI3_DSTA_DEPTH (1 << 27) 1158 1159#define R300_PFS_INSTR0_0 0x48C0 1160# define R300_FPI0_ARGC_SRC0C_XYZ 0 1161# define R300_FPI0_ARGC_SRC0C_XXX 1 1162# define R300_FPI0_ARGC_SRC0C_YYY 2 1163# define R300_FPI0_ARGC_SRC0C_ZZZ 3 1164# define R300_FPI0_ARGC_SRC1C_XYZ 4 1165# define R300_FPI0_ARGC_SRC1C_XXX 5 1166# define R300_FPI0_ARGC_SRC1C_YYY 6 1167# define R300_FPI0_ARGC_SRC1C_ZZZ 7 1168# define R300_FPI0_ARGC_SRC2C_XYZ 8 1169# define R300_FPI0_ARGC_SRC2C_XXX 9 1170# define R300_FPI0_ARGC_SRC2C_YYY 10 1171# define R300_FPI0_ARGC_SRC2C_ZZZ 11 1172# define R300_FPI0_ARGC_SRC0A 12 1173# define R300_FPI0_ARGC_SRC1A 13 1174# define R300_FPI0_ARGC_SRC2A 14 1175# define R300_FPI0_ARGC_SRC1C_LRP 15 1176# define R300_FPI0_ARGC_ZERO 20 1177# define R300_FPI0_ARGC_ONE 21 1178 /* GUESS */ 1179# define R300_FPI0_ARGC_HALF 22 1180# define R300_FPI0_ARGC_SRC0C_YZX 23 1181# define R300_FPI0_ARGC_SRC1C_YZX 24 1182# define R300_FPI0_ARGC_SRC2C_YZX 25 1183# define R300_FPI0_ARGC_SRC0C_ZXY 26 1184# define R300_FPI0_ARGC_SRC1C_ZXY 27 1185# define R300_FPI0_ARGC_SRC2C_ZXY 28 1186# define R300_FPI0_ARGC_SRC0CA_WZY 29 1187# define R300_FPI0_ARGC_SRC1CA_WZY 30 1188# define R300_FPI0_ARGC_SRC2CA_WZY 31 1189 1190# define R300_FPI0_ARG0C_SHIFT 0 1191# define R300_FPI0_ARG0C_MASK (31 << 0) 1192# define R300_FPI0_ARG0C_NEG (1 << 5) 1193# define R300_FPI0_ARG0C_ABS (1 << 6) 1194# define R300_FPI0_ARG1C_SHIFT 7 1195# define R300_FPI0_ARG1C_MASK (31 << 7) 1196# define R300_FPI0_ARG1C_NEG (1 << 12) 1197# define R300_FPI0_ARG1C_ABS (1 << 13) 1198# define R300_FPI0_ARG2C_SHIFT 14 1199# define R300_FPI0_ARG2C_MASK (31 << 14) 1200# define R300_FPI0_ARG2C_NEG (1 << 19) 1201# define R300_FPI0_ARG2C_ABS (1 << 20) 1202# define R300_FPI0_SPECIAL_LRP (1 << 21) 1203# define R300_FPI0_OUTC_MAD (0 << 23) 1204# define R300_FPI0_OUTC_DP3 (1 << 23) 1205# define R300_FPI0_OUTC_DP4 (2 << 23) 1206# define R300_FPI0_OUTC_MIN (4 << 23) 1207# define R300_FPI0_OUTC_MAX (5 << 23) 1208# define R300_FPI0_OUTC_CMPH (7 << 23) 1209# define R300_FPI0_OUTC_CMP (8 << 23) 1210# define R300_FPI0_OUTC_FRC (9 << 23) 1211# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) 1212# define R300_FPI0_OUTC_SAT (1 << 30) 1213# define R300_FPI0_INSERT_NOP (1U << 31) 1214 1215#define R300_PFS_INSTR2_0 0x49C0 1216# define R300_FPI2_ARGA_SRC0C_X 0 1217# define R300_FPI2_ARGA_SRC0C_Y 1 1218# define R300_FPI2_ARGA_SRC0C_Z 2 1219# define R300_FPI2_ARGA_SRC1C_X 3 1220# define R300_FPI2_ARGA_SRC1C_Y 4 1221# define R300_FPI2_ARGA_SRC1C_Z 5 1222# define R300_FPI2_ARGA_SRC2C_X 6 1223# define R300_FPI2_ARGA_SRC2C_Y 7 1224# define R300_FPI2_ARGA_SRC2C_Z 8 1225# define R300_FPI2_ARGA_SRC0A 9 1226# define R300_FPI2_ARGA_SRC1A 10 1227# define R300_FPI2_ARGA_SRC2A 11 1228# define R300_FPI2_ARGA_SRC1A_LRP 15 1229# define R300_FPI2_ARGA_ZERO 16 1230# define R300_FPI2_ARGA_ONE 17 1231 /* GUESS */ 1232# define R300_FPI2_ARGA_HALF 18 1233# define R300_FPI2_ARG0A_SHIFT 0 1234# define R300_FPI2_ARG0A_MASK (31 << 0) 1235# define R300_FPI2_ARG0A_NEG (1 << 5) 1236 /* GUESS */ 1237# define R300_FPI2_ARG0A_ABS (1 << 6) 1238# define R300_FPI2_ARG1A_SHIFT 7 1239# define R300_FPI2_ARG1A_MASK (31 << 7) 1240# define R300_FPI2_ARG1A_NEG (1 << 12) 1241 /* GUESS */ 1242# define R300_FPI2_ARG1A_ABS (1 << 13) 1243# define R300_FPI2_ARG2A_SHIFT 14 1244# define R300_FPI2_ARG2A_MASK (31 << 14) 1245# define R300_FPI2_ARG2A_NEG (1 << 19) 1246 /* GUESS */ 1247# define R300_FPI2_ARG2A_ABS (1 << 20) 1248# define R300_FPI2_SPECIAL_LRP (1 << 21) 1249# define R300_FPI2_OUTA_MAD (0 << 23) 1250# define R300_FPI2_OUTA_DP4 (1 << 23) 1251# define R300_FPI2_OUTA_MIN (2 << 23) 1252# define R300_FPI2_OUTA_MAX (3 << 23) 1253# define R300_FPI2_OUTA_CMP (6 << 23) 1254# define R300_FPI2_OUTA_FRC (7 << 23) 1255# define R300_FPI2_OUTA_EX2 (8 << 23) 1256# define R300_FPI2_OUTA_LG2 (9 << 23) 1257# define R300_FPI2_OUTA_RCP (10 << 23) 1258# define R300_FPI2_OUTA_RSQ (11 << 23) 1259# define R300_FPI2_OUTA_SAT (1 << 30) 1260# define R300_FPI2_UNKNOWN_31 (1U << 31) 1261/* END: Fragment program instruction set */ 1262 1263/* Fog state and color */ 1264#define R300_RE_FOG_STATE 0x4BC0 1265# define R300_FOG_ENABLE (1 << 0) 1266# define R300_FOG_MODE_LINEAR (0 << 1) 1267# define R300_FOG_MODE_EXP (1 << 1) 1268# define R300_FOG_MODE_EXP2 (2 << 1) 1269# define R300_FOG_MODE_MASK (3 << 1) 1270#define R300_FOG_COLOR_R 0x4BC8 1271#define R300_FOG_COLOR_G 0x4BCC 1272#define R300_FOG_COLOR_B 0x4BD0 1273 1274#define R300_PP_ALPHA_TEST 0x4BD4 1275# define R300_REF_ALPHA_MASK 0x000000ff 1276# define R300_ALPHA_TEST_FAIL (0 << 8) 1277# define R300_ALPHA_TEST_LESS (1 << 8) 1278# define R300_ALPHA_TEST_LEQUAL (3 << 8) 1279# define R300_ALPHA_TEST_EQUAL (2 << 8) 1280# define R300_ALPHA_TEST_GEQUAL (6 << 8) 1281# define R300_ALPHA_TEST_GREATER (4 << 8) 1282# define R300_ALPHA_TEST_NEQUAL (5 << 8) 1283# define R300_ALPHA_TEST_PASS (7 << 8) 1284# define R300_ALPHA_TEST_OP_MASK (7 << 8) 1285# define R300_ALPHA_TEST_ENABLE (1 << 11) 1286 1287/* gap */ 1288 1289/* Fragment program parameters in 7.16 floating point */ 1290#define R300_PFS_PARAM_0_X 0x4C00 1291#define R300_PFS_PARAM_0_Y 0x4C04 1292#define R300_PFS_PARAM_0_Z 0x4C08 1293#define R300_PFS_PARAM_0_W 0x4C0C 1294/* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ 1295#define R300_PFS_PARAM_31_X 0x4DF0 1296#define R300_PFS_PARAM_31_Y 0x4DF4 1297#define R300_PFS_PARAM_31_Z 0x4DF8 1298#define R300_PFS_PARAM_31_W 0x4DFC 1299 1300/* Notes: 1301 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in 1302 * the application 1303 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND 1304 * are set to the same 1305 * function (both registers are always set up completely in any case) 1306 * - Most blend flags are simply copied from R200 and not tested yet 1307 */ 1308#define R300_RB3D_CBLEND 0x4E04 1309#define R300_RB3D_ABLEND 0x4E08 1310/* the following only appear in CBLEND */ 1311# define R300_BLEND_ENABLE (1 << 0) 1312# define R300_BLEND_UNKNOWN (3 << 1) 1313# define R300_BLEND_NO_SEPARATE (1 << 3) 1314/* the following are shared between CBLEND and ABLEND */ 1315# define R300_FCN_MASK (3 << 12) 1316# define R300_COMB_FCN_ADD_CLAMP (0 << 12) 1317# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) 1318# define R300_COMB_FCN_SUB_CLAMP (2 << 12) 1319# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) 1320# define R300_COMB_FCN_MIN (4 << 12) 1321# define R300_COMB_FCN_MAX (5 << 12) 1322# define R300_COMB_FCN_RSUB_CLAMP (6 << 12) 1323# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12) 1324# define R300_BLEND_GL_ZERO (32) 1325# define R300_BLEND_GL_ONE (33) 1326# define R300_BLEND_GL_SRC_COLOR (34) 1327# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35) 1328# define R300_BLEND_GL_DST_COLOR (36) 1329# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37) 1330# define R300_BLEND_GL_SRC_ALPHA (38) 1331# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) 1332# define R300_BLEND_GL_DST_ALPHA (40) 1333# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41) 1334# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42) 1335# define R300_BLEND_GL_CONST_COLOR (43) 1336# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44) 1337# define R300_BLEND_GL_CONST_ALPHA (45) 1338# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) 1339# define R300_BLEND_MASK (63) 1340# define R300_SRC_BLEND_SHIFT (16) 1341# define R300_DST_BLEND_SHIFT (24) 1342#define R300_RB3D_BLEND_COLOR 0x4E10 1343#define R300_RB3D_COLORMASK 0x4E0C 1344# define R300_COLORMASK0_B (1<<0) 1345# define R300_COLORMASK0_G (1<<1) 1346# define R300_COLORMASK0_R (1<<2) 1347# define R300_COLORMASK0_A (1<<3) 1348 1349/* gap */ 1350 1351#define R300_RB3D_COLOROFFSET0 0x4E28 1352# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ 1353#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ 1354#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ 1355#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ 1356 1357/* gap */ 1358 1359/* Bit 16: Larger tiles 1360 * Bit 17: 4x2 tiles 1361 * Bit 18: Extremely weird tile like, but some pixels duplicated? 1362 */ 1363#define R300_RB3D_COLORPITCH0 0x4E38 1364# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ 1365# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ 1366# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1367# define R300_COLOR_MICROTILE_SQUARE_ENABLE (2 << 17) 1368# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1369# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1370# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1371# define R300_COLOR_FORMAT_RGB565 (2 << 22) 1372# define R300_COLOR_FORMAT_ARGB8888 (3 << 22) 1373#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ 1374#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ 1375#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ 1376 1377#define R300_RB3D_AARESOLVE_OFFSET 0x4E80 1378#define R300_RB3D_AARESOLVE_PITCH 0x4E84 1379#define R300_RB3D_AARESOLVE_CTL 0x4E88 1380/* gap */ 1381 1382/* Guess by Vladimir. 1383 * Set to 0A before 3D operations, set to 02 afterwards. 1384 */ 1385/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/ 1386# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 1387# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A 1388 1389/* gap */ 1390/* There seems to be no "write only" setting, so use Z-test = ALWAYS 1391 * for this. 1392 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 1393 */ 1394#define R300_ZB_CNTL 0x4F00 1395# define R300_STENCIL_ENABLE (1 << 0) 1396# define R300_Z_ENABLE (1 << 1) 1397# define R300_Z_WRITE_ENABLE (1 << 2) 1398# define R300_Z_SIGNED_COMPARE (1 << 3) 1399# define R300_STENCIL_FRONT_BACK (1 << 4) 1400 1401#define R300_ZB_ZSTENCILCNTL 0x4f04 1402 /* functions */ 1403# define R300_ZS_NEVER 0 1404# define R300_ZS_LESS 1 1405# define R300_ZS_LEQUAL 2 1406# define R300_ZS_EQUAL 3 1407# define R300_ZS_GEQUAL 4 1408# define R300_ZS_GREATER 5 1409# define R300_ZS_NOTEQUAL 6 1410# define R300_ZS_ALWAYS 7 1411# define R300_ZS_MASK 7 1412 /* operations */ 1413# define R300_ZS_KEEP 0 1414# define R300_ZS_ZERO 1 1415# define R300_ZS_REPLACE 2 1416# define R300_ZS_INCR 3 1417# define R300_ZS_DECR 4 1418# define R300_ZS_INVERT 5 1419# define R300_ZS_INCR_WRAP 6 1420# define R300_ZS_DECR_WRAP 7 1421# define R300_Z_FUNC_SHIFT 0 1422 /* front and back refer to operations done for front 1423 and back faces, i.e. separate stencil function support */ 1424# define R300_S_FRONT_FUNC_SHIFT 3 1425# define R300_S_FRONT_SFAIL_OP_SHIFT 6 1426# define R300_S_FRONT_ZPASS_OP_SHIFT 9 1427# define R300_S_FRONT_ZFAIL_OP_SHIFT 12 1428# define R300_S_BACK_FUNC_SHIFT 15 1429# define R300_S_BACK_SFAIL_OP_SHIFT 18 1430# define R300_S_BACK_ZPASS_OP_SHIFT 21 1431# define R300_S_BACK_ZFAIL_OP_SHIFT 24 1432 1433#define R300_ZB_STENCILREFMASK 0x4f08 1434# define R300_STENCILREF_SHIFT 0 1435# define R300_STENCILREF_MASK 0x000000ff 1436# define R300_STENCILMASK_SHIFT 8 1437# define R300_STENCILMASK_MASK 0x0000ff00 1438# define R300_STENCILWRITEMASK_SHIFT 16 1439# define R300_STENCILWRITEMASK_MASK 0x00ff0000 1440 1441/* gap */ 1442 1443#define R300_ZB_FORMAT 0x4f10 1444# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) 1445# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) 1446# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) 1447/* reserved up to (15 << 0) */ 1448# define R300_INVERT_13E3_LEADING_ONES (0 << 4) 1449# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) 1450 1451#define R300_ZB_ZTOP 0x4F14 1452# define R300_ZTOP_DISABLE (0 << 0) 1453# define R300_ZTOP_ENABLE (1 << 0) 1454 1455/* gap */ 1456 1457#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 1458# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) 1459# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) 1460# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) 1461# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) 1462# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) 1463# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31) 1464 1465#define R300_ZB_BW_CNTL 0x4f1c 1466# define R300_HIZ_DISABLE (0 << 0) 1467# define R300_HIZ_ENABLE (1 << 0) 1468# define R300_HIZ_MIN (0 << 1) 1469# define R300_HIZ_MAX (1 << 1) 1470# define R300_FAST_FILL_DISABLE (0 << 2) 1471# define R300_FAST_FILL_ENABLE (1 << 2) 1472# define R300_RD_COMP_DISABLE (0 << 3) 1473# define R300_RD_COMP_ENABLE (1 << 3) 1474# define R300_WR_COMP_DISABLE (0 << 4) 1475# define R300_WR_COMP_ENABLE (1 << 4) 1476# define R300_ZB_CB_CLEAR_RMW (0 << 5) 1477# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) 1478# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) 1479# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) 1480 1481# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) 1482# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) 1483# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) 1484# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) 1485 1486# define R500_BMASK_ENABLE (0 << 10) 1487# define R500_BMASK_DISABLE (1 << 10) 1488# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) 1489# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) 1490# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) 1491# define R500_HIZ_FP_EXP_BITS_1 (1 << 12) 1492# define R500_HIZ_FP_EXP_BITS_2 (2 << 12) 1493# define R500_HIZ_FP_EXP_BITS_3 (3 << 12) 1494# define R500_HIZ_FP_EXP_BITS_4 (4 << 12) 1495# define R500_HIZ_FP_EXP_BITS_5 (5 << 12) 1496# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) 1497# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) 1498# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) 1499# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) 1500# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) 1501# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) 1502# define R500_PEQ_PACKING_DISABLE (0 << 18) 1503# define R500_PEQ_PACKING_ENABLE (1 << 18) 1504# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) 1505# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) 1506 1507 1508/* gap */ 1509 1510/* Z Buffer Address Offset. 1511 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. 1512 */ 1513#define R300_ZB_DEPTHOFFSET 0x4f20 1514 1515/* Z Buffer Pitch and Endian Control */ 1516#define R300_ZB_DEPTHPITCH 0x4f24 1517# define R300_DEPTHPITCH_MASK 0x00003FFC 1518# define R300_DEPTHMACROTILE_DISABLE (0 << 16) 1519# define R300_DEPTHMACROTILE_ENABLE (1 << 16) 1520# define R300_DEPTHMICROTILE_LINEAR (0 << 17) 1521# define R300_DEPTHMICROTILE_TILED (1 << 17) 1522# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) 1523# define R300_DEPTHENDIAN_NO_SWAP (0 << 18) 1524# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) 1525# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) 1526# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) 1527 1528/* Z Buffer Clear Value */ 1529#define R300_ZB_DEPTHCLEARVALUE 0x4f28 1530 1531#define R300_ZB_ZMASK_OFFSET 0x4f30 1532#define R300_ZB_ZMASK_PITCH 0x4f34 1533#define R300_ZB_ZMASK_WRINDEX 0x4f38 1534#define R300_ZB_ZMASK_DWORD 0x4f3c 1535#define R300_ZB_ZMASK_RDINDEX 0x4f40 1536 1537/* Hierarchical Z Memory Offset */ 1538#define R300_ZB_HIZ_OFFSET 0x4f44 1539 1540/* Hierarchical Z Write Index */ 1541#define R300_ZB_HIZ_WRINDEX 0x4f48 1542 1543/* Hierarchical Z Data */ 1544#define R300_ZB_HIZ_DWORD 0x4f4c 1545 1546/* Hierarchical Z Read Index */ 1547#define R300_ZB_HIZ_RDINDEX 0x4f50 1548 1549/* Hierarchical Z Pitch */ 1550#define R300_ZB_HIZ_PITCH 0x4f54 1551 1552/* Z Buffer Z Pass Counter Data */ 1553#define R300_ZB_ZPASS_DATA 0x4f58 1554 1555/* Z Buffer Z Pass Counter Address */ 1556#define R300_ZB_ZPASS_ADDR 0x4f5c 1557 1558/* Depth buffer X and Y coordinate offset */ 1559#define R300_ZB_DEPTHXY_OFFSET 0x4f60 1560# define R300_DEPTHX_OFFSET_SHIFT 1 1561# define R300_DEPTHX_OFFSET_MASK 0x000007FE 1562# define R300_DEPTHY_OFFSET_SHIFT 17 1563# define R300_DEPTHY_OFFSET_MASK 0x07FE0000 1564 1565/* Sets the fifo sizes */ 1566#define R500_ZB_FIFO_SIZE 0x4fd0 1567# define R500_OP_FIFO_SIZE_FULL (0 << 0) 1568# define R500_OP_FIFO_SIZE_HALF (1 << 0) 1569# define R500_OP_FIFO_SIZE_QUATER (2 << 0) 1570# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) 1571 1572/* Stencil Reference Value and Mask for backfacing quads */ 1573/* R300_ZB_STENCILREFMASK handles front face */ 1574#define R500_ZB_STENCILREFMASK_BF 0x4fd4 1575# define R500_STENCILREF_SHIFT 0 1576# define R500_STENCILREF_MASK 0x000000ff 1577# define R500_STENCILMASK_SHIFT 8 1578# define R500_STENCILMASK_MASK 0x0000ff00 1579# define R500_STENCILWRITEMASK_SHIFT 16 1580# define R500_STENCILWRITEMASK_MASK 0x00ff0000 1581 1582/* BEGIN: Vertex program instruction set */ 1583 1584/* Every instruction is four dwords long: 1585 * DWORD 0: output and opcode 1586 * DWORD 1: first argument 1587 * DWORD 2: second argument 1588 * DWORD 3: third argument 1589 * 1590 * Notes: 1591 * - ABS r, a is implemented as MAX r, a, -a 1592 * - MOV is implemented as ADD to zero 1593 * - XPD is implemented as MUL + MAD 1594 * - FLR is implemented as FRC + ADD 1595 * - apparently, fglrx tries to schedule instructions so that there is at 1596 * least one instruction between the write to a temporary and the first 1597 * read from said temporary; however, violations of this scheduling are 1598 * allowed 1599 * - register indices seem to be unrelated with OpenGL aliasing to 1600 * conventional state 1601 * - only one attribute and one parameter can be loaded at a time; however, 1602 * the same attribute/parameter can be used for more than one argument 1603 * - the second software argument for POW is the third hardware argument 1604 * (no idea why) 1605 * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 1606 * 1607 * There is some magic surrounding LIT: 1608 * The single argument is replicated across all three inputs, but swizzled: 1609 * First argument: xyzy 1610 * Second argument: xyzx 1611 * Third argument: xyzw 1612 * Whenever the result is used later in the fragment program, fglrx forces 1613 * x and w to be 1.0 in the input selection; I don't know whether this is 1614 * strictly necessary 1615 */ 1616#define R300_VPI_OUT_OP_DOT (1 << 0) 1617#define R300_VPI_OUT_OP_MUL (2 << 0) 1618#define R300_VPI_OUT_OP_ADD (3 << 0) 1619#define R300_VPI_OUT_OP_MAD (4 << 0) 1620#define R300_VPI_OUT_OP_DST (5 << 0) 1621#define R300_VPI_OUT_OP_FRC (6 << 0) 1622#define R300_VPI_OUT_OP_MAX (7 << 0) 1623#define R300_VPI_OUT_OP_MIN (8 << 0) 1624#define R300_VPI_OUT_OP_SGE (9 << 0) 1625#define R300_VPI_OUT_OP_SLT (10 << 0) 1626 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ 1627#define R300_VPI_OUT_OP_UNK12 (12 << 0) 1628#define R300_VPI_OUT_OP_ARL (13 << 0) 1629#define R300_VPI_OUT_OP_EXP (65 << 0) 1630#define R300_VPI_OUT_OP_LOG (66 << 0) 1631 /* Used in fog computations, scalar(scalar) */ 1632#define R300_VPI_OUT_OP_UNK67 (67 << 0) 1633#define R300_VPI_OUT_OP_LIT (68 << 0) 1634#define R300_VPI_OUT_OP_POW (69 << 0) 1635#define R300_VPI_OUT_OP_RCP (70 << 0) 1636#define R300_VPI_OUT_OP_RSQ (72 << 0) 1637 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ 1638#define R300_VPI_OUT_OP_UNK73 (73 << 0) 1639#define R300_VPI_OUT_OP_EX2 (75 << 0) 1640#define R300_VPI_OUT_OP_LG2 (76 << 0) 1641#define R300_VPI_OUT_OP_MAD_2 (128 << 0) 1642 /* all temps, vector(scalar, vector, vector) */ 1643#define R300_VPI_OUT_OP_UNK129 (129 << 0) 1644 1645#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) 1646#define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8) 1647#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) 1648#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) 1649 1650#define R300_VPI_OUT_REG_INDEX_SHIFT 13 1651 /* GUESS based on fglrx native limits */ 1652#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) 1653 1654#define R300_VPI_OUT_WRITE_X (1 << 20) 1655#define R300_VPI_OUT_WRITE_Y (1 << 21) 1656#define R300_VPI_OUT_WRITE_Z (1 << 22) 1657#define R300_VPI_OUT_WRITE_W (1 << 23) 1658 1659#define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) 1660#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) 1661#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) 1662#define R300_VPI_IN_REG_CLASS_NONE (9 << 0) 1663#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) 1664 1665#define R300_VPI_IN_REG_INDEX_SHIFT 5 1666 /* GUESS based on fglrx native limits */ 1667#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) 1668 1669/* The R300 can select components from the input register arbitrarily. 1670 * Use the following constants, shifted by the component shift you 1671 * want to select 1672 */ 1673#define R300_VPI_IN_SELECT_X 0 1674#define R300_VPI_IN_SELECT_Y 1 1675#define R300_VPI_IN_SELECT_Z 2 1676#define R300_VPI_IN_SELECT_W 3 1677#define R300_VPI_IN_SELECT_ZERO 4 1678#define R300_VPI_IN_SELECT_ONE 5 1679#define R300_VPI_IN_SELECT_MASK 7 1680 1681#define R300_VPI_IN_X_SHIFT 13 1682#define R300_VPI_IN_Y_SHIFT 16 1683#define R300_VPI_IN_Z_SHIFT 19 1684#define R300_VPI_IN_W_SHIFT 22 1685 1686#define R300_VPI_IN_NEG_X (1 << 25) 1687#define R300_VPI_IN_NEG_Y (1 << 26) 1688#define R300_VPI_IN_NEG_Z (1 << 27) 1689#define R300_VPI_IN_NEG_W (1 << 28) 1690/* END: Vertex program instruction set */ 1691 1692/* BEGIN: Packet 3 commands */ 1693 1694/* A primitive emission dword. */ 1695#define R300_PRIM_TYPE_NONE (0 << 0) 1696#define R300_PRIM_TYPE_POINT (1 << 0) 1697#define R300_PRIM_TYPE_LINE (2 << 0) 1698#define R300_PRIM_TYPE_LINE_STRIP (3 << 0) 1699#define R300_PRIM_TYPE_TRI_LIST (4 << 0) 1700#define R300_PRIM_TYPE_TRI_FAN (5 << 0) 1701#define R300_PRIM_TYPE_TRI_STRIP (6 << 0) 1702#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1703#define R300_PRIM_TYPE_RECT_LIST (8 << 0) 1704#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1705#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1706 /* GUESS (based on r200) */ 1707#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) 1708#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) 1709#define R300_PRIM_TYPE_QUADS (13 << 0) 1710#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) 1711#define R300_PRIM_TYPE_POLYGON (15 << 0) 1712#define R300_PRIM_TYPE_MASK 0xF 1713#define R300_PRIM_WALK_IND (1 << 4) 1714#define R300_PRIM_WALK_LIST (2 << 4) 1715#define R300_PRIM_WALK_RING (3 << 4) 1716#define R300_PRIM_WALK_MASK (3 << 4) 1717 /* GUESS (based on r200) */ 1718#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) 1719#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) 1720#define R300_PRIM_NUM_VERTICES_SHIFT 16 1721#define R300_PRIM_NUM_VERTICES_MASK 0xffff 1722 1723/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. 1724 * Two parameter dwords: 1725 * 0. The first parameter appears to be always 0 1726 * 1. The second parameter is a standard primitive emission dword. 1727 */ 1728#define R300_PACKET3_3D_DRAW_VBUF 0x00002800 1729 1730/* Specify the full set of vertex arrays as (address, stride). 1731 * The first parameter is the number of vertex arrays specified. 1732 * The rest of the command is a variable length list of blocks, where 1733 * each block is three dwords long and specifies two arrays. 1734 * The first dword of a block is split into two words, the lower significant 1735 * word refers to the first array, the more significant word to the second 1736 * array in the block. 1737 * The low byte of each word contains the size of an array entry in dwords, 1738 * the high byte contains the stride of the array. 1739 * The second dword of a block contains the pointer to the first array, 1740 * the third dword of a block contains the pointer to the second array. 1741 * Note that if the total number of arrays is odd, the third dword of 1742 * the last block is omitted. 1743 */ 1744#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 1745 1746#define R300_PACKET3_INDX_BUFFER 0x00003300 1747# define R300_EB_UNK1_SHIFT 24 1748# define R300_EB_UNK1 (0x80<<24) 1749# define R300_EB_UNK2 0x0810 1750#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 1751#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 1752 1753/* END: Packet 3 commands */ 1754 1755 1756/* Color formats for 2d packets 1757 */ 1758#define R300_CP_COLOR_FORMAT_CI8 2 1759#define R300_CP_COLOR_FORMAT_ARGB1555 3 1760#define R300_CP_COLOR_FORMAT_RGB565 4 1761#define R300_CP_COLOR_FORMAT_ARGB8888 6 1762#define R300_CP_COLOR_FORMAT_RGB332 7 1763#define R300_CP_COLOR_FORMAT_RGB8 9 1764#define R300_CP_COLOR_FORMAT_ARGB4444 15 1765 1766/* 1767 * CP type-3 packets 1768 */ 1769#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 1770 1771#define R500_VAP_INDEX_OFFSET 0x208c 1772 1773#define R500_GA_US_VECTOR_INDEX 0x4250 1774#define R500_GA_US_VECTOR_DATA 0x4254 1775 1776#define R500_RS_IP_0 0x4074 1777#define R500_RS_INST_0 0x4320 1778 1779#define R500_US_CONFIG 0x4600 1780 1781#define R500_US_FC_CTRL 0x4624 1782#define R500_US_CODE_ADDR 0x4630 1783 1784#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 1785#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 1786 1787#define R300_SU_REG_DEST 0x42c8 1788#define RV530_FG_ZBREG_DEST 0x4be8 1789#define R300_ZB_ZPASS_DATA 0x4f58 1790#define R300_ZB_ZPASS_ADDR 0x4f5c 1791 1792#endif /* _R300_REG_H */ 1793