rv770d.h revision 261455
1/* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27#ifndef RV770_H 28#define RV770_H 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/rv770d.h 261455 2014-02-04 03:36:42Z eadler $"); 32 33#define R7XX_MAX_SH_GPRS 256 34#define R7XX_MAX_TEMP_GPRS 16 35#define R7XX_MAX_SH_THREADS 256 36#define R7XX_MAX_SH_STACK_ENTRIES 4096 37#define R7XX_MAX_BACKENDS 8 38#define R7XX_MAX_BACKENDS_MASK 0xff 39#define R7XX_MAX_SIMDS 16 40#define R7XX_MAX_SIMDS_MASK 0xffff 41#define R7XX_MAX_PIPES 8 42#define R7XX_MAX_PIPES_MASK 0xff 43 44/* Registers */ 45#define CB_COLOR0_BASE 0x28040 46#define CB_COLOR1_BASE 0x28044 47#define CB_COLOR2_BASE 0x28048 48#define CB_COLOR3_BASE 0x2804C 49#define CB_COLOR4_BASE 0x28050 50#define CB_COLOR5_BASE 0x28054 51#define CB_COLOR6_BASE 0x28058 52#define CB_COLOR7_BASE 0x2805C 53#define CB_COLOR7_FRAG 0x280FC 54 55#define CC_GC_SHADER_PIPE_CONFIG 0x8950 56#define CC_RB_BACKEND_DISABLE 0x98F4 57#define BACKEND_DISABLE(x) ((x) << 16) 58#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 59 60#define CGTS_SYS_TCC_DISABLE 0x3F90 61#define CGTS_TCC_DISABLE 0x9148 62#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 63#define CGTS_USER_TCC_DISABLE 0x914C 64 65#define CONFIG_MEMSIZE 0x5428 66 67#define CP_ME_CNTL 0x86D8 68#define CP_ME_HALT (1<<28) 69#define CP_PFP_HALT (1<<26) 70#define CP_ME_RAM_DATA 0xC160 71#define CP_ME_RAM_RADDR 0xC158 72#define CP_ME_RAM_WADDR 0xC15C 73#define CP_MEQ_THRESHOLDS 0x8764 74#define STQ_SPLIT(x) ((x) << 0) 75#define CP_PERFMON_CNTL 0x87FC 76#define CP_PFP_UCODE_ADDR 0xC150 77#define CP_PFP_UCODE_DATA 0xC154 78#define CP_QUEUE_THRESHOLDS 0x8760 79#define ROQ_IB1_START(x) ((x) << 0) 80#define ROQ_IB2_START(x) ((x) << 8) 81#define CP_RB_CNTL 0xC104 82#define RB_BUFSZ(x) ((x) << 0) 83#define RB_BLKSZ(x) ((x) << 8) 84#define RB_NO_UPDATE (1 << 27) 85#define RB_RPTR_WR_ENA (1U << 31) 86#define BUF_SWAP_32BIT (2 << 16) 87#define CP_RB_RPTR 0x8700 88#define CP_RB_RPTR_ADDR 0xC10C 89#define CP_RB_RPTR_ADDR_HI 0xC110 90#define CP_RB_RPTR_WR 0xC108 91#define CP_RB_WPTR 0xC114 92#define CP_RB_WPTR_ADDR 0xC118 93#define CP_RB_WPTR_ADDR_HI 0xC11C 94#define CP_RB_WPTR_DELAY 0x8704 95#define CP_SEM_WAIT_TIMER 0x85BC 96 97#define DB_DEBUG3 0x98B0 98#define DB_CLK_OFF_DELAY(x) ((x) << 11) 99#define DB_DEBUG4 0x9B8C 100#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 101 102#define DCP_TILING_CONFIG 0x6CA0 103#define PIPE_TILING(x) ((x) << 1) 104#define BANK_TILING(x) ((x) << 4) 105#define GROUP_SIZE(x) ((x) << 6) 106#define ROW_TILING(x) ((x) << 8) 107#define BANK_SWAPS(x) ((x) << 11) 108#define SAMPLE_SPLIT(x) ((x) << 14) 109#define BACKEND_MAP(x) ((x) << 16) 110 111#define GB_TILING_CONFIG 0x98F0 112#define PIPE_TILING__SHIFT 1 113#define PIPE_TILING__MASK 0x0000000e 114 115#define DMA_TILING_CONFIG 0x3ec8 116#define DMA_TILING_CONFIG2 0xd0b8 117 118#define GC_USER_SHADER_PIPE_CONFIG 0x8954 119#define INACTIVE_QD_PIPES(x) ((x) << 8) 120#define INACTIVE_QD_PIPES_MASK 0x0000FF00 121#define INACTIVE_QD_PIPES_SHIFT 8 122#define INACTIVE_SIMDS(x) ((x) << 16) 123#define INACTIVE_SIMDS_MASK 0x00FF0000 124 125#define GRBM_CNTL 0x8000 126#define GRBM_READ_TIMEOUT(x) ((x) << 0) 127#define GRBM_SOFT_RESET 0x8020 128#define SOFT_RESET_CP (1<<0) 129#define GRBM_STATUS 0x8010 130#define CMDFIFO_AVAIL_MASK 0x0000000F 131#define GUI_ACTIVE (1<<31) 132#define GRBM_STATUS2 0x8014 133 134#define CG_MULT_THERMAL_STATUS 0x740 135#define ASIC_T(x) ((x) << 16) 136#define ASIC_T_MASK 0x3FF0000 137#define ASIC_T_SHIFT 16 138 139#define HDP_HOST_PATH_CNTL 0x2C00 140#define HDP_NONSURFACE_BASE 0x2C04 141#define HDP_NONSURFACE_INFO 0x2C08 142#define HDP_NONSURFACE_SIZE 0x2C0C 143#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 144#define HDP_TILING_CONFIG 0x2F3C 145#define HDP_DEBUG1 0x2F34 146 147#define MC_SHARED_CHMAP 0x2004 148#define NOOFCHAN_SHIFT 12 149#define NOOFCHAN_MASK 0x00003000 150#define MC_SHARED_CHREMAP 0x2008 151 152#define MC_ARB_RAMCFG 0x2760 153#define NOOFBANK_SHIFT 0 154#define NOOFBANK_MASK 0x00000003 155#define NOOFRANK_SHIFT 2 156#define NOOFRANK_MASK 0x00000004 157#define NOOFROWS_SHIFT 3 158#define NOOFROWS_MASK 0x00000038 159#define NOOFCOLS_SHIFT 6 160#define NOOFCOLS_MASK 0x000000C0 161#define CHANSIZE_SHIFT 8 162#define CHANSIZE_MASK 0x00000100 163#define BURSTLENGTH_SHIFT 9 164#define BURSTLENGTH_MASK 0x00000200 165#define CHANSIZE_OVERRIDE (1 << 11) 166#define MC_VM_AGP_TOP 0x2028 167#define MC_VM_AGP_BOT 0x202C 168#define MC_VM_AGP_BASE 0x2030 169#define MC_VM_FB_LOCATION 0x2024 170#define MC_VM_MB_L1_TLB0_CNTL 0x2234 171#define MC_VM_MB_L1_TLB1_CNTL 0x2238 172#define MC_VM_MB_L1_TLB2_CNTL 0x223C 173#define MC_VM_MB_L1_TLB3_CNTL 0x2240 174#define ENABLE_L1_TLB (1 << 0) 175#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 176#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 177#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 178#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 179#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 180#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 181#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 182#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 183#define MC_VM_MD_L1_TLB0_CNTL 0x2654 184#define MC_VM_MD_L1_TLB1_CNTL 0x2658 185#define MC_VM_MD_L1_TLB2_CNTL 0x265C 186#define MC_VM_MD_L1_TLB3_CNTL 0x2698 187#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 188#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 189#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 190 191#define PA_CL_ENHANCE 0x8A14 192#define CLIP_VTX_REORDER_ENA (1 << 0) 193#define NUM_CLIP_SEQ(x) ((x) << 1) 194#define PA_SC_AA_CONFIG 0x28C04 195#define PA_SC_CLIPRECT_RULE 0x2820C 196#define PA_SC_EDGERULE 0x28230 197#define PA_SC_FIFO_SIZE 0x8BCC 198#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 199#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 200#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 201#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 202#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 203#define PA_SC_LINE_STIPPLE 0x28A0C 204#define PA_SC_LINE_STIPPLE_STATE 0x8B10 205#define PA_SC_MODE_CNTL 0x28A4C 206#define PA_SC_MULTI_CHIP_CNTL 0x8B20 207#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 208 209#define SCRATCH_REG0 0x8500 210#define SCRATCH_REG1 0x8504 211#define SCRATCH_REG2 0x8508 212#define SCRATCH_REG3 0x850C 213#define SCRATCH_REG4 0x8510 214#define SCRATCH_REG5 0x8514 215#define SCRATCH_REG6 0x8518 216#define SCRATCH_REG7 0x851C 217#define SCRATCH_UMSK 0x8540 218#define SCRATCH_ADDR 0x8544 219 220#define SMX_SAR_CTL0 0xA008 221#define SMX_DC_CTL0 0xA020 222#define USE_HASH_FUNCTION (1 << 0) 223#define CACHE_DEPTH(x) ((x) << 1) 224#define FLUSH_ALL_ON_EVENT (1 << 10) 225#define STALL_ON_EVENT (1 << 11) 226#define SMX_EVENT_CTL 0xA02C 227#define ES_FLUSH_CTL(x) ((x) << 0) 228#define GS_FLUSH_CTL(x) ((x) << 3) 229#define ACK_FLUSH_CTL(x) ((x) << 6) 230#define SYNC_FLUSH_CTL (1 << 8) 231 232#define SPI_CONFIG_CNTL 0x9100 233#define GPR_WRITE_PRIORITY(x) ((x) << 0) 234#define DISABLE_INTERP_1 (1 << 5) 235#define SPI_CONFIG_CNTL_1 0x913C 236#define VTX_DONE_DELAY(x) ((x) << 0) 237#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 238#define SPI_INPUT_Z 0x286D8 239#define SPI_PS_IN_CONTROL_0 0x286CC 240#define NUM_INTERP(x) ((x)<<0) 241#define POSITION_ENA (1<<8) 242#define POSITION_CENTROID (1<<9) 243#define POSITION_ADDR(x) ((x)<<10) 244#define PARAM_GEN(x) ((x)<<15) 245#define PARAM_GEN_ADDR(x) ((x)<<19) 246#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 247#define PERSP_GRADIENT_ENA (1<<28) 248#define LINEAR_GRADIENT_ENA (1<<29) 249#define POSITION_SAMPLE (1<<30) 250#define BARYC_AT_SAMPLE_ENA (1<<31) 251 252#define SQ_CONFIG 0x8C00 253#define VC_ENABLE (1 << 0) 254#define EXPORT_SRC_C (1 << 1) 255#define DX9_CONSTS (1 << 2) 256#define ALU_INST_PREFER_VECTOR (1 << 3) 257#define DX10_CLAMP (1 << 4) 258#define CLAUSE_SEQ_PRIO(x) ((x) << 8) 259#define PS_PRIO(x) ((x) << 24) 260#define VS_PRIO(x) ((x) << 26) 261#define GS_PRIO(x) ((x) << 28) 262#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 263#define SIMDA_RING0(x) ((x)<<0) 264#define SIMDA_RING1(x) ((x)<<8) 265#define SIMDB_RING0(x) ((x)<<16) 266#define SIMDB_RING1(x) ((x)<<24) 267#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 268#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 269#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 270#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 271#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 272#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 273#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 274#define ES_PRIO(x) ((x) << 30) 275#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 276#define NUM_PS_GPRS(x) ((x) << 0) 277#define NUM_VS_GPRS(x) ((x) << 16) 278#define DYN_GPR_ENABLE (1 << 27) 279#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 280#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 281#define NUM_GS_GPRS(x) ((x) << 0) 282#define NUM_ES_GPRS(x) ((x) << 16) 283#define SQ_MS_FIFO_SIZES 0x8CF0 284#define CACHE_FIFO_SIZE(x) ((x) << 0) 285#define FETCH_FIFO_HIWATER(x) ((x) << 8) 286#define DONE_FIFO_HIWATER(x) ((x) << 16) 287#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 288#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 289#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 290#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 291#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 292#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 293#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 294#define SQ_THREAD_RESOURCE_MGMT 0x8C0C 295#define NUM_PS_THREADS(x) ((x) << 0) 296#define NUM_VS_THREADS(x) ((x) << 8) 297#define NUM_GS_THREADS(x) ((x) << 16) 298#define NUM_ES_THREADS(x) ((x) << 24) 299 300#define SX_DEBUG_1 0x9058 301#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 302#define SX_EXPORT_BUFFER_SIZES 0x900C 303#define COLOR_BUFFER_SIZE(x) ((x) << 0) 304#define POSITION_BUFFER_SIZE(x) ((x) << 8) 305#define SMX_BUFFER_SIZE(x) ((x) << 16) 306#define SX_MISC 0x28350 307 308#define TA_CNTL_AUX 0x9508 309#define DISABLE_CUBE_WRAP (1 << 0) 310#define DISABLE_CUBE_ANISO (1 << 1) 311#define SYNC_GRADIENT (1 << 24) 312#define SYNC_WALKER (1 << 25) 313#define SYNC_ALIGNER (1 << 26) 314#define BILINEAR_PRECISION_6_BIT (0 << 31) 315#define BILINEAR_PRECISION_8_BIT (1U << 31) 316 317#define TCP_CNTL 0x9610 318#define TCP_CHAN_STEER 0x9614 319 320#define VC_ENHANCE 0x9714 321 322#define VGT_CACHE_INVALIDATION 0x88C4 323#define CACHE_INVALIDATION(x) ((x)<<0) 324#define VC_ONLY 0 325#define TC_ONLY 1 326#define VC_AND_TC 2 327#define AUTO_INVLD_EN(x) ((x) << 6) 328#define NO_AUTO 0 329#define ES_AUTO 1 330#define GS_AUTO 2 331#define ES_AND_GS_AUTO 3 332#define VGT_ES_PER_GS 0x88CC 333#define VGT_GS_PER_ES 0x88C8 334#define VGT_GS_PER_VS 0x88E8 335#define VGT_GS_VERTEX_REUSE 0x88D4 336#define VGT_NUM_INSTANCES 0x8974 337#define VGT_OUT_DEALLOC_CNTL 0x28C5C 338#define DEALLOC_DIST_MASK 0x0000007F 339#define VGT_STRMOUT_EN 0x28AB0 340#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 341#define VTX_REUSE_DEPTH_MASK 0x000000FF 342 343#define VM_CONTEXT0_CNTL 0x1410 344#define ENABLE_CONTEXT (1 << 0) 345#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 346#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 347#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 348#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 349#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 350#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 351#define VM_L2_CNTL 0x1400 352#define ENABLE_L2_CACHE (1 << 0) 353#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 354#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 355#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 356#define VM_L2_CNTL2 0x1404 357#define INVALIDATE_ALL_L1_TLBS (1 << 0) 358#define INVALIDATE_L2_CACHE (1 << 1) 359#define VM_L2_CNTL3 0x1408 360#define BANK_SELECT(x) ((x) << 0) 361#define CACHE_UPDATE_MODE(x) ((x) << 6) 362#define VM_L2_STATUS 0x140C 363#define L2_BUSY (1 << 0) 364 365#define WAIT_UNTIL 0x8040 366 367/* async DMA */ 368#define DMA_RB_RPTR 0xd008 369#define DMA_RB_WPTR 0xd00c 370 371/* async DMA packets */ 372#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 373 (((t) & 0x1) << 23) | \ 374 (((s) & 0x1) << 22) | \ 375 (((n) & 0xFFFF) << 0)) 376/* async DMA Packet types */ 377#define DMA_PACKET_WRITE 0x2 378#define DMA_PACKET_COPY 0x3 379#define DMA_PACKET_INDIRECT_BUFFER 0x4 380#define DMA_PACKET_SEMAPHORE 0x5 381#define DMA_PACKET_FENCE 0x6 382#define DMA_PACKET_TRAP 0x7 383#define DMA_PACKET_CONSTANT_FILL 0xd 384#define DMA_PACKET_NOP 0xf 385 386 387#define SRBM_STATUS 0x0E50 388 389/* DCE 3.2 HDMI */ 390#define HDMI_CONTROL 0x7400 391# define HDMI_KEEPOUT_MODE (1 << 0) 392# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 393# define HDMI_ERROR_ACK (1 << 8) 394# define HDMI_ERROR_MASK (1 << 9) 395#define HDMI_STATUS 0x7404 396# define HDMI_ACTIVE_AVMUTE (1 << 0) 397# define HDMI_AUDIO_PACKET_ERROR (1 << 16) 398# define HDMI_VBI_PACKET_ERROR (1 << 20) 399#define HDMI_AUDIO_PACKET_CONTROL 0x7408 400# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 401# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 402#define HDMI_ACR_PACKET_CONTROL 0x740c 403# define HDMI_ACR_SEND (1 << 0) 404# define HDMI_ACR_CONT (1 << 1) 405# define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 406# define HDMI_ACR_HW 0 407# define HDMI_ACR_32 1 408# define HDMI_ACR_44 2 409# define HDMI_ACR_48 3 410# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 411# define HDMI_ACR_AUTO_SEND (1 << 12) 412#define HDMI_VBI_PACKET_CONTROL 0x7410 413# define HDMI_NULL_SEND (1 << 0) 414# define HDMI_GC_SEND (1 << 4) 415# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 416#define HDMI_INFOFRAME_CONTROL0 0x7414 417# define HDMI_AVI_INFO_SEND (1 << 0) 418# define HDMI_AVI_INFO_CONT (1 << 1) 419# define HDMI_AUDIO_INFO_SEND (1 << 4) 420# define HDMI_AUDIO_INFO_CONT (1 << 5) 421# define HDMI_MPEG_INFO_SEND (1 << 8) 422# define HDMI_MPEG_INFO_CONT (1 << 9) 423#define HDMI_INFOFRAME_CONTROL1 0x7418 424# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 425# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 426# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 427#define HDMI_GENERIC_PACKET_CONTROL 0x741c 428# define HDMI_GENERIC0_SEND (1 << 0) 429# define HDMI_GENERIC0_CONT (1 << 1) 430# define HDMI_GENERIC1_SEND (1 << 4) 431# define HDMI_GENERIC1_CONT (1 << 5) 432# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 433# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 434#define HDMI_GC 0x7428 435# define HDMI_GC_AVMUTE (1 << 0) 436#define AFMT_AUDIO_PACKET_CONTROL2 0x742c 437# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 438# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 439# define AFMT_60958_CS_SOURCE (1 << 4) 440# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 441# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 442#define AFMT_AVI_INFO0 0x7454 443# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 444# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 445# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 446# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 447# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 448# define AFMT_AVI_INFO_Y_RGB 0 449# define AFMT_AVI_INFO_Y_YCBCR422 1 450# define AFMT_AVI_INFO_Y_YCBCR444 2 451# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 452# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 453# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 454# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 455# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 456# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 457# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 458# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 459# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 460# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 461#define AFMT_AVI_INFO1 0x7458 462# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 463# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 464# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 465#define AFMT_AVI_INFO2 0x745c 466# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 467# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 468#define AFMT_AVI_INFO3 0x7460 469# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 470# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 471#define AFMT_MPEG_INFO0 0x7464 472# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 473# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 474# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 475# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 476#define AFMT_MPEG_INFO1 0x7468 477# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 478# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 479# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 480#define AFMT_GENERIC0_HDR 0x746c 481#define AFMT_GENERIC0_0 0x7470 482#define AFMT_GENERIC0_1 0x7474 483#define AFMT_GENERIC0_2 0x7478 484#define AFMT_GENERIC0_3 0x747c 485#define AFMT_GENERIC0_4 0x7480 486#define AFMT_GENERIC0_5 0x7484 487#define AFMT_GENERIC0_6 0x7488 488#define AFMT_GENERIC1_HDR 0x748c 489#define AFMT_GENERIC1_0 0x7490 490#define AFMT_GENERIC1_1 0x7494 491#define AFMT_GENERIC1_2 0x7498 492#define AFMT_GENERIC1_3 0x749c 493#define AFMT_GENERIC1_4 0x74a0 494#define AFMT_GENERIC1_5 0x74a4 495#define AFMT_GENERIC1_6 0x74a8 496#define HDMI_ACR_32_0 0x74ac 497# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 498#define HDMI_ACR_32_1 0x74b0 499# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 500#define HDMI_ACR_44_0 0x74b4 501# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 502#define HDMI_ACR_44_1 0x74b8 503# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 504#define HDMI_ACR_48_0 0x74bc 505# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 506#define HDMI_ACR_48_1 0x74c0 507# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 508#define HDMI_ACR_STATUS_0 0x74c4 509#define HDMI_ACR_STATUS_1 0x74c8 510#define AFMT_AUDIO_INFO0 0x74cc 511# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 512# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 513# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 514#define AFMT_AUDIO_INFO1 0x74d0 515# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 516# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 517# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 518# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 519#define AFMT_60958_0 0x74d4 520# define AFMT_60958_CS_A(x) (((x) & 1) << 0) 521# define AFMT_60958_CS_B(x) (((x) & 1) << 1) 522# define AFMT_60958_CS_C(x) (((x) & 1) << 2) 523# define AFMT_60958_CS_D(x) (((x) & 3) << 3) 524# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 525# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 526# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 527# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 528# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 529# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 530#define AFMT_60958_1 0x74d8 531# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 532# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 533# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 534# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 535# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 536#define AFMT_AUDIO_CRC_CONTROL 0x74dc 537# define AFMT_AUDIO_CRC_EN (1 << 0) 538#define AFMT_RAMP_CONTROL0 0x74e0 539# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 540# define AFMT_RAMP_DATA_SIGN (1U << 31) 541#define AFMT_RAMP_CONTROL1 0x74e4 542# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 543# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 544#define AFMT_RAMP_CONTROL2 0x74e8 545# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 546#define AFMT_RAMP_CONTROL3 0x74ec 547# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 548#define AFMT_60958_2 0x74f0 549# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 550# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 551# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 552# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 553# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 554# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 555#define AFMT_STATUS 0x7600 556# define AFMT_AUDIO_ENABLE (1 << 4) 557# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 558# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 559# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 560#define AFMT_AUDIO_PACKET_CONTROL 0x7604 561# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 562# define AFMT_AUDIO_TEST_EN (1 << 12) 563# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 564# define AFMT_60958_CS_UPDATE (1 << 26) 565# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 566# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 567# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 568# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 569#define AFMT_VBI_PACKET_CONTROL 0x7608 570# define AFMT_GENERIC0_UPDATE (1 << 2) 571#define AFMT_INFOFRAME_CONTROL0 0x760c 572# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 573# define AFMT_AUDIO_INFO_UPDATE (1 << 7) 574# define AFMT_MPEG_INFO_UPDATE (1 << 10) 575#define AFMT_GENERIC0_7 0x7610 576/* second instance starts at 0x7800 */ 577#define HDMI_OFFSET0 (0x7400 - 0x7400) 578#define HDMI_OFFSET1 (0x7800 - 0x7400) 579 580/* DCE3.2 ELD audio interface */ 581#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ 582#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ 583#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ 584#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ 585#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ 586#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ 587#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ 588#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ 589#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ 590#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ 591#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ 592#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ 593#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ 594#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ 595# define MAX_CHANNELS(x) (((x) & 0x7) << 0) 596/* max channels minus one. 7 = 8 channels */ 597# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 598# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 599# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 600/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 601 * bit0 = 32 kHz 602 * bit1 = 44.1 kHz 603 * bit2 = 48 kHz 604 * bit3 = 88.2 kHz 605 * bit4 = 96 kHz 606 * bit5 = 176.4 kHz 607 * bit6 = 192 kHz 608 */ 609 610#define AZ_HOT_PLUG_CONTROL 0x7300 611# define AZ_FORCE_CODEC_WAKE (1 << 0) 612# define PIN0_JACK_DETECTION_ENABLE (1 << 4) 613# define PIN1_JACK_DETECTION_ENABLE (1 << 5) 614# define PIN2_JACK_DETECTION_ENABLE (1 << 6) 615# define PIN3_JACK_DETECTION_ENABLE (1 << 7) 616# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 617# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 618# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 619# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 620# define CODEC_HOT_PLUG_ENABLE (1 << 12) 621# define PIN0_AUDIO_ENABLED (1 << 24) 622# define PIN1_AUDIO_ENABLED (1 << 25) 623# define PIN2_AUDIO_ENABLED (1 << 26) 624# define PIN3_AUDIO_ENABLED (1 << 27) 625# define AUDIO_ENABLED (1U << 31) 626 627 628#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 629#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 630#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 631#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 632#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 633#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 634 635/* PCIE link stuff */ 636#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 637#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 638# define LC_LINK_WIDTH_SHIFT 0 639# define LC_LINK_WIDTH_MASK 0x7 640# define LC_LINK_WIDTH_X0 0 641# define LC_LINK_WIDTH_X1 1 642# define LC_LINK_WIDTH_X2 2 643# define LC_LINK_WIDTH_X4 3 644# define LC_LINK_WIDTH_X8 4 645# define LC_LINK_WIDTH_X16 6 646# define LC_LINK_WIDTH_RD_SHIFT 4 647# define LC_LINK_WIDTH_RD_MASK 0x70 648# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 649# define LC_RECONFIG_NOW (1 << 8) 650# define LC_RENEGOTIATION_SUPPORT (1 << 9) 651# define LC_RENEGOTIATE_EN (1 << 10) 652# define LC_SHORT_RECONFIG_EN (1 << 11) 653# define LC_UPCONFIGURE_SUPPORT (1 << 12) 654# define LC_UPCONFIGURE_DIS (1 << 13) 655#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 656# define LC_GEN2_EN_STRAP (1 << 0) 657# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 658# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 659# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 660# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 661# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 662# define LC_CURRENT_DATA_RATE (1 << 11) 663# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 664# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 665# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 666# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 667#define MM_CFGREGS_CNTL 0x544c 668# define MM_WR_TO_CFG_EN (1 << 3) 669#define LINK_CNTL2 0x88 /* F0 */ 670# define TARGET_LINK_SPEED_MASK (0xf << 0) 671# define SELECTABLE_DEEMPHASIS (1 << 6) 672 673#endif 674