cpufunc.h revision 266203
1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD: stable/10/sys/arm/include/cpufunc.h 266203 2014-05-16 00:14:50Z ian $ 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> 50#include <machine/cpuconf.h> 51#include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52 53static __inline void 54breakpoint(void) 55{ 56 __asm(".word 0xe7ffffff"); 57} 58 59struct cpu_functions { 60 61 /* CPU functions */ 62 63 u_int (*cf_id) (void); 64 void (*cf_cpwait) (void); 65 66 /* MMU functions */ 67 68 u_int (*cf_control) (u_int bic, u_int eor); 69 void (*cf_domains) (u_int domains); 70 void (*cf_setttb) (u_int ttb); 71 u_int (*cf_faultstatus) (void); 72 u_int (*cf_faultaddress) (void); 73 74 /* TLB functions */ 75 76 void (*cf_tlb_flushID) (void); 77 void (*cf_tlb_flushID_SE) (u_int va); 78 void (*cf_tlb_flushI) (void); 79 void (*cf_tlb_flushI_SE) (u_int va); 80 void (*cf_tlb_flushD) (void); 81 void (*cf_tlb_flushD_SE) (u_int va); 82 83 /* 84 * Cache operations: 85 * 86 * We define the following primitives: 87 * 88 * icache_sync_all Synchronize I-cache 89 * icache_sync_range Synchronize I-cache range 90 * 91 * dcache_wbinv_all Write-back and Invalidate D-cache 92 * dcache_wbinv_range Write-back and Invalidate D-cache range 93 * dcache_inv_range Invalidate D-cache range 94 * dcache_wb_range Write-back D-cache range 95 * 96 * idcache_wbinv_all Write-back and Invalidate D-cache, 97 * Invalidate I-cache 98 * idcache_wbinv_range Write-back and Invalidate D-cache, 99 * Invalidate I-cache range 100 * 101 * Note that the ARM term for "write-back" is "clean". We use 102 * the term "write-back" since it's a more common way to describe 103 * the operation. 104 * 105 * There are some rules that must be followed: 106 * 107 * ID-cache Invalidate All: 108 * Unlike other functions, this one must never write back. 109 * It is used to intialize the MMU when it is in an unknown 110 * state (such as when it may have lines tagged as valid 111 * that belong to a previous set of mappings). 112 * 113 * I-cache Synch (all or range): 114 * The goal is to synchronize the instruction stream, 115 * so you may beed to write-back dirty D-cache blocks 116 * first. If a range is requested, and you can't 117 * synchronize just a range, you have to hit the whole 118 * thing. 119 * 120 * D-cache Write-Back and Invalidate range: 121 * If you can't WB-Inv a range, you must WB-Inv the 122 * entire D-cache. 123 * 124 * D-cache Invalidate: 125 * If you can't Inv the D-cache, you must Write-Back 126 * and Invalidate. Code that uses this operation 127 * MUST NOT assume that the D-cache will not be written 128 * back to memory. 129 * 130 * D-cache Write-Back: 131 * If you can't Write-back without doing an Inv, 132 * that's fine. Then treat this as a WB-Inv. 133 * Skipping the invalidate is merely an optimization. 134 * 135 * All operations: 136 * Valid virtual addresses must be passed to each 137 * cache operation. 138 */ 139 void (*cf_icache_sync_all) (void); 140 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 141 142 void (*cf_dcache_wbinv_all) (void); 143 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 145 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 146 147 void (*cf_idcache_inv_all) (void); 148 void (*cf_idcache_wbinv_all) (void); 149 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 150 void (*cf_l2cache_wbinv_all) (void); 151 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 152 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 153 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 154 155 /* Other functions */ 156 157 void (*cf_flush_prefetchbuf) (void); 158 void (*cf_drain_writebuf) (void); 159 void (*cf_flush_brnchtgt_C) (void); 160 void (*cf_flush_brnchtgt_E) (u_int va); 161 162 void (*cf_sleep) (int mode); 163 164 /* Soft functions */ 165 166 int (*cf_dataabt_fixup) (void *arg); 167 int (*cf_prefetchabt_fixup) (void *arg); 168 169 void (*cf_context_switch) (void); 170 171 void (*cf_setup) (char *string); 172}; 173 174extern struct cpu_functions cpufuncs; 175extern u_int cputype; 176 177#define cpu_id() cpufuncs.cf_id() 178#define cpu_cpwait() cpufuncs.cf_cpwait() 179 180#define cpu_control(c, e) cpufuncs.cf_control(c, e) 181#define cpu_domains(d) cpufuncs.cf_domains(d) 182#define cpu_setttb(t) cpufuncs.cf_setttb(t) 183#define cpu_faultstatus() cpufuncs.cf_faultstatus() 184#define cpu_faultaddress() cpufuncs.cf_faultaddress() 185 186#ifndef SMP 187 188#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 189#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 190#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 191#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 192#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 193#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 194 195#else 196void tlb_broadcast(int); 197 198#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 199#define TLB_BROADCAST /* No need to explicitely send an IPI */ 200#else 201#define TLB_BROADCAST tlb_broadcast(7) 202#endif 203 204#define cpu_tlb_flushID() do { \ 205 cpufuncs.cf_tlb_flushID(); \ 206 TLB_BROADCAST; \ 207} while(0) 208 209#define cpu_tlb_flushID_SE(e) do { \ 210 cpufuncs.cf_tlb_flushID_SE(e); \ 211 TLB_BROADCAST; \ 212} while(0) 213 214 215#define cpu_tlb_flushI() do { \ 216 cpufuncs.cf_tlb_flushI(); \ 217 TLB_BROADCAST; \ 218} while(0) 219 220 221#define cpu_tlb_flushI_SE(e) do { \ 222 cpufuncs.cf_tlb_flushI_SE(e); \ 223 TLB_BROADCAST; \ 224} while(0) 225 226 227#define cpu_tlb_flushD() do { \ 228 cpufuncs.cf_tlb_flushD(); \ 229 TLB_BROADCAST; \ 230} while(0) 231 232 233#define cpu_tlb_flushD_SE(e) do { \ 234 cpufuncs.cf_tlb_flushD_SE(e); \ 235 TLB_BROADCAST; \ 236} while(0) 237 238#endif 239 240#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 241#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 242 243#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 244#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 245#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 246#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 247 248#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 249#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 250#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 251#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 252#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 253#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 254#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 255 256#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 257#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 258#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 259#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 260 261#define cpu_sleep(m) cpufuncs.cf_sleep(m) 262 263#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 264#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 265#define ABORT_FIXUP_OK 0 /* fixup succeeded */ 266#define ABORT_FIXUP_FAILED 1 /* fixup failed */ 267#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 268 269#define cpu_setup(a) cpufuncs.cf_setup(a) 270 271int set_cpufuncs (void); 272#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 273#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 274 275void cpufunc_nullop (void); 276int cpufunc_null_fixup (void *); 277int early_abort_fixup (void *); 278int late_abort_fixup (void *); 279u_int cpufunc_id (void); 280u_int cpufunc_cpuid (void); 281u_int cpufunc_control (u_int clear, u_int bic); 282void cpufunc_domains (u_int domains); 283u_int cpufunc_faultstatus (void); 284u_int cpufunc_faultaddress (void); 285u_int cpu_pfr (int); 286 287#ifdef CPU_ARM3 288u_int arm3_control (u_int clear, u_int bic); 289void arm3_cache_flush (void); 290#endif /* CPU_ARM3 */ 291 292#if defined(CPU_ARM6) || defined(CPU_ARM7) 293void arm67_setttb (u_int ttb); 294void arm67_tlb_flush (void); 295void arm67_tlb_purge (u_int va); 296void arm67_cache_flush (void); 297void arm67_context_switch (void); 298#endif /* CPU_ARM6 || CPU_ARM7 */ 299 300#ifdef CPU_ARM6 301void arm6_setup (char *string); 302#endif /* CPU_ARM6 */ 303 304#ifdef CPU_ARM7 305void arm7_setup (char *string); 306#endif /* CPU_ARM7 */ 307 308#ifdef CPU_ARM7TDMI 309int arm7_dataabt_fixup (void *arg); 310void arm7tdmi_setup (char *string); 311void arm7tdmi_setttb (u_int ttb); 312void arm7tdmi_tlb_flushID (void); 313void arm7tdmi_tlb_flushID_SE (u_int va); 314void arm7tdmi_cache_flushID (void); 315void arm7tdmi_context_switch (void); 316#endif /* CPU_ARM7TDMI */ 317 318#ifdef CPU_ARM8 319void arm8_setttb (u_int ttb); 320void arm8_tlb_flushID (void); 321void arm8_tlb_flushID_SE (u_int va); 322void arm8_cache_flushID (void); 323void arm8_cache_flushID_E (u_int entry); 324void arm8_cache_cleanID (void); 325void arm8_cache_cleanID_E (u_int entry); 326void arm8_cache_purgeID (void); 327void arm8_cache_purgeID_E (u_int entry); 328 329void arm8_cache_syncI (void); 330void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 331void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 332void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 333void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 334void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 335 336void arm8_context_switch (void); 337 338void arm8_setup (char *string); 339 340u_int arm8_clock_config (u_int, u_int); 341#endif 342 343 344#if defined(CPU_FA526) || defined(CPU_FA626TE) 345void fa526_setup (char *arg); 346void fa526_setttb (u_int ttb); 347void fa526_context_switch (void); 348void fa526_cpu_sleep (int); 349void fa526_tlb_flushI_SE (u_int); 350void fa526_tlb_flushID_SE (u_int); 351void fa526_flush_prefetchbuf (void); 352void fa526_flush_brnchtgt_E (u_int); 353 354void fa526_icache_sync_all (void); 355void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 356void fa526_dcache_wbinv_all (void); 357void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 358void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 359void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 360void fa526_idcache_wbinv_all(void); 361void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 362#endif 363 364 365#ifdef CPU_SA110 366void sa110_setup (char *string); 367void sa110_context_switch (void); 368#endif /* CPU_SA110 */ 369 370#if defined(CPU_SA1100) || defined(CPU_SA1110) 371void sa11x0_drain_readbuf (void); 372 373void sa11x0_context_switch (void); 374void sa11x0_cpu_sleep (int mode); 375 376void sa11x0_setup (char *string); 377#endif 378 379#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 380void sa1_setttb (u_int ttb); 381 382void sa1_tlb_flushID_SE (u_int va); 383 384void sa1_cache_flushID (void); 385void sa1_cache_flushI (void); 386void sa1_cache_flushD (void); 387void sa1_cache_flushD_SE (u_int entry); 388 389void sa1_cache_cleanID (void); 390void sa1_cache_cleanD (void); 391void sa1_cache_cleanD_E (u_int entry); 392 393void sa1_cache_purgeID (void); 394void sa1_cache_purgeID_E (u_int entry); 395void sa1_cache_purgeD (void); 396void sa1_cache_purgeD_E (u_int entry); 397 398void sa1_cache_syncI (void); 399void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 400void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 401void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 402void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 403void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 404 405#endif 406 407#ifdef CPU_ARM9 408void arm9_setttb (u_int); 409 410void arm9_tlb_flushID_SE (u_int va); 411 412void arm9_icache_sync_all (void); 413void arm9_icache_sync_range (vm_offset_t, vm_size_t); 414 415void arm9_dcache_wbinv_all (void); 416void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 417void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 418void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 419 420void arm9_idcache_wbinv_all (void); 421void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 422 423void arm9_context_switch (void); 424 425void arm9_setup (char *string); 426 427extern unsigned arm9_dcache_sets_max; 428extern unsigned arm9_dcache_sets_inc; 429extern unsigned arm9_dcache_index_max; 430extern unsigned arm9_dcache_index_inc; 431#endif 432 433#if defined(CPU_ARM9E) || defined(CPU_ARM10) 434void arm10_setttb (u_int); 435 436void arm10_tlb_flushID_SE (u_int); 437void arm10_tlb_flushI_SE (u_int); 438 439void arm10_icache_sync_all (void); 440void arm10_icache_sync_range (vm_offset_t, vm_size_t); 441 442void arm10_dcache_wbinv_all (void); 443void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 444void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 445void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 446 447void arm10_idcache_wbinv_all (void); 448void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 449 450void arm10_context_switch (void); 451 452void arm10_setup (char *string); 453 454extern unsigned arm10_dcache_sets_max; 455extern unsigned arm10_dcache_sets_inc; 456extern unsigned arm10_dcache_index_max; 457extern unsigned arm10_dcache_index_inc; 458 459u_int sheeva_control_ext (u_int, u_int); 460void sheeva_cpu_sleep (int); 461void sheeva_setttb (u_int); 462void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 463void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 464void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 465void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 466 467void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 468void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 469void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 470void sheeva_l2cache_wbinv_all (void); 471#endif 472 473#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \ 474 defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 475void arm11_setttb (u_int); 476void arm11_sleep (int); 477 478void arm11_tlb_flushID_SE (u_int); 479void arm11_tlb_flushI_SE (u_int); 480 481void arm11_context_switch (void); 482 483void arm11_setup (char *string); 484void arm11_tlb_flushID (void); 485void arm11_tlb_flushI (void); 486void arm11_tlb_flushD (void); 487void arm11_tlb_flushD_SE (u_int va); 488 489void arm11_drain_writebuf (void); 490 491void pj4b_setttb (u_int); 492 493void pj4b_drain_readbuf (void); 494void pj4b_flush_brnchtgt_all (void); 495void pj4b_flush_brnchtgt_va (u_int); 496void pj4b_sleep (int); 497 498void armv6_icache_sync_all (void); 499void armv6_icache_sync_range (vm_offset_t, vm_size_t); 500 501void armv6_dcache_wbinv_all (void); 502void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 503void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 504void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 505 506void armv6_idcache_inv_all (void); 507void armv6_idcache_wbinv_all (void); 508void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); 509 510void armv7_setttb (u_int); 511void armv7_tlb_flushID (void); 512void armv7_tlb_flushID_SE (u_int); 513void armv7_icache_sync_range (vm_offset_t, vm_size_t); 514void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 515void armv7_idcache_inv_all (void); 516void armv7_dcache_wbinv_all (void); 517void armv7_idcache_wbinv_all (void); 518void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 519void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 520void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 521void armv7_cpu_sleep (int); 522void armv7_setup (char *string); 523void armv7_context_switch (void); 524void armv7_drain_writebuf (void); 525void armv7_sev (void); 526u_int armv7_auxctrl (u_int, u_int); 527void pj4bv7_setup (char *string); 528void pj4b_config (void); 529 530int get_core_id (void); 531 532void armadaxp_idcache_wbinv_all (void); 533 534void cortexa_setup (char *); 535#endif 536 537#if defined(CPU_ARM1136) || defined(CPU_ARM1176) 538void arm11x6_setttb (u_int); 539void arm11x6_idcache_wbinv_all (void); 540void arm11x6_dcache_wbinv_all (void); 541void arm11x6_icache_sync_all (void); 542void arm11x6_flush_prefetchbuf (void); 543void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 544void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 545void arm11x6_setup (char *string); 546void arm11x6_sleep (int); /* no ref. for errata */ 547#endif 548#if defined(CPU_ARM1136) 549void arm1136_sleep_rev0 (int); /* for errata 336501 */ 550#endif 551 552#if defined(CPU_ARM9E) || defined (CPU_ARM10) 553void armv5_ec_setttb(u_int); 554 555void armv5_ec_icache_sync_all(void); 556void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 557 558void armv5_ec_dcache_wbinv_all(void); 559void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 560void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 561void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 562 563void armv5_ec_idcache_wbinv_all(void); 564void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 565#endif 566 567#if defined (CPU_ARM10) 568void armv5_setttb(u_int); 569 570void armv5_icache_sync_all(void); 571void armv5_icache_sync_range(vm_offset_t, vm_size_t); 572 573void armv5_dcache_wbinv_all(void); 574void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); 575void armv5_dcache_inv_range(vm_offset_t, vm_size_t); 576void armv5_dcache_wb_range(vm_offset_t, vm_size_t); 577 578void armv5_idcache_wbinv_all(void); 579void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); 580 581extern unsigned armv5_dcache_sets_max; 582extern unsigned armv5_dcache_sets_inc; 583extern unsigned armv5_dcache_index_max; 584extern unsigned armv5_dcache_index_inc; 585#endif 586 587#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 588 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 589 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 590 defined(CPU_FA526) || defined(CPU_FA626TE) || \ 591 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 592 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 593 594void armv4_tlb_flushID (void); 595void armv4_tlb_flushI (void); 596void armv4_tlb_flushD (void); 597void armv4_tlb_flushD_SE (u_int va); 598 599void armv4_drain_writebuf (void); 600void armv4_idcache_inv_all (void); 601#endif 602 603#if defined(CPU_IXP12X0) 604void ixp12x0_drain_readbuf (void); 605void ixp12x0_context_switch (void); 606void ixp12x0_setup (char *string); 607#endif 608 609#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 610 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 611 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 612void xscale_cpwait (void); 613 614void xscale_cpu_sleep (int mode); 615 616u_int xscale_control (u_int clear, u_int bic); 617 618void xscale_setttb (u_int ttb); 619 620void xscale_tlb_flushID_SE (u_int va); 621 622void xscale_cache_flushID (void); 623void xscale_cache_flushI (void); 624void xscale_cache_flushD (void); 625void xscale_cache_flushD_SE (u_int entry); 626 627void xscale_cache_cleanID (void); 628void xscale_cache_cleanD (void); 629void xscale_cache_cleanD_E (u_int entry); 630 631void xscale_cache_clean_minidata (void); 632 633void xscale_cache_purgeID (void); 634void xscale_cache_purgeID_E (u_int entry); 635void xscale_cache_purgeD (void); 636void xscale_cache_purgeD_E (u_int entry); 637 638void xscale_cache_syncI (void); 639void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 640void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 641void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 642void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 643void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 644void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 645 646void xscale_context_switch (void); 647 648void xscale_setup (char *string); 649#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 650 CPU_XSCALE_80219 */ 651 652#ifdef CPU_XSCALE_81342 653 654void xscalec3_l2cache_purge (void); 655void xscalec3_cache_purgeID (void); 656void xscalec3_cache_purgeD (void); 657void xscalec3_cache_cleanID (void); 658void xscalec3_cache_cleanD (void); 659void xscalec3_cache_syncI (void); 660 661void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 662void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 663void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 664void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 665void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 666 667void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 668void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 669void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 670 671 672void xscalec3_setttb (u_int ttb); 673void xscalec3_context_switch (void); 674 675#endif /* CPU_XSCALE_81342 */ 676 677#define tlb_flush cpu_tlb_flushID 678#define setttb cpu_setttb 679#define drain_writebuf cpu_drain_writebuf 680 681/* 682 * Macros for manipulating CPU interrupts 683 */ 684static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 685 686static __inline u_int32_t 687__set_cpsr_c(u_int bic, u_int eor) 688{ 689 u_int32_t tmp, ret; 690 691 __asm __volatile( 692 "mrs %0, cpsr\n" /* Get the CPSR */ 693 "bic %1, %0, %2\n" /* Clear bits */ 694 "eor %1, %1, %3\n" /* XOR bits */ 695 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 696 : "=&r" (ret), "=&r" (tmp) 697 : "r" (bic), "r" (eor) : "memory"); 698 699 return ret; 700} 701 702#define ARM_CPSR_F32 (1 << 6) /* FIQ disable */ 703#define ARM_CPSR_I32 (1 << 7) /* IRQ disable */ 704 705#define disable_interrupts(mask) \ 706 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \ 707 (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 708 709#define enable_interrupts(mask) \ 710 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0)) 711 712#define restore_interrupts(old_cpsr) \ 713 (__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \ 714 (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 715 716static __inline register_t 717intr_disable(void) 718{ 719 register_t s; 720 721 s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32); 722 return (s); 723} 724 725static __inline void 726intr_restore(register_t s) 727{ 728 729 restore_interrupts(s); 730} 731 732/* Functions to manipulate the CPSR. */ 733u_int SetCPSR(u_int bic, u_int eor); 734u_int GetCPSR(void); 735 736/* 737 * Functions to manipulate cpu r13 738 * (in arm/arm32/setstack.S) 739 */ 740 741void set_stackptr (u_int mode, u_int address); 742u_int get_stackptr (u_int mode); 743 744/* 745 * Miscellany 746 */ 747 748int get_pc_str_offset (void); 749 750/* 751 * CPU functions from locore.S 752 */ 753 754void cpu_reset (void) __attribute__((__noreturn__)); 755 756/* 757 * Cache info variables. 758 */ 759 760/* PRIMARY CACHE VARIABLES */ 761extern int arm_picache_size; 762extern int arm_picache_line_size; 763extern int arm_picache_ways; 764 765extern int arm_pdcache_size; /* and unified */ 766extern int arm_pdcache_line_size; 767extern int arm_pdcache_ways; 768 769extern int arm_pcache_type; 770extern int arm_pcache_unified; 771 772extern int arm_dcache_align; 773extern int arm_dcache_align_mask; 774 775extern u_int arm_cache_level; 776extern u_int arm_cache_loc; 777extern u_int arm_cache_type[14]; 778 779#endif /* _KERNEL */ 780#endif /* _MACHINE_CPUFUNC_H_ */ 781 782/* End of cpufunc.h */ 783