imx6_mp.c revision 266203 
1/*-
2 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de>
3 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx6_mp.c 266203 2014-05-16 00:14:50Z ian $");
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/lock.h>
33#include <sys/mutex.h>
34#include <sys/smp.h>
35
36#include <machine/smp.h>
37#include <machine/fdt.h>
38#include <machine/intr.h>
39
40#define	SCU_PHYSBASE			0x00a00000
41#define	SCU_SIZE			0x00001000
42
43#define	SCU_CONTROL_REG			0x00
44#define	  SCU_CONTROL_ENABLE		  (1 << 0)
45#define	SCU_CONFIG_REG			0x04
46#define	  SCU_CONFIG_REG_NCPU_MASK	  0x03
47#define	SCU_CPUPOWER_REG		0x08
48#define	SCU_INV_TAGS_REG		0x0c
49#define	SCU_DIAG_CONTROL		0x30
50#define	  SCU_DIAG_DISABLE_MIGBIT	  (1 << 0)
51#define	SCU_FILTER_START_REG		0x40
52#define	SCU_FILTER_END_REG		0x44
53#define	SCU_SECURE_ACCESS_REG		0x50
54#define	SCU_NONSECURE_ACCESS_REG	0x54
55
56#define	SRC_PHYSBASE			0x020d8000
57#define SRC_SIZE			0x4000
58#define	SRC_CONTROL_REG			0x00
59#define	SRC_CONTROL_C1ENA_SHIFT		  22	/* Bit for Core 1 enable */
60#define	SRC_CONTROL_C1RST_SHIFT		  14	/* Bit for Core 1 reset */
61#define	SRC_GPR0_C1FUNC			0x20	/* Register for Core 1 entry func */
62#define	SRC_GPR1_C1ARG			0x24	/* Register for Core 1 entry arg */
63
64void
65platform_mp_init_secondary(void)
66{
67
68	gic_init_secondary();
69}
70
71void
72platform_mp_setmaxid(void)
73{
74	bus_space_handle_t scu;
75	uint32_t val;
76
77	/* If we've already set the global vars don't bother to do it again. */
78	if (mp_ncpus != 0)
79		return;
80
81	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
82		panic("Couldn't map the SCU\n");
83	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG);
84	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
85
86	mp_maxid = (val & SCU_CONFIG_REG_NCPU_MASK);
87	mp_ncpus = mp_maxid + 1;
88}
89
90int
91platform_mp_probe(void)
92{
93
94	/* I think platform_mp_setmaxid must get called first, but be safe. */
95	if (mp_ncpus == 0)
96		platform_mp_setmaxid();
97
98	return (mp_ncpus > 1);
99}
100
101void
102platform_mp_start_ap(void)
103{
104	bus_space_handle_t scu;
105	bus_space_handle_t src;
106
107	uint32_t val;
108	int i;
109
110	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
111		panic("Couldn't map the SCU\n");
112	if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
113		panic("Couldn't map the system reset controller (SRC)\n");
114
115	/*
116	 * Invalidate SCU cache tags.  The 0x0000ffff constant invalidates all
117	 * ways on all cores 0-3.  Per the ARM docs, it's harmless to write to
118	 * the bits for cores that are not present.
119	 */
120	bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
121
122	/*
123	 * Erratum ARM/MP: 764369 (problems with cache maintenance).
124	 * Setting the "disable-migratory bit" in the undocumented SCU
125	 * Diagnostic Control Register helps work around the problem.
126	 */
127	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
128	bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
129	    val | SCU_DIAG_DISABLE_MIGBIT);
130
131	/*
132	 * Enable the SCU, then clean the cache on this core.  After these two
133	 * operations the cache tag ram in the SCU is coherent with the contents
134	 * of the cache on this core.  The other cores aren't running yet so
135	 * their caches can't contain valid data yet, but we've initialized
136	 * their SCU tag ram above, so they will be coherent from startup.
137	 */
138	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
139	bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
140	    val | SCU_CONTROL_ENABLE);
141	cpu_idcache_wbinv_all();
142
143	/*
144	 * For each AP core, set the entry point address and argument registers,
145	 * and set the core-enable and core-reset bits in the control register.
146	 */
147	val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
148	for (i=1; i < mp_ncpus; i++) {
149		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
150		    pmap_kextract((vm_offset_t)mpentry));
151		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG  + 8*i, 0);
152
153		val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
154		    ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
155
156	}
157	bus_space_write_4(fdtbus_bs_tag, src, 0, val);
158
159	armv7_sev();
160
161	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
162	bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
163}
164
165void
166platform_ipi_send(cpuset_t cpus, u_int ipi)
167{
168
169	pic_ipi_send(cpus, ipi);
170}
171