bcm2835_sdhci.c revision 318198
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 318198 2017-05-11 21:01:02Z marius $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/mutex.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <machine/bus.h> 43 44#include <dev/fdt/fdt_common.h> 45#include <dev/ofw/ofw_bus.h> 46#include <dev/ofw/ofw_bus_subr.h> 47 48#include <dev/mmc/bridge.h> 49#include <dev/mmc/mmcreg.h> 50 51#include <dev/sdhci/sdhci.h> 52 53#include "mmcbr_if.h" 54#include "sdhci_if.h" 55 56#include "bcm2835_dma.h" 57#include "bcm2835_vcbus.h" 58 59#define BCM2835_DEFAULT_SDHCI_FREQ 50 60 61#define BCM_SDHCI_BUFFER_SIZE 512 62#define NUM_DMA_SEGS 2 63 64#ifdef DEBUG 65#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67#else 68#define dprintf(fmt, args...) 69#endif 70 71static int bcm2835_sdhci_hs = 1; 72static int bcm2835_sdhci_pio_mode = 0; 73 74TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 75TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 76 77struct bcm_sdhci_softc { 78 device_t sc_dev; 79 struct mtx sc_mtx; 80 struct resource * sc_mem_res; 81 struct resource * sc_irq_res; 82 bus_space_tag_t sc_bst; 83 bus_space_handle_t sc_bsh; 84 void * sc_intrhand; 85 struct mmc_request * sc_req; 86 struct mmc_data * sc_data; 87 uint32_t sc_flags; 88#define LPC_SD_FLAGS_IGNORECRC (1 << 0) 89 int sc_xfer_direction; 90#define DIRECTION_READ 0 91#define DIRECTION_WRITE 1 92 int sc_xfer_done; 93 int sc_bus_busy; 94 struct sdhci_slot sc_slot; 95 int sc_dma_inuse; 96 int sc_dma_ch; 97 bus_dma_tag_t sc_dma_tag; 98 bus_dmamap_t sc_dma_map; 99 vm_paddr_t sc_sdhci_buffer_phys; 100 uint32_t cmd_and_mode; 101 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 102 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 103 int dmamap_seg_count; 104 int dmamap_seg_index; 105 int dmamap_status; 106}; 107 108static int bcm_sdhci_probe(device_t); 109static int bcm_sdhci_attach(device_t); 110static int bcm_sdhci_detach(device_t); 111static void bcm_sdhci_intr(void *); 112 113static int bcm_sdhci_get_ro(device_t, device_t); 114static void bcm_sdhci_dma_intr(int ch, void *arg); 115 116#define bcm_sdhci_lock(_sc) \ 117 mtx_lock(&_sc->sc_mtx); 118#define bcm_sdhci_unlock(_sc) \ 119 mtx_unlock(&_sc->sc_mtx); 120 121static void 122bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 123{ 124 struct bcm_sdhci_softc *sc = arg; 125 int i; 126 127 sc->dmamap_status = err; 128 sc->dmamap_seg_count = nseg; 129 130 /* Note nseg is guaranteed to be zero if err is non-zero. */ 131 for (i = 0; i < nseg; i++) { 132 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 133 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 134 } 135} 136 137static int 138bcm_sdhci_probe(device_t dev) 139{ 140 141 if (!ofw_bus_status_okay(dev)) 142 return (ENXIO); 143 144 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 145 return (ENXIO); 146 147 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 148 return (BUS_PROBE_DEFAULT); 149} 150 151static int 152bcm_sdhci_attach(device_t dev) 153{ 154 struct bcm_sdhci_softc *sc = device_get_softc(dev); 155 int rid, err; 156 phandle_t node; 157 pcell_t cell; 158 int default_freq; 159 160 sc->sc_dev = dev; 161 sc->sc_req = NULL; 162 err = 0; 163 164 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 165 node = ofw_bus_get_node(sc->sc_dev); 166 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 167 default_freq = (int)fdt32_to_cpu(cell)/1000000; 168 169 dprintf("SDHCI frequency: %dMHz\n", default_freq); 170 171 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 172 173 rid = 0; 174 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 175 RF_ACTIVE); 176 if (!sc->sc_mem_res) { 177 device_printf(dev, "cannot allocate memory window\n"); 178 err = ENXIO; 179 goto fail; 180 } 181 182 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 183 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 184 185 rid = 0; 186 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 187 RF_ACTIVE); 188 if (!sc->sc_irq_res) { 189 device_printf(dev, "cannot allocate interrupt\n"); 190 err = ENXIO; 191 goto fail; 192 } 193 194 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 195 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 196 device_printf(dev, "cannot setup interrupt handler\n"); 197 err = ENXIO; 198 goto fail; 199 } 200 201 if (!bcm2835_sdhci_pio_mode) 202 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 203 204 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 205 if (bcm2835_sdhci_hs) 206 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 207 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 208 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 209 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 210 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 211 | SDHCI_QUIRK_MISSING_CAPS; 212 213 sdhci_init_slot(dev, &sc->sc_slot, 0); 214 215 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 216 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 217 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 218 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 219 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 220 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 221 goto fail; 222 223 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 224 225 /* Allocate bus_dma resources. */ 226 err = bus_dma_tag_create(bus_get_dma_tag(dev), 227 1, 0, BUS_SPACE_MAXADDR_32BIT, 228 BUS_SPACE_MAXADDR, NULL, NULL, 229 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 230 BUS_DMA_ALLOCNOW, NULL, NULL, 231 &sc->sc_dma_tag); 232 233 if (err) { 234 device_printf(dev, "failed allocate DMA tag"); 235 goto fail; 236 } 237 238 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 239 if (err) { 240 device_printf(dev, "bus_dmamap_create failed\n"); 241 goto fail; 242 } 243 244 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 245 SDHCI_BUFFER); 246 247 bus_generic_probe(dev); 248 bus_generic_attach(dev); 249 250 sdhci_start_slot(&sc->sc_slot); 251 252 return (0); 253 254fail: 255 if (sc->sc_intrhand) 256 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 257 if (sc->sc_irq_res) 258 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 259 if (sc->sc_mem_res) 260 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 261 mtx_destroy(&sc->sc_mtx); 262 263 return (err); 264} 265 266static int 267bcm_sdhci_detach(device_t dev) 268{ 269 270 return (EBUSY); 271} 272 273static void 274bcm_sdhci_intr(void *arg) 275{ 276 struct bcm_sdhci_softc *sc = arg; 277 278 sdhci_generic_intr(&sc->sc_slot); 279} 280 281static int 282bcm_sdhci_get_ro(device_t bus, device_t child) 283{ 284 285 return (0); 286} 287 288static inline uint32_t 289RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 290{ 291 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 292 return val; 293} 294 295static inline void 296WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 297{ 298 299 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 300 /* 301 * The Arasan HC has a bug where it may lose the content of 302 * consecutive writes to registers that are within two SD-card 303 * clock cycles of each other (a clock domain crossing problem). 304 */ 305 if (sc->sc_slot.clock > 0) 306 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 307} 308 309static uint8_t 310bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 311{ 312 struct bcm_sdhci_softc *sc = device_get_softc(dev); 313 uint32_t val = RD4(sc, off & ~3); 314 315 return ((val >> (off & 3)*8) & 0xff); 316} 317 318static uint16_t 319bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 320{ 321 struct bcm_sdhci_softc *sc = device_get_softc(dev); 322 uint32_t val = RD4(sc, off & ~3); 323 324 /* 325 * Standard 32-bit handling of command and transfer mode. 326 */ 327 if (off == SDHCI_TRANSFER_MODE) { 328 return (sc->cmd_and_mode >> 16); 329 } else if (off == SDHCI_COMMAND_FLAGS) { 330 return (sc->cmd_and_mode & 0x0000ffff); 331 } 332 return ((val >> (off & 3)*8) & 0xffff); 333} 334 335static uint32_t 336bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 337{ 338 struct bcm_sdhci_softc *sc = device_get_softc(dev); 339 340 return RD4(sc, off); 341} 342 343static void 344bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 345 uint32_t *data, bus_size_t count) 346{ 347 struct bcm_sdhci_softc *sc = device_get_softc(dev); 348 349 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 350} 351 352static void 353bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 354{ 355 struct bcm_sdhci_softc *sc = device_get_softc(dev); 356 uint32_t val32 = RD4(sc, off & ~3); 357 val32 &= ~(0xff << (off & 3)*8); 358 val32 |= (val << (off & 3)*8); 359 WR4(sc, off & ~3, val32); 360} 361 362static void 363bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 364{ 365 struct bcm_sdhci_softc *sc = device_get_softc(dev); 366 uint32_t val32; 367 if (off == SDHCI_COMMAND_FLAGS) 368 val32 = sc->cmd_and_mode; 369 else 370 val32 = RD4(sc, off & ~3); 371 val32 &= ~(0xffff << (off & 3)*8); 372 val32 |= (val << (off & 3)*8); 373 if (off == SDHCI_TRANSFER_MODE) 374 sc->cmd_and_mode = val32; 375 else { 376 WR4(sc, off & ~3, val32); 377 if (off == SDHCI_COMMAND_FLAGS) 378 sc->cmd_and_mode = val32; 379 } 380} 381 382static void 383bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 384{ 385 struct bcm_sdhci_softc *sc = device_get_softc(dev); 386 WR4(sc, off, val); 387} 388 389static void 390bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 391 uint32_t *data, bus_size_t count) 392{ 393 struct bcm_sdhci_softc *sc = device_get_softc(dev); 394 395 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 396} 397 398static void 399bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 400{ 401 struct sdhci_slot *slot; 402 vm_paddr_t pdst, psrc; 403 int err, idx, len, sync_op; 404 405 slot = &sc->sc_slot; 406 idx = sc->dmamap_seg_index++; 407 len = sc->dmamap_seg_sizes[idx]; 408 slot->offset += len; 409 410 if (slot->curcmd->data->flags & MMC_DATA_READ) { 411 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 412 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 413 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 414 BCM_DMA_INC_ADDR, 415 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 416 psrc = sc->sc_sdhci_buffer_phys; 417 pdst = sc->dmamap_seg_addrs[idx]; 418 sync_op = BUS_DMASYNC_PREREAD; 419 } else { 420 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 421 BCM_DMA_INC_ADDR, 422 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 423 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 424 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 425 psrc = sc->dmamap_seg_addrs[idx]; 426 pdst = sc->sc_sdhci_buffer_phys; 427 sync_op = BUS_DMASYNC_PREWRITE; 428 } 429 430 /* 431 * When starting a new DMA operation do the busdma sync operation, and 432 * disable SDCHI data interrrupts because we'll be driven by DMA 433 * interrupts (or SDHCI error interrupts) until the IO is done. 434 */ 435 if (idx == 0) { 436 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 437 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 438 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 439 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 440 slot->intmask); 441 } 442 443 /* 444 * Start the DMA transfer. Only programming errors (like failing to 445 * allocate a channel) cause a non-zero return from bcm_dma_start(). 446 */ 447 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 448 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 449} 450 451static void 452bcm_sdhci_dma_intr(int ch, void *arg) 453{ 454 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 455 struct sdhci_slot *slot = &sc->sc_slot; 456 uint32_t reg, mask; 457 int left, sync_op; 458 459 mtx_lock(&slot->mtx); 460 461 /* 462 * If there are more segments for the current dma, start the next one. 463 * Otherwise unload the dma map and decide what to do next based on the 464 * status of the sdhci controller and whether there's more data left. 465 */ 466 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 467 bcm_sdhci_start_dma_seg(sc); 468 mtx_unlock(&slot->mtx); 469 return; 470 } 471 472 if (slot->curcmd->data->flags & MMC_DATA_READ) { 473 sync_op = BUS_DMASYNC_POSTREAD; 474 mask = SDHCI_INT_DATA_AVAIL; 475 } else { 476 sync_op = BUS_DMASYNC_POSTWRITE; 477 mask = SDHCI_INT_SPACE_AVAIL; 478 } 479 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 480 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 481 482 sc->dmamap_seg_count = 0; 483 sc->dmamap_seg_index = 0; 484 485 left = min(BCM_SDHCI_BUFFER_SIZE, 486 slot->curcmd->data->len - slot->offset); 487 488 /* DATA END? */ 489 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 490 491 if (reg & SDHCI_INT_DATA_END) { 492 /* ACK for all outstanding interrupts */ 493 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 494 495 /* enable INT */ 496 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 497 | SDHCI_INT_DATA_END; 498 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 499 slot->intmask); 500 501 /* finish this data */ 502 sdhci_finish_data(slot); 503 } 504 else { 505 /* already available? */ 506 if (reg & mask) { 507 508 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 509 bcm_sdhci_write_4(slot->bus, slot, 510 SDHCI_INT_STATUS, mask); 511 512 /* continue next DMA transfer */ 513 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 514 (uint8_t *)slot->curcmd->data->data + 515 slot->offset, left, bcm_sdhci_dmacb, sc, 516 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 517 slot->curcmd->error = MMC_ERR_NO_MEMORY; 518 sdhci_finish_data(slot); 519 } else { 520 bcm_sdhci_start_dma_seg(sc); 521 } 522 } else { 523 /* wait for next data by INT */ 524 525 /* enable INT */ 526 slot->intmask |= SDHCI_INT_DATA_AVAIL | 527 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 528 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 529 slot->intmask); 530 } 531 } 532 533 mtx_unlock(&slot->mtx); 534} 535 536static void 537bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 538{ 539 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 540 size_t left; 541 542 if (sc->dmamap_seg_count != 0) { 543 device_printf(sc->sc_dev, "DMA in use\n"); 544 return; 545 } 546 547 left = min(BCM_SDHCI_BUFFER_SIZE, 548 slot->curcmd->data->len - slot->offset); 549 550 KASSERT((left & 3) == 0, 551 ("%s: len = %d, not word-aligned", __func__, left)); 552 553 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 554 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 555 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 556 sc->dmamap_status != 0) { 557 slot->curcmd->error = MMC_ERR_NO_MEMORY; 558 return; 559 } 560 561 /* DMA start */ 562 bcm_sdhci_start_dma_seg(sc); 563} 564 565static void 566bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 567{ 568 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 569 size_t left; 570 571 if (sc->dmamap_seg_count != 0) { 572 device_printf(sc->sc_dev, "DMA in use\n"); 573 return; 574 } 575 576 left = min(BCM_SDHCI_BUFFER_SIZE, 577 slot->curcmd->data->len - slot->offset); 578 579 KASSERT((left & 3) == 0, 580 ("%s: len = %d, not word-aligned", __func__, left)); 581 582 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 583 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 584 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 585 sc->dmamap_status != 0) { 586 slot->curcmd->error = MMC_ERR_NO_MEMORY; 587 return; 588 } 589 590 /* DMA start */ 591 bcm_sdhci_start_dma_seg(sc); 592} 593 594static int 595bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 596{ 597 size_t left; 598 599 /* 600 * Do not use DMA for transfers less than block size or with a length 601 * that is not a multiple of four. 602 */ 603 left = min(BCM_DMA_BLOCK_SIZE, 604 slot->curcmd->data->len - slot->offset); 605 if (left < BCM_DMA_BLOCK_SIZE) 606 return (0); 607 if (left & 0x03) 608 return (0); 609 610 return (1); 611} 612 613static void 614bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 615 uint32_t *intmask) 616{ 617 618 /* DMA transfer FIFO 1KB */ 619 if (slot->curcmd->data->flags & MMC_DATA_READ) 620 bcm_sdhci_read_dma(dev, slot); 621 else 622 bcm_sdhci_write_dma(dev, slot); 623} 624 625static void 626bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 627{ 628 629 sdhci_finish_data(slot); 630} 631 632static device_method_t bcm_sdhci_methods[] = { 633 /* Device interface */ 634 DEVMETHOD(device_probe, bcm_sdhci_probe), 635 DEVMETHOD(device_attach, bcm_sdhci_attach), 636 DEVMETHOD(device_detach, bcm_sdhci_detach), 637 638 /* Bus interface */ 639 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 640 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 641 642 /* MMC bridge interface */ 643 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 644 DEVMETHOD(mmcbr_request, sdhci_generic_request), 645 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 646 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 647 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 648 649 /* Platform transfer methods */ 650 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 651 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 652 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 653 /* SDHCI registers accessors */ 654 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 655 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 656 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 657 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 658 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 659 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 660 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 661 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 662 663 DEVMETHOD_END 664}; 665 666static devclass_t bcm_sdhci_devclass; 667 668static driver_t bcm_sdhci_driver = { 669 "sdhci_bcm", 670 bcm_sdhci_methods, 671 sizeof(struct bcm_sdhci_softc), 672}; 673 674DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 675 NULL, NULL); 676MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 677MMC_DECLARE_BRIDGE(sdhci_bcm); 678