imx_sdhci.c revision 266152
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx_sdhci.c 266152 2014-05-15 16:11:06Z ian $"); 29 30/* 31 * SDHCI driver glue for Freescale i.MX SoC family. 32 * 33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/resource.h> 43#include <sys/rman.h> 44#include <sys/taskqueue.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <machine/intr.h> 49 50#include <arm/freescale/imx/imx51_ccmvar.h> 51 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55#include <dev/mmc/bridge.h> 56#include <dev/mmc/mmcreg.h> 57#include <dev/mmc/mmcbrvar.h> 58 59#include <dev/sdhci/sdhci.h> 60#include "sdhci_if.h" 61 62struct imx_sdhci_softc { 63 device_t dev; 64 struct resource * mem_res; 65 struct resource * irq_res; 66 void * intr_cookie; 67 struct sdhci_slot slot; 68 uint32_t baseclk_hz; 69 uint32_t sdclockreg_freq_bits; 70 uint32_t cmd_and_mode; 71 uint32_t r1bfix_intmask; 72 uint8_t r1bfix_type; 73 uint8_t hwtype; 74}; 75 76#define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 77#define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 78#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 79 80#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 81#define HWTYPE_ESDHC 1 /* imx5x and earlier. */ 82#define HWTYPE_USDHC 2 /* imx6. */ 83 84#define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 85#define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 86#define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 87#define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 88#define SDHC_VEND_IPGEN (1 << 11) 89#define SDHC_VEND_HCKEN (1 << 12) 90#define SDHC_VEND_PEREN (1 << 13) 91 92#define SDHC_PROT_CTRL 0x28 93#define SDHC_PROT_LED (1 << 0) 94#define SDHC_PROT_WIDTH_1BIT (0 << 1) 95#define SDHC_PROT_WIDTH_4BIT (1 << 1) 96#define SDHC_PROT_WIDTH_8BIT (2 << 1) 97#define SDHC_PROT_WIDTH_MASK (3 << 1) 98#define SDHC_PROT_D3CD (1 << 3) 99#define SDHC_PROT_EMODE_BIG (0 << 4) 100#define SDHC_PROT_EMODE_HALF (1 << 4) 101#define SDHC_PROT_EMODE_LITTLE (2 << 4) 102#define SDHC_PROT_EMODE_MASK (3 << 4) 103#define SDHC_PROT_SDMA (0 << 8) 104#define SDHC_PROT_ADMA1 (1 << 8) 105#define SDHC_PROT_ADMA2 (2 << 8) 106#define SDHC_PROT_ADMA264 (3 << 8) 107#define SDHC_PROT_DMA_MASK (3 << 8) 108#define SDHC_PROT_CDTL (1 << 6) 109#define SDHC_PROT_CDSS (1 << 7) 110 111#define SDHC_CLK_IPGEN (1 << 0) 112#define SDHC_CLK_HCKEN (1 << 1) 113#define SDHC_CLK_PEREN (1 << 2) 114#define SDHC_CLK_DIVISOR_MASK 0x000000f0 115#define SDHC_CLK_DIVISOR_SHIFT 4 116#define SDHC_CLK_PRESCALE_MASK 0x0000ff00 117#define SDHC_CLK_PRESCALE_SHIFT 8 118 119static struct ofw_compat_data compat_data[] = { 120 {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 121 {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 122 {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 123 {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 124 {NULL, HWTYPE_NONE}, 125};; 126 127static void imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable); 128 129static inline uint32_t 130RD4(struct imx_sdhci_softc *sc, bus_size_t off) 131{ 132 133 return (bus_read_4(sc->mem_res, off)); 134} 135 136static inline void 137WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val) 138{ 139 140 bus_write_4(sc->mem_res, off, val); 141} 142 143static uint8_t 144imx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 145{ 146 struct imx_sdhci_softc *sc = device_get_softc(dev); 147 uint32_t val32, wrk32; 148 149 /* 150 * Most of the things in the standard host control register are in the 151 * hardware's wider protocol control register, but some of the bits are 152 * moved around. 153 */ 154 if (off == SDHCI_HOST_CONTROL) { 155 wrk32 = RD4(sc, SDHC_PROT_CTRL); 156 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 157 SDHCI_CTRL_FORCE_CARD); 158 switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 159 case SDHC_PROT_WIDTH_1BIT: 160 /* Value is already 0. */ 161 break; 162 case SDHC_PROT_WIDTH_4BIT: 163 val32 |= SDHCI_CTRL_4BITBUS; 164 break; 165 case SDHC_PROT_WIDTH_8BIT: 166 val32 |= SDHCI_CTRL_8BITBUS; 167 break; 168 } 169 switch (wrk32 & SDHC_PROT_DMA_MASK) { 170 case SDHC_PROT_SDMA: 171 /* Value is already 0. */ 172 break; 173 case SDHC_PROT_ADMA1: 174 /* This value is deprecated, should never appear. */ 175 break; 176 case SDHC_PROT_ADMA2: 177 val32 |= SDHCI_CTRL_ADMA2; 178 break; 179 case SDHC_PROT_ADMA264: 180 val32 |= SDHCI_CTRL_ADMA264; 181 break; 182 } 183 return val32; 184 } 185 186 /* 187 * XXX can't find the bus power on/off knob. For now we have to say the 188 * power is always on and always set to the same voltage. 189 */ 190 if (off == SDHCI_POWER_CONTROL) { 191 return (SDHCI_POWER_ON | SDHCI_POWER_300); 192 } 193 194 195 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 196} 197 198static uint16_t 199imx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 200{ 201 struct imx_sdhci_softc *sc = device_get_softc(dev); 202 uint32_t val32, wrk32; 203 204 if (sc->hwtype == HWTYPE_USDHC) { 205 /* 206 * The USDHC hardware has nothing in the version register, but 207 * it's v3 compatible with all our translation code. 208 */ 209 if (off == SDHCI_HOST_VERSION) { 210 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 211 } 212 /* 213 * The USDHC hardware moved the transfer mode bits to the mixed 214 * control register, fetch them from there. 215 */ 216 if (off == SDHCI_TRANSFER_MODE) 217 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 218 219 } else if (sc->hwtype == HWTYPE_ESDHC) { 220 221 /* 222 * The ESDHC hardware has the typical 32-bit combined "command 223 * and mode" register that we have to cache so that command 224 * isn't written until after mode. On a read, just retrieve the 225 * cached values last written. 226 */ 227 if (off == SDHCI_TRANSFER_MODE) { 228 return (sc->cmd_and_mode >> 16); 229 } else if (off == SDHCI_COMMAND_FLAGS) { 230 return (sc->cmd_and_mode & 0x0000ffff); 231 } 232 } 233 234 /* 235 * This hardware only manages one slot. Synthesize a slot interrupt 236 * status register... if there are any enabled interrupts active they 237 * must be coming from our one and only slot. 238 */ 239 if (off == SDHCI_SLOT_INT_STATUS) { 240 val32 = RD4(sc, SDHCI_INT_STATUS); 241 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 242 return (val32 ? 1 : 0); 243 } 244 245 /* 246 * The clock enable bit is in the vendor register and the clock-stable 247 * bit is in the present state register. Transcribe them as if they 248 * were in the clock control register where they should be. 249 * XXX Is it important that we distinguish between "internal" and "card" 250 * clocks? Probably not; transcribe the card clock status to both bits. 251 */ 252 if (off == SDHCI_CLOCK_CONTROL) { 253 val32 = 0; 254 wrk32 = RD4(sc, SDHC_VEND_SPEC); 255 if (wrk32 & SDHC_VEND_FRC_SDCLK_ON) 256 val32 |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN; 257 wrk32 = RD4(sc, SDHCI_PRESENT_STATE); 258 if (wrk32 & 0x08) 259 val32 |= SDHCI_CLOCK_INT_STABLE; 260 val32 |= sc->sdclockreg_freq_bits; 261 return (val32); 262 } 263 264 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 265} 266 267static uint32_t 268imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 269{ 270 struct imx_sdhci_softc *sc = device_get_softc(dev); 271 uint32_t val32; 272 273 /* 274 * The hardware leaves the base clock frequency out of the capabilities 275 * register; fill it in. The timeout clock is the same as the active 276 * output sdclock; we indicate that with a quirk setting so don't 277 * populate the timeout frequency bits. 278 * 279 * XXX Turn off (for now) features the hardware can do but this driver 280 * doesn't yet handle (1.8v, suspend/resume, etc). 281 */ 282 if (off == SDHCI_CAPABILITIES) { 283 val32 = RD4(sc, off); 284 val32 &= ~SDHCI_CAN_VDD_180; 285 val32 &= ~SDHCI_CAN_DO_SUSPEND; 286 val32 |= SDHCI_CAN_DO_8BITBUS; 287 val32 |= (sc->baseclk_hz / 1000000) << SDHCI_CLOCK_BASE_SHIFT; 288 return (val32); 289 } 290 291 val32 = RD4(sc, off); 292 293 /* 294 * imx_sdhci_intr() can synthesize a DATA_END interrupt following a 295 * command with an R1B response, mix it into the hardware status. 296 */ 297 if (off == SDHCI_INT_STATUS) { 298 val32 |= sc->r1bfix_intmask; 299 } 300 301 return val32; 302} 303 304static void 305imx_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 306 uint32_t *data, bus_size_t count) 307{ 308 struct imx_sdhci_softc *sc = device_get_softc(dev); 309 310 bus_read_multi_4(sc->mem_res, off, data, count); 311} 312 313static void 314imx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 315{ 316 struct imx_sdhci_softc *sc = device_get_softc(dev); 317 uint32_t val32; 318 319 /* 320 * Most of the things in the standard host control register are in the 321 * hardware's wider protocol control register, but some of the bits are 322 * moved around. 323 */ 324 if (off == SDHCI_HOST_CONTROL) { 325 val32 = RD4(sc, SDHC_PROT_CTRL); 326 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 327 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 328 val32 |= (val & SDHCI_CTRL_LED); 329 if (val & SDHCI_CTRL_8BITBUS) 330 val32 |= SDHC_PROT_WIDTH_8BIT; 331 else 332 val32 |= (val & SDHCI_CTRL_4BITBUS); 333 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 334 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 335 WR4(sc, SDHC_PROT_CTRL, val32); 336 return; 337 } 338 339 /* XXX I can't find the bus power on/off knob; do nothing. */ 340 if (off == SDHCI_POWER_CONTROL) { 341 return; 342 } 343 344 val32 = RD4(sc, off & ~3); 345 val32 &= ~(0xff << (off & 3) * 8); 346 val32 |= (val << (off & 3) * 8); 347 348 WR4(sc, off & ~3, val32); 349} 350 351static void 352imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 353{ 354 struct imx_sdhci_softc *sc = device_get_softc(dev); 355 uint32_t val32; 356 357 /* The USDHC hardware moved the transfer mode bits to mixed control. */ 358 if (sc->hwtype == HWTYPE_USDHC) { 359 if (off == SDHCI_TRANSFER_MODE) { 360 val32 = RD4(sc, USDHC_MIX_CONTROL); 361 val32 &= ~0x3f; 362 val32 |= val & 0x37; 363 // XXX acmd23 not supported here (or by sdhci driver) 364 WR4(sc, USDHC_MIX_CONTROL, val32); 365 return; 366 } 367 } 368 369 /* 370 * The clock control stuff is complex enough to have its own routine 371 * that can both change speeds and en/disable the clock output. Also, 372 * save the register bits in SDHCI format so that we can play them back 373 * in the read2 routine without complex decoding. 374 */ 375 if (off == SDHCI_CLOCK_CONTROL) { 376 sc->sdclockreg_freq_bits = val & 0xffc0; 377 if (val & SDHCI_CLOCK_CARD_EN) { 378 imx_sdhc_set_clock(sc, true); 379 } else { 380 imx_sdhc_set_clock(sc, false); 381 } 382 } 383 384 /* 385 * Figure out whether we need to check the DAT0 line for busy status at 386 * interrupt time. The controller should be doing this, but for some 387 * reason it doesn't. There are two cases: 388 * - R1B response with no data transfer should generate a DATA_END (aka 389 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 390 * there's no data transfer there's no DATA_END interrupt. This is 391 * documented; they seem to think it's a feature. 392 * - R1B response after Auto-CMD12 appears to not work, even though 393 * there's a control bit for it (bit 3) in the vendor register. 394 * When we're starting a command that needs a manual DAT0 line check at 395 * interrupt time, we leave ourselves a note in r1bfix_type so that we 396 * can do the extra work in imx_sdhci_intr(). 397 */ 398 if (off == SDHCI_COMMAND_FLAGS) { 399 if (val & SDHCI_CMD_DATA) { 400 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 401 val32 = RD4(sc, USDHC_MIX_CONTROL); 402 if ((val32 & MBAUTOCMD) == MBAUTOCMD) 403 sc->r1bfix_type = R1BFIX_AC12; 404 } else { 405 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 406 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 407 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 408 sc->r1bfix_type = R1BFIX_NODATA; 409 } 410 } 411 } 412 413 val32 = RD4(sc, off & ~3); 414 val32 &= ~(0xffff << (off & 3) * 8); 415 val32 |= ((val & 0xffff) << (off & 3) * 8); 416 WR4(sc, off & ~3, val32); 417} 418 419static void 420imx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 421{ 422 struct imx_sdhci_softc *sc = device_get_softc(dev); 423 424 /* Clear synthesized interrupts, then pass the value to the hardware. */ 425 if (off == SDHCI_INT_STATUS) { 426 sc->r1bfix_intmask &= ~val; 427 } 428 429 WR4(sc, off, val); 430} 431 432static void 433imx_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 434 uint32_t *data, bus_size_t count) 435{ 436 struct imx_sdhci_softc *sc = device_get_softc(dev); 437 438 bus_write_multi_4(sc->mem_res, off, data, count); 439} 440 441static void 442imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable) 443{ 444 uint32_t divisor, enable_bits, enable_reg, freq, prescale, val32; 445 446 if (sc->hwtype == HWTYPE_ESDHC) { 447 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) & 448 SDHCI_DIVIDER_MASK; 449 enable_reg = SDHCI_CLOCK_CONTROL; 450 enable_bits = SDHC_CLK_IPGEN | SDHC_CLK_HCKEN | 451 SDHC_CLK_PEREN; 452 } else { 453 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) & 454 SDHCI_DIVIDER_MASK; 455 divisor |= ((sc->sdclockreg_freq_bits >> 456 SDHCI_DIVIDER_HI_SHIFT) & 457 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 458 enable_reg = SDHCI_CLOCK_CONTROL; 459 enable_bits = SDHC_VEND_IPGEN | SDHC_VEND_HCKEN | 460 SDHC_VEND_PEREN; 461 } 462 463 WR4(sc, SDHC_VEND_SPEC, 464 RD4(sc, SDHC_VEND_SPEC) & ~SDHC_VEND_FRC_SDCLK_ON); 465 WR4(sc, enable_reg, RD4(sc, enable_reg) & ~enable_bits); 466 467 if (!enable) 468 return; 469 470 if (divisor == 0) 471 freq = sc->baseclk_hz; 472 else 473 freq = sc->baseclk_hz / (2 * divisor); 474 475 for (prescale = 2; prescale < freq / prescale / 16;) 476 prescale <<= 1; 477 478 for (divisor = 1; freq < freq / prescale / divisor;) 479 ++divisor; 480 481 prescale >>= 1; 482 divisor -= 1; 483 484 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 485 val32 &= ~SDHC_CLK_DIVISOR_MASK; 486 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 487 val32 &= ~SDHC_CLK_PRESCALE_MASK; 488 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 489 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 490 491 WR4(sc, enable_reg, RD4(sc, enable_reg) | enable_bits); 492 WR4(sc, SDHC_VEND_SPEC, 493 RD4(sc, SDHC_VEND_SPEC) | SDHC_VEND_FRC_SDCLK_ON); 494} 495 496static void 497imx_sdhci_intr(void *arg) 498{ 499 struct imx_sdhci_softc *sc = arg; 500 uint32_t intmask; 501 502 intmask = RD4(sc, SDHCI_INT_STATUS); 503 504 /* 505 * Manually check the DAT0 line for R1B response types that the 506 * controller fails to handle properly. 507 * 508 * To do the NODATA fix, when the RESPONSE (COMMAND_COMPLETE) interrupt 509 * occurs, we have to wait for the DAT0 line to be released, then 510 * synthesize a DATA_END (TRANSFER_COMPLETE) interrupt, which we do by 511 * storing SDHCI_INT_DATA_END into a variable that gets ORed into the 512 * return value when the SDHCI_INT_STATUS register is read. 513 * 514 * For the AC12 fix, when the DATA_END interrupt occurs we wait for the 515 * DAT0 line to be released, and the waiting is all the fix we need. 516 */ 517 if ((sc->r1bfix_type == R1BFIX_NODATA && 518 (intmask & SDHCI_INT_RESPONSE)) || 519 (sc->r1bfix_type == R1BFIX_AC12 && 520 (intmask & SDHCI_INT_DATA_END))) { 521 uint32_t count; 522 count = 0; 523 /* XXX use a callout or something instead of busy-waiting. */ 524 while (count < 250000 && 525 (RD4(sc, SDHCI_PRESENT_STATE) & SDHCI_DAT_ACTIVE)) { 526 ++count; 527 DELAY(1); 528 } 529 if (count >= 250000) 530 sc->r1bfix_intmask = SDHCI_INT_DATA_TIMEOUT; 531 else if (sc->r1bfix_type == R1BFIX_NODATA) 532 sc->r1bfix_intmask = SDHCI_INT_DATA_END; 533 sc->r1bfix_type = R1BFIX_NONE; 534 } 535 536 sdhci_generic_intr(&sc->slot); 537} 538 539static int 540imx_sdhci_get_ro(device_t bus, device_t child) 541{ 542 543 return (false); 544} 545 546static int 547imx_sdhci_detach(device_t dev) 548{ 549 550 return (EBUSY); 551} 552 553static int 554imx_sdhci_attach(device_t dev) 555{ 556 struct imx_sdhci_softc *sc = device_get_softc(dev); 557 int rid, err; 558 559 sc->dev = dev; 560 561 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 562 if (sc->hwtype == HWTYPE_NONE) 563 panic("Impossible: not compatible in imx_sdhci_attach()"); 564 565 rid = 0; 566 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 567 RF_ACTIVE); 568 if (!sc->mem_res) { 569 device_printf(dev, "cannot allocate memory window\n"); 570 err = ENXIO; 571 goto fail; 572 } 573 574 rid = 0; 575 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 576 RF_ACTIVE); 577 if (!sc->irq_res) { 578 device_printf(dev, "cannot allocate interrupt\n"); 579 err = ENXIO; 580 goto fail; 581 } 582 583 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 584 NULL, imx_sdhci_intr, sc, &sc->intr_cookie)) { 585 device_printf(dev, "cannot setup interrupt handler\n"); 586 err = ENXIO; 587 goto fail; 588 } 589 590 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 591 592 /* 593 * DMA is not really broken, I just haven't implemented it yet. 594 */ 595 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 596 597 /* 598 * Set the buffer watermark level to 128 words (512 bytes) for both read 599 * and write. The hardware has a restriction that when the read or 600 * write ready status is asserted, that means you can read exactly the 601 * number of words set in the watermark register before you have to 602 * re-check the status and potentially wait for more data. The main 603 * sdhci driver provides no hook for doing status checking on less than 604 * a full block boundary, so we set the watermark level to be a full 605 * block. Reads and writes where the block size is less than the 606 * watermark size will work correctly too, no need to change the 607 * watermark for different size blocks. However, 128 is the maximum 608 * allowed for the watermark, so PIO is limitted to 512 byte blocks 609 * (which works fine for SD cards, may be a problem for SDIO some day). 610 * 611 * XXX need named constants for this stuff. 612 */ 613 WR4(sc, SDHC_WTMK_LVL, 0x08800880); 614 615 /* XXX get imx6 clock frequency from CCM */ 616 if (sc->hwtype == HWTYPE_USDHC) { 617 sc->baseclk_hz = 200000000; 618 } else if (sc->hwtype == HWTYPE_ESDHC) { 619 sc->baseclk_hz = imx51_get_clock(IMX51CLK_PERCLK_ROOT); 620 } 621 622 sdhci_init_slot(dev, &sc->slot, 0); 623 624 bus_generic_probe(dev); 625 bus_generic_attach(dev); 626 627 sdhci_start_slot(&sc->slot); 628 629 return (0); 630 631fail: 632 if (sc->intr_cookie) 633 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 634 if (sc->irq_res) 635 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 636 if (sc->mem_res) 637 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 638 639 return (err); 640} 641 642static int 643imx_sdhci_probe(device_t dev) 644{ 645 646 if (!ofw_bus_status_okay(dev)) 647 return (ENXIO); 648 649 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 650 case HWTYPE_ESDHC: 651 device_set_desc(dev, "Freescale eSDHC controller"); 652 return (BUS_PROBE_DEFAULT); 653 case HWTYPE_USDHC: 654 device_set_desc(dev, "Freescale uSDHC controller"); 655 return (BUS_PROBE_DEFAULT); 656 default: 657 break; 658 } 659 return (ENXIO); 660} 661 662static device_method_t imx_sdhci_methods[] = { 663 /* Device interface */ 664 DEVMETHOD(device_probe, imx_sdhci_probe), 665 DEVMETHOD(device_attach, imx_sdhci_attach), 666 DEVMETHOD(device_detach, imx_sdhci_detach), 667 668 /* Bus interface */ 669 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 670 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 671 DEVMETHOD(bus_print_child, bus_generic_print_child), 672 673 /* MMC bridge interface */ 674 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 675 DEVMETHOD(mmcbr_request, sdhci_generic_request), 676 DEVMETHOD(mmcbr_get_ro, imx_sdhci_get_ro), 677 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 678 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 679 680 /* SDHCI registers accessors */ 681 DEVMETHOD(sdhci_read_1, imx_sdhci_read_1), 682 DEVMETHOD(sdhci_read_2, imx_sdhci_read_2), 683 DEVMETHOD(sdhci_read_4, imx_sdhci_read_4), 684 DEVMETHOD(sdhci_read_multi_4, imx_sdhci_read_multi_4), 685 DEVMETHOD(sdhci_write_1, imx_sdhci_write_1), 686 DEVMETHOD(sdhci_write_2, imx_sdhci_write_2), 687 DEVMETHOD(sdhci_write_4, imx_sdhci_write_4), 688 DEVMETHOD(sdhci_write_multi_4, imx_sdhci_write_multi_4), 689 690 { 0, 0 } 691}; 692 693static devclass_t imx_sdhci_devclass; 694 695static driver_t imx_sdhci_driver = { 696 "sdhci_imx", 697 imx_sdhci_methods, 698 sizeof(struct imx_sdhci_softc), 699}; 700 701DRIVER_MODULE(sdhci_imx, simplebus, imx_sdhci_driver, imx_sdhci_devclass, 0, 0); 702MODULE_DEPEND(sdhci_imx, sdhci, 1, 1, 1); 703 704