omap4_mp.c revision 266203
1296341Sdelphij/*- 2238405Sjkim * Copyright (c) 2012 Olivier Houchard. All rights reserved. 3238405Sjkim * 4238405Sjkim * Redistribution and use in source and binary forms, with or without 5238405Sjkim * modification, are permitted provided that the following conditions 6238405Sjkim * are met: 7238405Sjkim * 1. Redistributions of source code must retain the above copyright 8238405Sjkim * notice, this list of conditions and the following disclaimer. 9238405Sjkim * 2. Redistributions in binary form must reproduce the above copyright 10238405Sjkim * notice, this list of conditions and the following disclaimer in the 11238405Sjkim * documentation and/or other materials provided with the distribution. 12238405Sjkim * 13238405Sjkim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14238405Sjkim * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15238405Sjkim * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16238405Sjkim * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17238405Sjkim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18238405Sjkim * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19238405Sjkim * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20238405Sjkim * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21238405Sjkim * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22238405Sjkim * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23238405Sjkim */ 24238405Sjkim 25238405Sjkim#include <sys/cdefs.h> 26238405Sjkim__FBSDID("$FreeBSD: stable/10/sys/arm/ti/omap4/omap4_mp.c 266203 2014-05-16 00:14:50Z ian $"); 27238405Sjkim#include <sys/param.h> 28238405Sjkim#include <sys/systm.h> 29238405Sjkim#include <sys/bus.h> 30238405Sjkim#include <sys/lock.h> 31238405Sjkim#include <sys/mutex.h> 32238405Sjkim#include <sys/smp.h> 33238405Sjkim 34238405Sjkim#include <machine/smp.h> 35238405Sjkim#include <machine/fdt.h> 36238405Sjkim#include <machine/intr.h> 37238405Sjkim 38238405Sjkim#include <arm/ti/ti_smc.h> 39238405Sjkim#include <arm/ti/omap4/omap4_smc.h> 40238405Sjkim 41279264Sdelphijvoid 42279264Sdelphijplatform_mp_init_secondary(void) 43238405Sjkim{ 44238405Sjkim gic_init_secondary(); 45238405Sjkim} 46238405Sjkim 47238405Sjkimvoid 48238405Sjkimplatform_mp_setmaxid(void) 49238405Sjkim{ 50238405Sjkim 51238405Sjkim mp_maxid = 1; 52238405Sjkim} 53279264Sdelphij 54279264Sdelphijint 55279264Sdelphijplatform_mp_probe(void) 56238405Sjkim{ 57279264Sdelphij 58279264Sdelphij mp_ncpus = 2; 59279264Sdelphij return (1); 60279264Sdelphij} 61279264Sdelphij 62279264Sdelphijvoid 63238405Sjkimplatform_mp_start_ap(void) 64279264Sdelphij{ 65279264Sdelphij bus_addr_t scu_addr; 66279264Sdelphij 67279264Sdelphij if (bus_space_map(fdtbus_bs_tag, 0x48240000, 0x1000, 0, &scu_addr) != 0) 68279264Sdelphij panic("Couldn't map the SCU\n"); 69238405Sjkim /* Enable the SCU */ 70279264Sdelphij *(volatile unsigned int *)scu_addr |= 1; 71238405Sjkim //*(volatile unsigned int *)(scu_addr + 0x30) |= 1; 72238405Sjkim cpu_idcache_wbinv_all(); 73238405Sjkim cpu_l2cache_wbinv_all(); 74238405Sjkim ti_smc0(0x200, 0xfffffdff, MODIFY_AUX_CORE_0); 75238405Sjkim ti_smc0(pmap_kextract((vm_offset_t)mpentry), 0, WRITE_AUX_CORE_1); 76238405Sjkim armv7_sev(); 77238405Sjkim bus_space_unmap(fdtbus_bs_tag, scu_addr, 0x1000); 78238405Sjkim} 79238405Sjkim 80238405Sjkimvoid 81238405Sjkimplatform_ipi_send(cpuset_t cpus, u_int ipi) 82238405Sjkim{ 83238405Sjkim pic_ipi_send(cpus, ipi); 84238405Sjkim} 85238405Sjkim