pmap-v6.c revision 266160
1/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2/*- 3 * Copyright 2011 Semihalf 4 * Copyright 2004 Olivier Houchard. 5 * Copyright 2003 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Steve C. Woodford for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * From: FreeBSD: src/sys/arm/arm/pmap.c,v 1.113 2009/07/24 13:50:29 39 */ 40 41/*- 42 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 43 * Copyright (c) 2001 Richard Earnshaw 44 * Copyright (c) 2001-2002 Christopher Gilbert 45 * All rights reserved. 46 * 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the company nor the name of the author may be used to 53 * endorse or promote products derived from this software without specific 54 * prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 57 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 58 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 60 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 61 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 66 * SUCH DAMAGE. 67 */ 68/*- 69 * Copyright (c) 1999 The NetBSD Foundation, Inc. 70 * All rights reserved. 71 * 72 * This code is derived from software contributed to The NetBSD Foundation 73 * by Charles M. Hannum. 74 * 75 * Redistribution and use in source and binary forms, with or without 76 * modification, are permitted provided that the following conditions 77 * are met: 78 * 1. Redistributions of source code must retain the above copyright 79 * notice, this list of conditions and the following disclaimer. 80 * 2. Redistributions in binary form must reproduce the above copyright 81 * notice, this list of conditions and the following disclaimer in the 82 * documentation and/or other materials provided with the distribution. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 85 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 86 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 87 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 88 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 89 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 90 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 91 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 92 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 93 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 94 * POSSIBILITY OF SUCH DAMAGE. 95 */ 96 97/*- 98 * Copyright (c) 1994-1998 Mark Brinicombe. 99 * Copyright (c) 1994 Brini. 100 * All rights reserved. 101 * 102 * This code is derived from software written for Brini by Mark Brinicombe 103 * 104 * Redistribution and use in source and binary forms, with or without 105 * modification, are permitted provided that the following conditions 106 * are met: 107 * 1. Redistributions of source code must retain the above copyright 108 * notice, this list of conditions and the following disclaimer. 109 * 2. Redistributions in binary form must reproduce the above copyright 110 * notice, this list of conditions and the following disclaimer in the 111 * documentation and/or other materials provided with the distribution. 112 * 3. All advertising materials mentioning features or use of this software 113 * must display the following acknowledgement: 114 * This product includes software developed by Mark Brinicombe. 115 * 4. The name of the author may not be used to endorse or promote products 116 * derived from this software without specific prior written permission. 117 * 118 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 119 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 120 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 121 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 122 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 123 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 124 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 125 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 126 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 127 * 128 * RiscBSD kernel project 129 * 130 * pmap.c 131 * 132 * Machine dependant vm stuff 133 * 134 * Created : 20/09/94 135 */ 136 137/* 138 * Special compilation symbols 139 * PMAP_DEBUG - Build in pmap_debug_level code 140 * 141 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c 142*/ 143/* Include header files */ 144 145#include "opt_vm.h" 146#include "opt_pmap.h" 147 148#include <sys/cdefs.h> 149__FBSDID("$FreeBSD: stable/10/sys/arm/arm/pmap-v6.c 266160 2014-05-15 17:30:16Z ian $"); 150#include <sys/param.h> 151#include <sys/systm.h> 152#include <sys/kernel.h> 153#include <sys/ktr.h> 154#include <sys/lock.h> 155#include <sys/proc.h> 156#include <sys/malloc.h> 157#include <sys/msgbuf.h> 158#include <sys/mutex.h> 159#include <sys/vmmeter.h> 160#include <sys/mman.h> 161#include <sys/rwlock.h> 162#include <sys/smp.h> 163#include <sys/sched.h> 164#include <sys/sysctl.h> 165 166#include <vm/vm.h> 167#include <vm/vm_param.h> 168#include <vm/uma.h> 169#include <vm/pmap.h> 170#include <vm/vm_kern.h> 171#include <vm/vm_object.h> 172#include <vm/vm_map.h> 173#include <vm/vm_page.h> 174#include <vm/vm_pageout.h> 175#include <vm/vm_extern.h> 176#include <vm/vm_reserv.h> 177 178#include <machine/md_var.h> 179#include <machine/cpu.h> 180#include <machine/cpufunc.h> 181#include <machine/pcb.h> 182 183#ifdef DEBUG 184extern int last_fault_code; 185#endif 186 187#ifdef PMAP_DEBUG 188#define PDEBUG(_lev_,_stat_) \ 189 if (pmap_debug_level >= (_lev_)) \ 190 ((_stat_)) 191#define dprintf printf 192 193int pmap_debug_level = 0; 194#define PMAP_INLINE 195#else /* PMAP_DEBUG */ 196#define PDEBUG(_lev_,_stat_) /* Nothing */ 197#define dprintf(x, arg...) 198#define PMAP_INLINE __inline 199#endif /* PMAP_DEBUG */ 200 201#ifdef PV_STATS 202#define PV_STAT(x) do { x ; } while (0) 203#else 204#define PV_STAT(x) do { } while (0) 205#endif 206 207#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 208 209#ifdef ARM_L2_PIPT 210#define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((pa), (size)) 211#define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((pa), (size)) 212#else 213#define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((va), (size)) 214#define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((va), (size)) 215#endif 216 217extern struct pv_addr systempage; 218 219/* 220 * Internal function prototypes 221 */ 222 223static PMAP_INLINE 224struct pv_entry *pmap_find_pv(struct md_page *, pmap_t, vm_offset_t); 225static void pmap_free_pv_chunk(struct pv_chunk *pc); 226static void pmap_free_pv_entry(pmap_t pmap, pv_entry_t pv); 227static pv_entry_t pmap_get_pv_entry(pmap_t pmap, boolean_t try); 228static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap); 229static boolean_t pmap_pv_insert_section(pmap_t, vm_offset_t, 230 vm_paddr_t); 231static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vm_offset_t); 232static int pmap_pvh_wired_mappings(struct md_page *, int); 233 234static void pmap_enter_locked(pmap_t, vm_offset_t, vm_prot_t, 235 vm_page_t, vm_prot_t, boolean_t, int); 236static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va); 237static void pmap_alloc_l1(pmap_t); 238static void pmap_free_l1(pmap_t); 239 240static void pmap_map_section(pmap_t, vm_offset_t, vm_offset_t, 241 vm_prot_t, boolean_t); 242static void pmap_promote_section(pmap_t, vm_offset_t); 243static boolean_t pmap_demote_section(pmap_t, vm_offset_t); 244static boolean_t pmap_enter_section(pmap_t, vm_offset_t, vm_page_t, 245 vm_prot_t); 246static void pmap_remove_section(pmap_t, vm_offset_t); 247 248static int pmap_clearbit(struct vm_page *, u_int); 249 250static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 251static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 252static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 253static vm_offset_t kernel_pt_lookup(vm_paddr_t); 254 255static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 256 257vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 258vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 259vm_offset_t pmap_curmaxkvaddr; 260vm_paddr_t kernel_l1pa; 261 262vm_offset_t kernel_vm_end = 0; 263 264vm_offset_t vm_max_kernel_address; 265 266struct pmap kernel_pmap_store; 267 268static pt_entry_t *csrc_pte, *cdst_pte; 269static vm_offset_t csrcp, cdstp; 270static struct mtx cmtx; 271 272static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 273/* 274 * These routines are called when the CPU type is identified to set up 275 * the PTE prototypes, cache modes, etc. 276 * 277 * The variables are always here, just in case LKMs need to reference 278 * them (though, they shouldn't). 279 */ 280static void pmap_set_prot(pt_entry_t *pte, vm_prot_t prot, uint8_t user); 281pt_entry_t pte_l1_s_cache_mode; 282pt_entry_t pte_l1_s_cache_mode_pt; 283 284pt_entry_t pte_l2_l_cache_mode; 285pt_entry_t pte_l2_l_cache_mode_pt; 286 287pt_entry_t pte_l2_s_cache_mode; 288pt_entry_t pte_l2_s_cache_mode_pt; 289 290struct msgbuf *msgbufp = 0; 291 292/* 293 * Crashdump maps. 294 */ 295static caddr_t crashdumpmap; 296 297extern void bcopy_page(vm_offset_t, vm_offset_t); 298extern void bzero_page(vm_offset_t); 299 300char *_tmppt; 301 302/* 303 * Metadata for L1 translation tables. 304 */ 305struct l1_ttable { 306 /* Entry on the L1 Table list */ 307 SLIST_ENTRY(l1_ttable) l1_link; 308 309 /* Entry on the L1 Least Recently Used list */ 310 TAILQ_ENTRY(l1_ttable) l1_lru; 311 312 /* Track how many domains are allocated from this L1 */ 313 volatile u_int l1_domain_use_count; 314 315 /* 316 * A free-list of domain numbers for this L1. 317 * We avoid using ffs() and a bitmap to track domains since ffs() 318 * is slow on ARM. 319 */ 320 u_int8_t l1_domain_first; 321 u_int8_t l1_domain_free[PMAP_DOMAINS]; 322 323 /* Physical address of this L1 page table */ 324 vm_paddr_t l1_physaddr; 325 326 /* KVA of this L1 page table */ 327 pd_entry_t *l1_kva; 328}; 329 330/* 331 * Convert a virtual address into its L1 table index. That is, the 332 * index used to locate the L2 descriptor table pointer in an L1 table. 333 * This is basically used to index l1->l1_kva[]. 334 * 335 * Each L2 descriptor table represents 1MB of VA space. 336 */ 337#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 338 339/* 340 * L1 Page Tables are tracked using a Least Recently Used list. 341 * - New L1s are allocated from the HEAD. 342 * - Freed L1s are added to the TAIl. 343 * - Recently accessed L1s (where an 'access' is some change to one of 344 * the userland pmaps which owns this L1) are moved to the TAIL. 345 */ 346static TAILQ_HEAD(, l1_ttable) l1_lru_list; 347/* 348 * A list of all L1 tables 349 */ 350static SLIST_HEAD(, l1_ttable) l1_list; 351static struct mtx l1_lru_lock; 352 353/* 354 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 355 * 356 * This is normally 16MB worth L2 page descriptors for any given pmap. 357 * Reference counts are maintained for L2 descriptors so they can be 358 * freed when empty. 359 */ 360struct l2_dtable { 361 /* The number of L2 page descriptors allocated to this l2_dtable */ 362 u_int l2_occupancy; 363 364 /* List of L2 page descriptors */ 365 struct l2_bucket { 366 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 367 vm_paddr_t l2b_phys; /* Physical address of same */ 368 u_short l2b_l1idx; /* This L2 table's L1 index */ 369 u_short l2b_occupancy; /* How many active descriptors */ 370 } l2_bucket[L2_BUCKET_SIZE]; 371}; 372 373/* pmap_kenter_internal flags */ 374#define KENTER_CACHE 0x1 375#define KENTER_USER 0x2 376 377/* 378 * Given an L1 table index, calculate the corresponding l2_dtable index 379 * and bucket index within the l2_dtable. 380 */ 381#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 382 (L2_SIZE - 1)) 383#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 384 385/* 386 * Given a virtual address, this macro returns the 387 * virtual address required to drop into the next L2 bucket. 388 */ 389#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 390 391/* 392 * We try to map the page tables write-through, if possible. However, not 393 * all CPUs have a write-through cache mode, so on those we have to sync 394 * the cache when we frob page tables. 395 * 396 * We try to evaluate this at compile time, if possible. However, it's 397 * not always possible to do that, hence this run-time var. 398 */ 399int pmap_needs_pte_sync; 400 401/* 402 * Macro to determine if a mapping might be resident in the 403 * instruction cache and/or TLB 404 */ 405#define PTE_BEEN_EXECD(pte) (L2_S_EXECUTABLE(pte) && L2_S_REFERENCED(pte)) 406 407/* 408 * Macro to determine if a mapping might be resident in the 409 * data cache and/or TLB 410 */ 411#define PTE_BEEN_REFD(pte) (L2_S_REFERENCED(pte)) 412 413#ifndef PMAP_SHPGPERPROC 414#define PMAP_SHPGPERPROC 200 415#endif 416 417#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 418 curproc->p_vmspace->vm_map.pmap == (pm)) 419 420/* 421 * Data for the pv entry allocation mechanism 422 */ 423static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 424static int pv_entry_count, pv_entry_max, pv_entry_high_water; 425static struct md_page *pv_table; 426static int shpgperproc = PMAP_SHPGPERPROC; 427 428struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 429int pv_maxchunks; /* How many chunks we have KVA for */ 430vm_offset_t pv_vafree; /* Freelist stored in the PTE */ 431 432static __inline struct pv_chunk * 433pv_to_chunk(pv_entry_t pv) 434{ 435 436 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 437} 438 439#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 440 441CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 442CTASSERT(_NPCM == 8); 443CTASSERT(_NPCPV == 252); 444 445#define PC_FREE0_6 0xfffffffful /* Free values for index 0 through 6 */ 446#define PC_FREE7 0x0ffffffful /* Free values for index 7 */ 447 448static const uint32_t pc_freemask[_NPCM] = { 449 PC_FREE0_6, PC_FREE0_6, PC_FREE0_6, 450 PC_FREE0_6, PC_FREE0_6, PC_FREE0_6, 451 PC_FREE0_6, PC_FREE7 452}; 453 454static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 455 456/* Superpages utilization enabled = 1 / disabled = 0 */ 457static int sp_enabled = 0; 458SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN, &sp_enabled, 0, 459 "Are large page mappings enabled?"); 460 461SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 462 "Current number of pv entries"); 463 464#ifdef PV_STATS 465static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 466 467SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 468 "Current number of pv entry chunks"); 469SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 470 "Current number of pv entry chunks allocated"); 471SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 472 "Current number of pv entry chunks frees"); 473SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 474 "Number of times tried to get a chunk page but failed."); 475 476static long pv_entry_frees, pv_entry_allocs; 477static int pv_entry_spare; 478 479SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 480 "Current number of pv entry frees"); 481SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 482 "Current number of pv entry allocs"); 483SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 484 "Current number of spare pv entries"); 485#endif 486 487uma_zone_t l2zone; 488static uma_zone_t l2table_zone; 489static vm_offset_t pmap_kernel_l2dtable_kva; 490static vm_offset_t pmap_kernel_l2ptp_kva; 491static vm_paddr_t pmap_kernel_l2ptp_phys; 492static struct rwlock pvh_global_lock; 493 494int l1_mem_types[] = { 495 ARM_L1S_STRONG_ORD, 496 ARM_L1S_DEVICE_NOSHARE, 497 ARM_L1S_DEVICE_SHARE, 498 ARM_L1S_NRML_NOCACHE, 499 ARM_L1S_NRML_IWT_OWT, 500 ARM_L1S_NRML_IWB_OWB, 501 ARM_L1S_NRML_IWBA_OWBA 502}; 503 504int l2l_mem_types[] = { 505 ARM_L2L_STRONG_ORD, 506 ARM_L2L_DEVICE_NOSHARE, 507 ARM_L2L_DEVICE_SHARE, 508 ARM_L2L_NRML_NOCACHE, 509 ARM_L2L_NRML_IWT_OWT, 510 ARM_L2L_NRML_IWB_OWB, 511 ARM_L2L_NRML_IWBA_OWBA 512}; 513 514int l2s_mem_types[] = { 515 ARM_L2S_STRONG_ORD, 516 ARM_L2S_DEVICE_NOSHARE, 517 ARM_L2S_DEVICE_SHARE, 518 ARM_L2S_NRML_NOCACHE, 519 ARM_L2S_NRML_IWT_OWT, 520 ARM_L2S_NRML_IWB_OWB, 521 ARM_L2S_NRML_IWBA_OWBA 522}; 523 524/* 525 * This list exists for the benefit of pmap_map_chunk(). It keeps track 526 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 527 * find them as necessary. 528 * 529 * Note that the data on this list MUST remain valid after initarm() returns, 530 * as pmap_bootstrap() uses it to contruct L2 table metadata. 531 */ 532SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 533 534static void 535pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 536{ 537 int i; 538 539 l1->l1_kva = l1pt; 540 l1->l1_domain_use_count = 0; 541 l1->l1_domain_first = 0; 542 543 for (i = 0; i < PMAP_DOMAINS; i++) 544 l1->l1_domain_free[i] = i + 1; 545 546 /* 547 * Copy the kernel's L1 entries to each new L1. 548 */ 549 if (l1pt != pmap_kernel()->pm_l1->l1_kva) 550 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 551 552 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 553 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 554 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 555 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 556} 557 558static vm_offset_t 559kernel_pt_lookup(vm_paddr_t pa) 560{ 561 struct pv_addr *pv; 562 563 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 564 if (pv->pv_pa == pa) 565 return (pv->pv_va); 566 } 567 return (0); 568} 569 570void 571pmap_pte_init_mmu_v6(void) 572{ 573 574 if (PTE_PAGETABLE >= 3) 575 pmap_needs_pte_sync = 1; 576 pte_l1_s_cache_mode = l1_mem_types[PTE_CACHE]; 577 pte_l2_l_cache_mode = l2l_mem_types[PTE_CACHE]; 578 pte_l2_s_cache_mode = l2s_mem_types[PTE_CACHE]; 579 580 pte_l1_s_cache_mode_pt = l1_mem_types[PTE_PAGETABLE]; 581 pte_l2_l_cache_mode_pt = l2l_mem_types[PTE_PAGETABLE]; 582 pte_l2_s_cache_mode_pt = l2s_mem_types[PTE_PAGETABLE]; 583 584} 585 586/* 587 * Allocate an L1 translation table for the specified pmap. 588 * This is called at pmap creation time. 589 */ 590static void 591pmap_alloc_l1(pmap_t pmap) 592{ 593 struct l1_ttable *l1; 594 u_int8_t domain; 595 596 /* 597 * Remove the L1 at the head of the LRU list 598 */ 599 mtx_lock(&l1_lru_lock); 600 l1 = TAILQ_FIRST(&l1_lru_list); 601 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 602 603 /* 604 * Pick the first available domain number, and update 605 * the link to the next number. 606 */ 607 domain = l1->l1_domain_first; 608 l1->l1_domain_first = l1->l1_domain_free[domain]; 609 610 /* 611 * If there are still free domain numbers in this L1, 612 * put it back on the TAIL of the LRU list. 613 */ 614 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 615 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 616 617 mtx_unlock(&l1_lru_lock); 618 619 /* 620 * Fix up the relevant bits in the pmap structure 621 */ 622 pmap->pm_l1 = l1; 623 pmap->pm_domain = domain + 1; 624} 625 626/* 627 * Free an L1 translation table. 628 * This is called at pmap destruction time. 629 */ 630static void 631pmap_free_l1(pmap_t pmap) 632{ 633 struct l1_ttable *l1 = pmap->pm_l1; 634 635 mtx_lock(&l1_lru_lock); 636 637 /* 638 * If this L1 is currently on the LRU list, remove it. 639 */ 640 if (l1->l1_domain_use_count < PMAP_DOMAINS) 641 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 642 643 /* 644 * Free up the domain number which was allocated to the pmap 645 */ 646 l1->l1_domain_free[pmap->pm_domain - 1] = l1->l1_domain_first; 647 l1->l1_domain_first = pmap->pm_domain - 1; 648 l1->l1_domain_use_count--; 649 650 /* 651 * The L1 now must have at least 1 free domain, so add 652 * it back to the LRU list. If the use count is zero, 653 * put it at the head of the list, otherwise it goes 654 * to the tail. 655 */ 656 if (l1->l1_domain_use_count == 0) { 657 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 658 } else 659 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 660 661 mtx_unlock(&l1_lru_lock); 662} 663 664/* 665 * Returns a pointer to the L2 bucket associated with the specified pmap 666 * and VA, or NULL if no L2 bucket exists for the address. 667 */ 668static PMAP_INLINE struct l2_bucket * 669pmap_get_l2_bucket(pmap_t pmap, vm_offset_t va) 670{ 671 struct l2_dtable *l2; 672 struct l2_bucket *l2b; 673 u_short l1idx; 674 675 l1idx = L1_IDX(va); 676 677 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL || 678 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 679 return (NULL); 680 681 return (l2b); 682} 683 684/* 685 * Returns a pointer to the L2 bucket associated with the specified pmap 686 * and VA. 687 * 688 * If no L2 bucket exists, perform the necessary allocations to put an L2 689 * bucket/page table in place. 690 * 691 * Note that if a new L2 bucket/page was allocated, the caller *must* 692 * increment the bucket occupancy counter appropriately *before* 693 * releasing the pmap's lock to ensure no other thread or cpu deallocates 694 * the bucket/page in the meantime. 695 */ 696static struct l2_bucket * 697pmap_alloc_l2_bucket(pmap_t pmap, vm_offset_t va) 698{ 699 struct l2_dtable *l2; 700 struct l2_bucket *l2b; 701 u_short l1idx; 702 703 l1idx = L1_IDX(va); 704 705 PMAP_ASSERT_LOCKED(pmap); 706 rw_assert(&pvh_global_lock, RA_WLOCKED); 707 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 708 /* 709 * No mapping at this address, as there is 710 * no entry in the L1 table. 711 * Need to allocate a new l2_dtable. 712 */ 713 PMAP_UNLOCK(pmap); 714 rw_wunlock(&pvh_global_lock); 715 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) { 716 rw_wlock(&pvh_global_lock); 717 PMAP_LOCK(pmap); 718 return (NULL); 719 } 720 rw_wlock(&pvh_global_lock); 721 PMAP_LOCK(pmap); 722 if (pmap->pm_l2[L2_IDX(l1idx)] != NULL) { 723 /* 724 * Someone already allocated the l2_dtable while 725 * we were doing the same. 726 */ 727 uma_zfree(l2table_zone, l2); 728 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 729 } else { 730 bzero(l2, sizeof(*l2)); 731 /* 732 * Link it into the parent pmap 733 */ 734 pmap->pm_l2[L2_IDX(l1idx)] = l2; 735 } 736 } 737 738 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 739 740 /* 741 * Fetch pointer to the L2 page table associated with the address. 742 */ 743 if (l2b->l2b_kva == NULL) { 744 pt_entry_t *ptep; 745 746 /* 747 * No L2 page table has been allocated. Chances are, this 748 * is because we just allocated the l2_dtable, above. 749 */ 750 PMAP_UNLOCK(pmap); 751 rw_wunlock(&pvh_global_lock); 752 ptep = uma_zalloc(l2zone, M_NOWAIT); 753 rw_wlock(&pvh_global_lock); 754 PMAP_LOCK(pmap); 755 if (l2b->l2b_kva != 0) { 756 /* We lost the race. */ 757 uma_zfree(l2zone, ptep); 758 return (l2b); 759 } 760 l2b->l2b_phys = vtophys(ptep); 761 if (ptep == NULL) { 762 /* 763 * Oops, no more L2 page tables available at this 764 * time. We may need to deallocate the l2_dtable 765 * if we allocated a new one above. 766 */ 767 if (l2->l2_occupancy == 0) { 768 pmap->pm_l2[L2_IDX(l1idx)] = NULL; 769 uma_zfree(l2table_zone, l2); 770 } 771 return (NULL); 772 } 773 774 l2->l2_occupancy++; 775 l2b->l2b_kva = ptep; 776 l2b->l2b_l1idx = l1idx; 777 } 778 779 return (l2b); 780} 781 782static PMAP_INLINE void 783pmap_free_l2_ptp(pt_entry_t *l2) 784{ 785 uma_zfree(l2zone, l2); 786} 787/* 788 * One or more mappings in the specified L2 descriptor table have just been 789 * invalidated. 790 * 791 * Garbage collect the metadata and descriptor table itself if necessary. 792 * 793 * The pmap lock must be acquired when this is called (not necessary 794 * for the kernel pmap). 795 */ 796static void 797pmap_free_l2_bucket(pmap_t pmap, struct l2_bucket *l2b, u_int count) 798{ 799 struct l2_dtable *l2; 800 pd_entry_t *pl1pd, l1pd; 801 pt_entry_t *ptep; 802 u_short l1idx; 803 804 805 /* 806 * Update the bucket's reference count according to how many 807 * PTEs the caller has just invalidated. 808 */ 809 l2b->l2b_occupancy -= count; 810 811 /* 812 * Note: 813 * 814 * Level 2 page tables allocated to the kernel pmap are never freed 815 * as that would require checking all Level 1 page tables and 816 * removing any references to the Level 2 page table. See also the 817 * comment elsewhere about never freeing bootstrap L2 descriptors. 818 * 819 * We make do with just invalidating the mapping in the L2 table. 820 * 821 * This isn't really a big deal in practice and, in fact, leads 822 * to a performance win over time as we don't need to continually 823 * alloc/free. 824 */ 825 if (l2b->l2b_occupancy > 0 || pmap == pmap_kernel()) 826 return; 827 828 /* 829 * There are no more valid mappings in this level 2 page table. 830 * Go ahead and NULL-out the pointer in the bucket, then 831 * free the page table. 832 */ 833 l1idx = l2b->l2b_l1idx; 834 ptep = l2b->l2b_kva; 835 l2b->l2b_kva = NULL; 836 837 pl1pd = &pmap->pm_l1->l1_kva[l1idx]; 838 839 /* 840 * If the L1 slot matches the pmap's domain 841 * number, then invalidate it. 842 */ 843 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 844 if (l1pd == (L1_C_DOM(pmap->pm_domain) | L1_TYPE_C)) { 845 *pl1pd = 0; 846 PTE_SYNC(pl1pd); 847 } 848 849 /* 850 * Release the L2 descriptor table back to the pool cache. 851 */ 852 pmap_free_l2_ptp(ptep); 853 854 /* 855 * Update the reference count in the associated l2_dtable 856 */ 857 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 858 if (--l2->l2_occupancy > 0) 859 return; 860 861 /* 862 * There are no more valid mappings in any of the Level 1 863 * slots managed by this l2_dtable. Go ahead and NULL-out 864 * the pointer in the parent pmap and free the l2_dtable. 865 */ 866 pmap->pm_l2[L2_IDX(l1idx)] = NULL; 867 uma_zfree(l2table_zone, l2); 868} 869 870/* 871 * Pool cache constructors for L2 descriptor tables, metadata and pmap 872 * structures. 873 */ 874static int 875pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 876{ 877 struct l2_bucket *l2b; 878 pt_entry_t *ptep, pte; 879 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 880 881 /* 882 * The mappings for these page tables were initially made using 883 * pmap_kenter() by the pool subsystem. Therefore, the cache- 884 * mode will not be right for page table mappings. To avoid 885 * polluting the pmap_kenter() code with a special case for 886 * page tables, we simply fix up the cache-mode here if it's not 887 * correct. 888 */ 889 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 890 ptep = &l2b->l2b_kva[l2pte_index(va)]; 891 pte = *ptep; 892 893 cpu_idcache_wbinv_range(va, PAGE_SIZE); 894 pmap_l2cache_wbinv_range(va, pte & L2_S_FRAME, PAGE_SIZE); 895 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 896 /* 897 * Page tables must have the cache-mode set to 898 * Write-Thru. 899 */ 900 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 901 PTE_SYNC(ptep); 902 cpu_tlb_flushD_SE(va); 903 cpu_cpwait(); 904 } 905 906 memset(mem, 0, L2_TABLE_SIZE_REAL); 907 return (0); 908} 909 910/* 911 * Modify pte bits for all ptes corresponding to the given physical address. 912 * We use `maskbits' rather than `clearbits' because we're always passing 913 * constants and the latter would require an extra inversion at run-time. 914 */ 915static int 916pmap_clearbit(struct vm_page *m, u_int maskbits) 917{ 918 struct l2_bucket *l2b; 919 struct pv_entry *pv, *pve, *next_pv; 920 struct md_page *pvh; 921 pd_entry_t *pl1pd; 922 pt_entry_t *ptep, npte, opte; 923 pmap_t pmap; 924 vm_offset_t va; 925 u_int oflags; 926 int count = 0; 927 928 rw_wlock(&pvh_global_lock); 929 if ((m->flags & PG_FICTITIOUS) != 0) 930 goto small_mappings; 931 932 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 933 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 934 va = pv->pv_va; 935 pmap = PV_PMAP(pv); 936 PMAP_LOCK(pmap); 937 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 938 KASSERT((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO, 939 ("pmap_clearbit: valid section mapping expected")); 940 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_WRITE)) 941 (void)pmap_demote_section(pmap, va); 942 else if ((maskbits & PVF_REF) && L1_S_REFERENCED(*pl1pd)) { 943 if (pmap_demote_section(pmap, va)) { 944 if ((pv->pv_flags & PVF_WIRED) == 0) { 945 /* 946 * Remove the mapping to a single page 947 * so that a subsequent access may 948 * repromote. Since the underlying 949 * l2_bucket is fully populated, this 950 * removal never frees an entire 951 * l2_bucket. 952 */ 953 va += (VM_PAGE_TO_PHYS(m) & 954 L1_S_OFFSET); 955 l2b = pmap_get_l2_bucket(pmap, va); 956 KASSERT(l2b != NULL, 957 ("pmap_clearbit: no l2 bucket for " 958 "va 0x%#x, pmap 0x%p", va, pmap)); 959 ptep = &l2b->l2b_kva[l2pte_index(va)]; 960 *ptep = 0; 961 PTE_SYNC(ptep); 962 pmap_free_l2_bucket(pmap, l2b, 1); 963 pve = pmap_remove_pv(m, pmap, va); 964 KASSERT(pve != NULL, ("pmap_clearbit: " 965 "no PV entry for managed mapping")); 966 pmap_free_pv_entry(pmap, pve); 967 968 } 969 } 970 } else if ((maskbits & PVF_MOD) && L1_S_WRITABLE(*pl1pd)) { 971 if (pmap_demote_section(pmap, va)) { 972 if ((pv->pv_flags & PVF_WIRED) == 0) { 973 /* 974 * Write protect the mapping to a 975 * single page so that a subsequent 976 * write access may repromote. 977 */ 978 va += (VM_PAGE_TO_PHYS(m) & 979 L1_S_OFFSET); 980 l2b = pmap_get_l2_bucket(pmap, va); 981 KASSERT(l2b != NULL, 982 ("pmap_clearbit: no l2 bucket for " 983 "va 0x%#x, pmap 0x%p", va, pmap)); 984 ptep = &l2b->l2b_kva[l2pte_index(va)]; 985 if ((*ptep & L2_S_PROTO) != 0) { 986 pve = pmap_find_pv(&m->md, 987 pmap, va); 988 KASSERT(pve != NULL, 989 ("pmap_clearbit: no PV " 990 "entry for managed mapping")); 991 pve->pv_flags &= ~PVF_WRITE; 992 *ptep |= L2_APX; 993 PTE_SYNC(ptep); 994 } 995 } 996 } 997 } 998 PMAP_UNLOCK(pmap); 999 } 1000 1001small_mappings: 1002 if (TAILQ_EMPTY(&m->md.pv_list)) { 1003 rw_wunlock(&pvh_global_lock); 1004 return (0); 1005 } 1006 1007 /* 1008 * Loop over all current mappings setting/clearing as appropos 1009 */ 1010 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1011 va = pv->pv_va; 1012 pmap = PV_PMAP(pv); 1013 oflags = pv->pv_flags; 1014 pv->pv_flags &= ~maskbits; 1015 1016 PMAP_LOCK(pmap); 1017 1018 l2b = pmap_get_l2_bucket(pmap, va); 1019 KASSERT(l2b != NULL, ("pmap_clearbit: no l2 bucket for " 1020 "va 0x%#x, pmap 0x%p", va, pmap)); 1021 1022 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1023 npte = opte = *ptep; 1024 1025 if (maskbits & (PVF_WRITE | PVF_MOD)) { 1026 /* make the pte read only */ 1027 npte |= L2_APX; 1028 } 1029 1030 if (maskbits & PVF_REF) { 1031 /* 1032 * Clear referenced flag in PTE so that we 1033 * will take a flag fault the next time the mapping 1034 * is referenced. 1035 */ 1036 npte &= ~L2_S_REF; 1037 } 1038 1039 CTR4(KTR_PMAP,"clearbit: pmap:%p bits:%x pte:%x->%x", 1040 pmap, maskbits, opte, npte); 1041 if (npte != opte) { 1042 count++; 1043 *ptep = npte; 1044 PTE_SYNC(ptep); 1045 /* Flush the TLB entry if a current pmap. */ 1046 if (PTE_BEEN_EXECD(opte)) 1047 cpu_tlb_flushID_SE(pv->pv_va); 1048 else if (PTE_BEEN_REFD(opte)) 1049 cpu_tlb_flushD_SE(pv->pv_va); 1050 } 1051 1052 PMAP_UNLOCK(pmap); 1053 1054 } 1055 1056 if (maskbits & PVF_WRITE) 1057 vm_page_aflag_clear(m, PGA_WRITEABLE); 1058 rw_wunlock(&pvh_global_lock); 1059 return (count); 1060} 1061 1062/* 1063 * main pv_entry manipulation functions: 1064 * pmap_enter_pv: enter a mapping onto a vm_page list 1065 * pmap_remove_pv: remove a mappiing from a vm_page list 1066 * 1067 * NOTE: pmap_enter_pv expects to lock the pvh itself 1068 * pmap_remove_pv expects the caller to lock the pvh before calling 1069 */ 1070 1071/* 1072 * pmap_enter_pv: enter a mapping onto a vm_page's PV list 1073 * 1074 * => caller should hold the proper lock on pvh_global_lock 1075 * => caller should have pmap locked 1076 * => we will (someday) gain the lock on the vm_page's PV list 1077 * => caller should adjust ptp's wire_count before calling 1078 * => caller should not adjust pmap's wire_count 1079 */ 1080static void 1081pmap_enter_pv(struct vm_page *m, struct pv_entry *pve, pmap_t pmap, 1082 vm_offset_t va, u_int flags) 1083{ 1084 1085 rw_assert(&pvh_global_lock, RA_WLOCKED); 1086 1087 PMAP_ASSERT_LOCKED(pmap); 1088 pve->pv_va = va; 1089 pve->pv_flags = flags; 1090 1091 TAILQ_INSERT_HEAD(&m->md.pv_list, pve, pv_list); 1092 if (pve->pv_flags & PVF_WIRED) 1093 ++pmap->pm_stats.wired_count; 1094} 1095 1096/* 1097 * 1098 * pmap_find_pv: Find a pv entry 1099 * 1100 * => caller should hold lock on vm_page 1101 */ 1102static PMAP_INLINE struct pv_entry * 1103pmap_find_pv(struct md_page *md, pmap_t pmap, vm_offset_t va) 1104{ 1105 struct pv_entry *pv; 1106 1107 rw_assert(&pvh_global_lock, RA_WLOCKED); 1108 TAILQ_FOREACH(pv, &md->pv_list, pv_list) 1109 if (pmap == PV_PMAP(pv) && va == pv->pv_va) 1110 break; 1111 1112 return (pv); 1113} 1114 1115/* 1116 * vector_page_setprot: 1117 * 1118 * Manipulate the protection of the vector page. 1119 */ 1120void 1121vector_page_setprot(int prot) 1122{ 1123 struct l2_bucket *l2b; 1124 pt_entry_t *ptep; 1125 1126 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1127 1128 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1129 /* 1130 * Set referenced flag. 1131 * Vectors' page is always desired 1132 * to be allowed to reside in TLB. 1133 */ 1134 *ptep |= L2_S_REF; 1135 1136 pmap_set_prot(ptep, prot|VM_PROT_EXECUTE, 0); 1137 1138 cpu_tlb_flushD_SE(vector_page); 1139 cpu_cpwait(); 1140} 1141 1142static void 1143pmap_set_prot(pt_entry_t *ptep, vm_prot_t prot, uint8_t user) 1144{ 1145 1146 *ptep &= ~(L2_S_PROT_MASK | L2_XN); 1147 1148 if (!(prot & VM_PROT_EXECUTE)) 1149 *ptep |= L2_XN; 1150 1151 /* Set defaults first - kernel read access */ 1152 *ptep |= L2_APX; 1153 *ptep |= L2_S_PROT_R; 1154 /* Now tune APs as desired */ 1155 if (user) 1156 *ptep |= L2_S_PROT_U; 1157 1158 if (prot & VM_PROT_WRITE) 1159 *ptep &= ~(L2_APX); 1160} 1161 1162/* 1163 * pmap_remove_pv: try to remove a mapping from a pv_list 1164 * 1165 * => caller should hold proper lock on pmap_main_lock 1166 * => pmap should be locked 1167 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1168 * => caller should adjust ptp's wire_count and free PTP if needed 1169 * => caller should NOT adjust pmap's wire_count 1170 * => we return the removed pve 1171 */ 1172static struct pv_entry * 1173pmap_remove_pv(struct vm_page *m, pmap_t pmap, vm_offset_t va) 1174{ 1175 struct pv_entry *pve; 1176 1177 rw_assert(&pvh_global_lock, RA_WLOCKED); 1178 PMAP_ASSERT_LOCKED(pmap); 1179 1180 pve = pmap_find_pv(&m->md, pmap, va); /* find corresponding pve */ 1181 if (pve != NULL) { 1182 TAILQ_REMOVE(&m->md.pv_list, pve, pv_list); 1183 if (pve->pv_flags & PVF_WIRED) 1184 --pmap->pm_stats.wired_count; 1185 } 1186 if (TAILQ_EMPTY(&m->md.pv_list)) 1187 vm_page_aflag_clear(m, PGA_WRITEABLE); 1188 1189 return(pve); /* return removed pve */ 1190} 1191 1192/* 1193 * 1194 * pmap_modify_pv: Update pv flags 1195 * 1196 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1197 * => caller should NOT adjust pmap's wire_count 1198 * => we return the old flags 1199 * 1200 * Modify a physical-virtual mapping in the pv table 1201 */ 1202static u_int 1203pmap_modify_pv(struct vm_page *m, pmap_t pmap, vm_offset_t va, 1204 u_int clr_mask, u_int set_mask) 1205{ 1206 struct pv_entry *npv; 1207 u_int flags, oflags; 1208 1209 PMAP_ASSERT_LOCKED(pmap); 1210 rw_assert(&pvh_global_lock, RA_WLOCKED); 1211 if ((npv = pmap_find_pv(&m->md, pmap, va)) == NULL) 1212 return (0); 1213 1214 /* 1215 * There is at least one VA mapping this page. 1216 */ 1217 oflags = npv->pv_flags; 1218 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1219 1220 if ((flags ^ oflags) & PVF_WIRED) { 1221 if (flags & PVF_WIRED) 1222 ++pmap->pm_stats.wired_count; 1223 else 1224 --pmap->pm_stats.wired_count; 1225 } 1226 1227 return (oflags); 1228} 1229 1230/* Function to set the debug level of the pmap code */ 1231#ifdef PMAP_DEBUG 1232void 1233pmap_debug(int level) 1234{ 1235 pmap_debug_level = level; 1236 dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1237} 1238#endif /* PMAP_DEBUG */ 1239 1240void 1241pmap_pinit0(struct pmap *pmap) 1242{ 1243 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1244 1245 bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1246 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1247 PMAP_LOCK_INIT(pmap); 1248 TAILQ_INIT(&pmap->pm_pvchunk); 1249} 1250 1251/* 1252 * Initialize a vm_page's machine-dependent fields. 1253 */ 1254void 1255pmap_page_init(vm_page_t m) 1256{ 1257 1258 TAILQ_INIT(&m->md.pv_list); 1259 m->md.pv_memattr = VM_MEMATTR_DEFAULT; 1260} 1261 1262static vm_offset_t 1263pmap_ptelist_alloc(vm_offset_t *head) 1264{ 1265 pt_entry_t *pte; 1266 vm_offset_t va; 1267 1268 va = *head; 1269 if (va == 0) 1270 return (va); /* Out of memory */ 1271 pte = vtopte(va); 1272 *head = *pte; 1273 if ((*head & L2_TYPE_MASK) != L2_TYPE_INV) 1274 panic("%s: va is not L2_TYPE_INV!", __func__); 1275 *pte = 0; 1276 return (va); 1277} 1278 1279static void 1280pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 1281{ 1282 pt_entry_t *pte; 1283 1284 if ((va & L2_TYPE_MASK) != L2_TYPE_INV) 1285 panic("%s: freeing va that is not L2_TYPE INV!", __func__); 1286 pte = vtopte(va); 1287 *pte = *head; /* virtual! L2_TYPE is L2_TYPE_INV though */ 1288 *head = va; 1289} 1290 1291static void 1292pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 1293{ 1294 int i; 1295 vm_offset_t va; 1296 1297 *head = 0; 1298 for (i = npages - 1; i >= 0; i--) { 1299 va = (vm_offset_t)base + i * PAGE_SIZE; 1300 pmap_ptelist_free(head, va); 1301 } 1302} 1303 1304/* 1305 * Initialize the pmap module. 1306 * Called by vm_init, to initialize any structures that the pmap 1307 * system needs to map virtual memory. 1308 */ 1309void 1310pmap_init(void) 1311{ 1312 vm_size_t s; 1313 int i, pv_npg; 1314 1315 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1316 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1317 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL, 1318 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1319 1320 /* 1321 * Are large page mappings supported and enabled? 1322 */ 1323 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled); 1324 if (sp_enabled) { 1325 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1326 ("pmap_init: can't assign to pagesizes[1]")); 1327 pagesizes[1] = NBPDR; 1328 } 1329 1330 /* 1331 * Calculate the size of the pv head table for superpages. 1332 */ 1333 for (i = 0; phys_avail[i + 1]; i += 2); 1334 pv_npg = round_1mpage(phys_avail[(i - 2) + 1]) / NBPDR; 1335 1336 /* 1337 * Allocate memory for the pv head table for superpages. 1338 */ 1339 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 1340 s = round_page(s); 1341 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 1342 M_WAITOK | M_ZERO); 1343 for (i = 0; i < pv_npg; i++) 1344 TAILQ_INIT(&pv_table[i].pv_list); 1345 1346 /* 1347 * Initialize the address space for the pv chunks. 1348 */ 1349 1350 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1351 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1352 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1353 pv_entry_max = roundup(pv_entry_max, _NPCPV); 1354 pv_entry_high_water = 9 * (pv_entry_max / 10); 1355 1356 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 1357 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 1358 1359 if (pv_chunkbase == NULL) 1360 panic("pmap_init: not enough kvm for pv chunks"); 1361 1362 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 1363 1364 /* 1365 * Now it is safe to enable pv_table recording. 1366 */ 1367 PDEBUG(1, printf("pmap_init: done!\n")); 1368} 1369 1370SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 1371 "Max number of PV entries"); 1372SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 1373 "Page share factor per proc"); 1374 1375static SYSCTL_NODE(_vm_pmap, OID_AUTO, section, CTLFLAG_RD, 0, 1376 "1MB page mapping counters"); 1377 1378static u_long pmap_section_demotions; 1379SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, demotions, CTLFLAG_RD, 1380 &pmap_section_demotions, 0, "1MB page demotions"); 1381 1382static u_long pmap_section_mappings; 1383SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, mappings, CTLFLAG_RD, 1384 &pmap_section_mappings, 0, "1MB page mappings"); 1385 1386static u_long pmap_section_p_failures; 1387SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, p_failures, CTLFLAG_RD, 1388 &pmap_section_p_failures, 0, "1MB page promotion failures"); 1389 1390static u_long pmap_section_promotions; 1391SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, promotions, CTLFLAG_RD, 1392 &pmap_section_promotions, 0, "1MB page promotions"); 1393 1394int 1395pmap_fault_fixup(pmap_t pmap, vm_offset_t va, vm_prot_t ftype, int user) 1396{ 1397 struct l2_dtable *l2; 1398 struct l2_bucket *l2b; 1399 pd_entry_t *pl1pd, l1pd; 1400 pt_entry_t *ptep, pte; 1401 vm_paddr_t pa; 1402 u_int l1idx; 1403 int rv = 0; 1404 1405 l1idx = L1_IDX(va); 1406 rw_wlock(&pvh_global_lock); 1407 PMAP_LOCK(pmap); 1408 /* 1409 * Check and possibly fix-up L1 section mapping 1410 * only when superpage mappings are enabled to speed up. 1411 */ 1412 if (sp_enabled) { 1413 pl1pd = &pmap->pm_l1->l1_kva[l1idx]; 1414 l1pd = *pl1pd; 1415 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) { 1416 /* Catch an access to the vectors section */ 1417 if (l1idx == L1_IDX(vector_page)) 1418 goto out; 1419 /* 1420 * Stay away from the kernel mappings. 1421 * None of them should fault from L1 entry. 1422 */ 1423 if (pmap == pmap_kernel()) 1424 goto out; 1425 /* 1426 * Catch a forbidden userland access 1427 */ 1428 if (user && !(l1pd & L1_S_PROT_U)) 1429 goto out; 1430 /* 1431 * Superpage is always either mapped read only 1432 * or it is modified and permitted to be written 1433 * by default. Therefore, process only reference 1434 * flag fault and demote page in case of write fault. 1435 */ 1436 if ((ftype & VM_PROT_WRITE) && !L1_S_WRITABLE(l1pd) && 1437 L1_S_REFERENCED(l1pd)) { 1438 (void)pmap_demote_section(pmap, va); 1439 goto out; 1440 } else if (!L1_S_REFERENCED(l1pd)) { 1441 /* Mark the page "referenced" */ 1442 *pl1pd = l1pd | L1_S_REF; 1443 PTE_SYNC(pl1pd); 1444 goto l1_section_out; 1445 } else 1446 goto out; 1447 } 1448 } 1449 /* 1450 * If there is no l2_dtable for this address, then the process 1451 * has no business accessing it. 1452 * 1453 * Note: This will catch userland processes trying to access 1454 * kernel addresses. 1455 */ 1456 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 1457 if (l2 == NULL) 1458 goto out; 1459 1460 /* 1461 * Likewise if there is no L2 descriptor table 1462 */ 1463 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1464 if (l2b->l2b_kva == NULL) 1465 goto out; 1466 1467 /* 1468 * Check the PTE itself. 1469 */ 1470 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1471 pte = *ptep; 1472 if (pte == 0) 1473 goto out; 1474 1475 /* 1476 * Catch a userland access to the vector page mapped at 0x0 1477 */ 1478 if (user && !(pte & L2_S_PROT_U)) 1479 goto out; 1480 if (va == vector_page) 1481 goto out; 1482 1483 pa = l2pte_pa(pte); 1484 CTR5(KTR_PMAP, "pmap_fault_fix: pmap:%p va:%x pte:0x%x ftype:%x user:%x", 1485 pmap, va, pte, ftype, user); 1486 if ((ftype & VM_PROT_WRITE) && !(L2_S_WRITABLE(pte)) && 1487 L2_S_REFERENCED(pte)) { 1488 /* 1489 * This looks like a good candidate for "page modified" 1490 * emulation... 1491 */ 1492 struct pv_entry *pv; 1493 struct vm_page *m; 1494 1495 /* Extract the physical address of the page */ 1496 if ((m = PHYS_TO_VM_PAGE(pa)) == NULL) { 1497 goto out; 1498 } 1499 /* Get the current flags for this page. */ 1500 1501 pv = pmap_find_pv(&m->md, pmap, va); 1502 if (pv == NULL) { 1503 goto out; 1504 } 1505 1506 /* 1507 * Do the flags say this page is writable? If not then it 1508 * is a genuine write fault. If yes then the write fault is 1509 * our fault as we did not reflect the write access in the 1510 * PTE. Now we know a write has occurred we can correct this 1511 * and also set the modified bit 1512 */ 1513 if ((pv->pv_flags & PVF_WRITE) == 0) { 1514 goto out; 1515 } 1516 1517 vm_page_dirty(m); 1518 1519 /* Re-enable write permissions for the page */ 1520 *ptep = (pte & ~L2_APX); 1521 PTE_SYNC(ptep); 1522 rv = 1; 1523 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep); 1524 } else if (!L2_S_REFERENCED(pte)) { 1525 /* 1526 * This looks like a good candidate for "page referenced" 1527 * emulation. 1528 */ 1529 struct pv_entry *pv; 1530 struct vm_page *m; 1531 1532 /* Extract the physical address of the page */ 1533 if ((m = PHYS_TO_VM_PAGE(pa)) == NULL) 1534 goto out; 1535 /* Get the current flags for this page. */ 1536 pv = pmap_find_pv(&m->md, pmap, va); 1537 if (pv == NULL) 1538 goto out; 1539 1540 vm_page_aflag_set(m, PGA_REFERENCED); 1541 1542 /* Mark the page "referenced" */ 1543 *ptep = pte | L2_S_REF; 1544 PTE_SYNC(ptep); 1545 rv = 1; 1546 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep); 1547 } 1548 1549 /* 1550 * We know there is a valid mapping here, so simply 1551 * fix up the L1 if necessary. 1552 */ 1553 pl1pd = &pmap->pm_l1->l1_kva[l1idx]; 1554 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | L1_C_PROTO; 1555 if (*pl1pd != l1pd) { 1556 *pl1pd = l1pd; 1557 PTE_SYNC(pl1pd); 1558 rv = 1; 1559 } 1560 1561#ifdef DEBUG 1562 /* 1563 * If 'rv == 0' at this point, it generally indicates that there is a 1564 * stale TLB entry for the faulting address. This happens when two or 1565 * more processes are sharing an L1. Since we don't flush the TLB on 1566 * a context switch between such processes, we can take domain faults 1567 * for mappings which exist at the same VA in both processes. EVEN IF 1568 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 1569 * example. 1570 * 1571 * This is extremely likely to happen if pmap_enter() updated the L1 1572 * entry for a recently entered mapping. In this case, the TLB is 1573 * flushed for the new mapping, but there may still be TLB entries for 1574 * other mappings belonging to other processes in the 1MB range 1575 * covered by the L1 entry. 1576 * 1577 * Since 'rv == 0', we know that the L1 already contains the correct 1578 * value, so the fault must be due to a stale TLB entry. 1579 * 1580 * Since we always need to flush the TLB anyway in the case where we 1581 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 1582 * stale TLB entries dynamically. 1583 * 1584 * However, the above condition can ONLY happen if the current L1 is 1585 * being shared. If it happens when the L1 is unshared, it indicates 1586 * that other parts of the pmap are not doing their job WRT managing 1587 * the TLB. 1588 */ 1589 if (rv == 0 && pmap->pm_l1->l1_domain_use_count == 1) { 1590 printf("fixup: pmap %p, va 0x%08x, ftype %d - nothing to do!\n", 1591 pmap, va, ftype); 1592 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 1593 l2, l2b, ptep, pl1pd); 1594 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 1595 pte, l1pd, last_fault_code); 1596#ifdef DDB 1597 Debugger(); 1598#endif 1599 } 1600#endif 1601 1602l1_section_out: 1603 cpu_tlb_flushID_SE(va); 1604 cpu_cpwait(); 1605 1606 rv = 1; 1607 1608out: 1609 rw_wunlock(&pvh_global_lock); 1610 PMAP_UNLOCK(pmap); 1611 return (rv); 1612} 1613 1614void 1615pmap_postinit(void) 1616{ 1617 struct l2_bucket *l2b; 1618 struct l1_ttable *l1; 1619 pd_entry_t *pl1pt; 1620 pt_entry_t *ptep, pte; 1621 vm_offset_t va, eva; 1622 u_int loop, needed; 1623 1624 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 1625 needed -= 1; 1626 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 1627 1628 for (loop = 0; loop < needed; loop++, l1++) { 1629 /* Allocate a L1 page table */ 1630 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 1631 0xffffffff, L1_TABLE_SIZE, 0); 1632 1633 if (va == 0) 1634 panic("Cannot allocate L1 KVM"); 1635 1636 eva = va + L1_TABLE_SIZE; 1637 pl1pt = (pd_entry_t *)va; 1638 1639 while (va < eva) { 1640 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1641 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1642 pte = *ptep; 1643 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1644 *ptep = pte; 1645 PTE_SYNC(ptep); 1646 cpu_tlb_flushD_SE(va); 1647 1648 va += PAGE_SIZE; 1649 } 1650 pmap_init_l1(l1, pl1pt); 1651 } 1652#ifdef DEBUG 1653 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 1654 needed); 1655#endif 1656} 1657 1658/* 1659 * This is used to stuff certain critical values into the PCB where they 1660 * can be accessed quickly from cpu_switch() et al. 1661 */ 1662void 1663pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb) 1664{ 1665 struct l2_bucket *l2b; 1666 1667 pcb->pcb_pagedir = pmap->pm_l1->l1_physaddr; 1668 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 1669 (DOMAIN_CLIENT << (pmap->pm_domain * 2)); 1670 1671 if (vector_page < KERNBASE) { 1672 pcb->pcb_pl1vec = &pmap->pm_l1->l1_kva[L1_IDX(vector_page)]; 1673 l2b = pmap_get_l2_bucket(pmap, vector_page); 1674 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 1675 L1_C_DOM(pmap->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 1676 } else 1677 pcb->pcb_pl1vec = NULL; 1678} 1679 1680void 1681pmap_activate(struct thread *td) 1682{ 1683 pmap_t pmap; 1684 struct pcb *pcb; 1685 1686 pmap = vmspace_pmap(td->td_proc->p_vmspace); 1687 pcb = td->td_pcb; 1688 1689 critical_enter(); 1690 pmap_set_pcb_pagedir(pmap, pcb); 1691 1692 if (td == curthread) { 1693 u_int cur_dacr, cur_ttb; 1694 1695 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 1696 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 1697 1698 cur_ttb &= ~(L1_TABLE_SIZE - 1); 1699 1700 if (cur_ttb == (u_int)pcb->pcb_pagedir && 1701 cur_dacr == pcb->pcb_dacr) { 1702 /* 1703 * No need to switch address spaces. 1704 */ 1705 critical_exit(); 1706 return; 1707 } 1708 1709 1710 /* 1711 * We MUST, I repeat, MUST fix up the L1 entry corresponding 1712 * to 'vector_page' in the incoming L1 table before switching 1713 * to it otherwise subsequent interrupts/exceptions (including 1714 * domain faults!) will jump into hyperspace. 1715 */ 1716 if (pcb->pcb_pl1vec) { 1717 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 1718 } 1719 1720 cpu_domains(pcb->pcb_dacr); 1721 cpu_setttb(pcb->pcb_pagedir); 1722 } 1723 critical_exit(); 1724} 1725 1726static int 1727pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 1728{ 1729 pd_entry_t *pdep, pde; 1730 pt_entry_t *ptep, pte; 1731 vm_offset_t pa; 1732 int rv = 0; 1733 1734 /* 1735 * Make sure the descriptor itself has the correct cache mode 1736 */ 1737 pdep = &kl1[L1_IDX(va)]; 1738 pde = *pdep; 1739 1740 if (l1pte_section_p(pde)) { 1741 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 1742 *pdep = (pde & ~L1_S_CACHE_MASK) | 1743 pte_l1_s_cache_mode_pt; 1744 PTE_SYNC(pdep); 1745 rv = 1; 1746 } 1747 } else { 1748 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 1749 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 1750 if (ptep == NULL) 1751 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 1752 1753 ptep = &ptep[l2pte_index(va)]; 1754 pte = *ptep; 1755 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1756 *ptep = (pte & ~L2_S_CACHE_MASK) | 1757 pte_l2_s_cache_mode_pt; 1758 PTE_SYNC(ptep); 1759 rv = 1; 1760 } 1761 } 1762 1763 return (rv); 1764} 1765 1766static void 1767pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 1768 pt_entry_t **ptep) 1769{ 1770 vm_offset_t va = *availp; 1771 struct l2_bucket *l2b; 1772 1773 if (ptep) { 1774 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1775 if (l2b == NULL) 1776 panic("pmap_alloc_specials: no l2b for 0x%x", va); 1777 1778 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 1779 } 1780 1781 *vap = va; 1782 *availp = va + (PAGE_SIZE * pages); 1783} 1784 1785/* 1786 * Bootstrap the system enough to run with virtual memory. 1787 * 1788 * On the arm this is called after mapping has already been enabled 1789 * and just syncs the pmap module with what has already been done. 1790 * [We can't call it easily with mapping off since the kernel is not 1791 * mapped with PA == VA, hence we would have to relocate every address 1792 * from the linked base (virtual) address "KERNBASE" to the actual 1793 * (physical) address starting relative to 0] 1794 */ 1795#define PMAP_STATIC_L2_SIZE 16 1796 1797void 1798pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt) 1799{ 1800 static struct l1_ttable static_l1; 1801 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 1802 struct l1_ttable *l1 = &static_l1; 1803 struct l2_dtable *l2; 1804 struct l2_bucket *l2b; 1805 pd_entry_t pde; 1806 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 1807 pt_entry_t *ptep; 1808 vm_paddr_t pa; 1809 vm_offset_t va; 1810 vm_size_t size; 1811 int l1idx, l2idx, l2next = 0; 1812 1813 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", 1814 firstaddr, vm_max_kernel_address)); 1815 1816 virtual_avail = firstaddr; 1817 kernel_pmap->pm_l1 = l1; 1818 kernel_l1pa = l1pt->pv_pa; 1819 1820 /* 1821 * Scan the L1 translation table created by initarm() and create 1822 * the required metadata for all valid mappings found in it. 1823 */ 1824 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 1825 pde = kernel_l1pt[l1idx]; 1826 1827 /* 1828 * We're only interested in Coarse mappings. 1829 * pmap_extract() can deal with section mappings without 1830 * recourse to checking L2 metadata. 1831 */ 1832 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 1833 continue; 1834 1835 /* 1836 * Lookup the KVA of this L2 descriptor table 1837 */ 1838 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 1839 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 1840 1841 if (ptep == NULL) { 1842 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 1843 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 1844 } 1845 1846 /* 1847 * Fetch the associated L2 metadata structure. 1848 * Allocate a new one if necessary. 1849 */ 1850 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 1851 if (l2next == PMAP_STATIC_L2_SIZE) 1852 panic("pmap_bootstrap: out of static L2s"); 1853 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 1854 &static_l2[l2next++]; 1855 } 1856 1857 /* 1858 * One more L1 slot tracked... 1859 */ 1860 l2->l2_occupancy++; 1861 1862 /* 1863 * Fill in the details of the L2 descriptor in the 1864 * appropriate bucket. 1865 */ 1866 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1867 l2b->l2b_kva = ptep; 1868 l2b->l2b_phys = pa; 1869 l2b->l2b_l1idx = l1idx; 1870 1871 /* 1872 * Establish an initial occupancy count for this descriptor 1873 */ 1874 for (l2idx = 0; 1875 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1876 l2idx++) { 1877 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 1878 l2b->l2b_occupancy++; 1879 } 1880 } 1881 1882 /* 1883 * Make sure the descriptor itself has the correct cache mode. 1884 * If not, fix it, but whine about the problem. Port-meisters 1885 * should consider this a clue to fix up their initarm() 1886 * function. :) 1887 */ 1888 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 1889 printf("pmap_bootstrap: WARNING! wrong cache mode for " 1890 "L2 pte @ %p\n", ptep); 1891 } 1892 } 1893 1894 1895 /* 1896 * Ensure the primary (kernel) L1 has the correct cache mode for 1897 * a page table. Bitch if it is not correctly set. 1898 */ 1899 for (va = (vm_offset_t)kernel_l1pt; 1900 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 1901 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 1902 printf("pmap_bootstrap: WARNING! wrong cache mode for " 1903 "primary L1 @ 0x%x\n", va); 1904 } 1905 1906 cpu_dcache_wbinv_all(); 1907 cpu_l2cache_wbinv_all(); 1908 cpu_tlb_flushID(); 1909 cpu_cpwait(); 1910 1911 PMAP_LOCK_INIT(kernel_pmap); 1912 CPU_FILL(&kernel_pmap->pm_active); 1913 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 1914 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 1915 1916 /* 1917 * Initialize the global pv list lock. 1918 */ 1919 rw_init(&pvh_global_lock, "pmap pv global"); 1920 1921 /* 1922 * Reserve some special page table entries/VA space for temporary 1923 * mapping of pages. 1924 */ 1925 1926 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 1927 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 1928 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 1929 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 1930 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) / 1931 L1_S_SIZE; 1932 pmap_alloc_specials(&virtual_avail, 1933 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 1934 &pmap_kernel_l2ptp_kva, NULL); 1935 1936 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 1937 pmap_alloc_specials(&virtual_avail, 1938 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 1939 &pmap_kernel_l2dtable_kva, NULL); 1940 1941 pmap_alloc_specials(&virtual_avail, 1942 1, (vm_offset_t*)&_tmppt, NULL); 1943 pmap_alloc_specials(&virtual_avail, 1944 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL); 1945 SLIST_INIT(&l1_list); 1946 TAILQ_INIT(&l1_lru_list); 1947 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 1948 pmap_init_l1(l1, kernel_l1pt); 1949 cpu_dcache_wbinv_all(); 1950 cpu_l2cache_wbinv_all(); 1951 1952 virtual_avail = round_page(virtual_avail); 1953 virtual_end = vm_max_kernel_address; 1954 kernel_vm_end = pmap_curmaxkvaddr; 1955 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 1956 1957 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 1958} 1959 1960/*************************************************** 1961 * Pmap allocation/deallocation routines. 1962 ***************************************************/ 1963 1964/* 1965 * Release any resources held by the given physical map. 1966 * Called when a pmap initialized by pmap_pinit is being released. 1967 * Should only be called if the map contains no valid mappings. 1968 */ 1969void 1970pmap_release(pmap_t pmap) 1971{ 1972 struct pcb *pcb; 1973 1974 cpu_idcache_wbinv_all(); 1975 cpu_l2cache_wbinv_all(); 1976 cpu_tlb_flushID(); 1977 cpu_cpwait(); 1978 if (vector_page < KERNBASE) { 1979 struct pcb *curpcb = PCPU_GET(curpcb); 1980 pcb = thread0.td_pcb; 1981 if (pmap_is_current(pmap)) { 1982 /* 1983 * Frob the L1 entry corresponding to the vector 1984 * page so that it contains the kernel pmap's domain 1985 * number. This will ensure pmap_remove() does not 1986 * pull the current vector page out from under us. 1987 */ 1988 critical_enter(); 1989 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 1990 cpu_domains(pcb->pcb_dacr); 1991 cpu_setttb(pcb->pcb_pagedir); 1992 critical_exit(); 1993 } 1994 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 1995 /* 1996 * Make sure cpu_switch(), et al, DTRT. This is safe to do 1997 * since this process has no remaining mappings of its own. 1998 */ 1999 curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2000 curpcb->pcb_l1vec = pcb->pcb_l1vec; 2001 curpcb->pcb_dacr = pcb->pcb_dacr; 2002 curpcb->pcb_pagedir = pcb->pcb_pagedir; 2003 2004 } 2005 pmap_free_l1(pmap); 2006 2007 dprintf("pmap_release()\n"); 2008} 2009 2010 2011 2012/* 2013 * Helper function for pmap_grow_l2_bucket() 2014 */ 2015static __inline int 2016pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2017{ 2018 struct l2_bucket *l2b; 2019 pt_entry_t *ptep; 2020 vm_paddr_t pa; 2021 struct vm_page *m; 2022 2023 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2024 if (m == NULL) 2025 return (1); 2026 pa = VM_PAGE_TO_PHYS(m); 2027 2028 if (pap) 2029 *pap = pa; 2030 2031 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2032 2033 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2034 *ptep = L2_S_PROTO | pa | cache_mode | L2_S_REF; 2035 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE, 0); 2036 PTE_SYNC(ptep); 2037 2038 return (0); 2039} 2040 2041/* 2042 * This is the same as pmap_alloc_l2_bucket(), except that it is only 2043 * used by pmap_growkernel(). 2044 */ 2045static __inline struct l2_bucket * 2046pmap_grow_l2_bucket(pmap_t pmap, vm_offset_t va) 2047{ 2048 struct l2_dtable *l2; 2049 struct l2_bucket *l2b; 2050 struct l1_ttable *l1; 2051 pd_entry_t *pl1pd; 2052 u_short l1idx; 2053 vm_offset_t nva; 2054 2055 l1idx = L1_IDX(va); 2056 2057 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2058 /* 2059 * No mapping at this address, as there is 2060 * no entry in the L1 table. 2061 * Need to allocate a new l2_dtable. 2062 */ 2063 nva = pmap_kernel_l2dtable_kva; 2064 if ((nva & PAGE_MASK) == 0) { 2065 /* 2066 * Need to allocate a backing page 2067 */ 2068 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2069 return (NULL); 2070 } 2071 2072 l2 = (struct l2_dtable *)nva; 2073 nva += sizeof(struct l2_dtable); 2074 2075 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2076 PAGE_MASK)) { 2077 /* 2078 * The new l2_dtable straddles a page boundary. 2079 * Map in another page to cover it. 2080 */ 2081 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2082 return (NULL); 2083 } 2084 2085 pmap_kernel_l2dtable_kva = nva; 2086 2087 /* 2088 * Link it into the parent pmap 2089 */ 2090 pmap->pm_l2[L2_IDX(l1idx)] = l2; 2091 memset(l2, 0, sizeof(*l2)); 2092 } 2093 2094 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2095 2096 /* 2097 * Fetch pointer to the L2 page table associated with the address. 2098 */ 2099 if (l2b->l2b_kva == NULL) { 2100 pt_entry_t *ptep; 2101 2102 /* 2103 * No L2 page table has been allocated. Chances are, this 2104 * is because we just allocated the l2_dtable, above. 2105 */ 2106 nva = pmap_kernel_l2ptp_kva; 2107 ptep = (pt_entry_t *)nva; 2108 if ((nva & PAGE_MASK) == 0) { 2109 /* 2110 * Need to allocate a backing page 2111 */ 2112 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2113 &pmap_kernel_l2ptp_phys)) 2114 return (NULL); 2115 } 2116 memset(ptep, 0, L2_TABLE_SIZE_REAL); 2117 l2->l2_occupancy++; 2118 l2b->l2b_kva = ptep; 2119 l2b->l2b_l1idx = l1idx; 2120 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2121 2122 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2123 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2124 } 2125 2126 /* Distribute new L1 entry to all other L1s */ 2127 SLIST_FOREACH(l1, &l1_list, l1_link) { 2128 pl1pd = &l1->l1_kva[L1_IDX(va)]; 2129 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2130 L1_C_PROTO; 2131 PTE_SYNC(pl1pd); 2132 } 2133 2134 return (l2b); 2135} 2136 2137 2138/* 2139 * grow the number of kernel page table entries, if needed 2140 */ 2141void 2142pmap_growkernel(vm_offset_t addr) 2143{ 2144 pmap_t kpmap = pmap_kernel(); 2145 2146 if (addr <= pmap_curmaxkvaddr) 2147 return; /* we are OK */ 2148 2149 /* 2150 * whoops! we need to add kernel PTPs 2151 */ 2152 2153 /* Map 1MB at a time */ 2154 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2155 pmap_grow_l2_bucket(kpmap, pmap_curmaxkvaddr); 2156 2157 /* 2158 * flush out the cache, expensive but growkernel will happen so 2159 * rarely 2160 */ 2161 cpu_dcache_wbinv_all(); 2162 cpu_l2cache_wbinv_all(); 2163 cpu_tlb_flushD(); 2164 cpu_cpwait(); 2165 kernel_vm_end = pmap_curmaxkvaddr; 2166} 2167 2168/* 2169 * Returns TRUE if the given page is mapped individually or as part of 2170 * a 1MB section. Otherwise, returns FALSE. 2171 */ 2172boolean_t 2173pmap_page_is_mapped(vm_page_t m) 2174{ 2175 boolean_t rv; 2176 2177 if ((m->oflags & VPO_UNMANAGED) != 0) 2178 return (FALSE); 2179 rw_wlock(&pvh_global_lock); 2180 rv = !TAILQ_EMPTY(&m->md.pv_list) || 2181 ((m->flags & PG_FICTITIOUS) == 0 && 2182 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 2183 rw_wunlock(&pvh_global_lock); 2184 return (rv); 2185} 2186 2187/* 2188 * Remove all pages from specified address space 2189 * this aids process exit speeds. Also, this code 2190 * is special cased for current process only, but 2191 * can have the more generic (and slightly slower) 2192 * mode enabled. This is much faster than pmap_remove 2193 * in the case of running down an entire address space. 2194 */ 2195void 2196pmap_remove_pages(pmap_t pmap) 2197{ 2198 struct pv_entry *pv; 2199 struct l2_bucket *l2b = NULL; 2200 struct pv_chunk *pc, *npc; 2201 struct md_page *pvh; 2202 pd_entry_t *pl1pd, l1pd; 2203 pt_entry_t *ptep; 2204 vm_page_t m, mt; 2205 vm_offset_t va; 2206 uint32_t inuse, bitmask; 2207 int allfree, bit, field, idx; 2208 2209 rw_wlock(&pvh_global_lock); 2210 PMAP_LOCK(pmap); 2211 2212 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 2213 allfree = 1; 2214 for (field = 0; field < _NPCM; field++) { 2215 inuse = ~pc->pc_map[field] & pc_freemask[field]; 2216 while (inuse != 0) { 2217 bit = ffs(inuse) - 1; 2218 bitmask = 1ul << bit; 2219 idx = field * sizeof(inuse) * NBBY + bit; 2220 pv = &pc->pc_pventry[idx]; 2221 va = pv->pv_va; 2222 inuse &= ~bitmask; 2223 if (pv->pv_flags & PVF_WIRED) { 2224 /* Cannot remove wired pages now. */ 2225 allfree = 0; 2226 continue; 2227 } 2228 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 2229 l1pd = *pl1pd; 2230 l2b = pmap_get_l2_bucket(pmap, va); 2231 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) { 2232 pvh = pa_to_pvh(l1pd & L1_S_FRAME); 2233 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2234 if (TAILQ_EMPTY(&pvh->pv_list)) { 2235 m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME); 2236 KASSERT((vm_offset_t)m >= KERNBASE, 2237 ("Trying to access non-existent page " 2238 "va %x l1pd %x", trunc_1mpage(va), l1pd)); 2239 for (mt = m; mt < &m[L2_PTE_NUM_TOTAL]; mt++) { 2240 if (TAILQ_EMPTY(&mt->md.pv_list)) 2241 vm_page_aflag_clear(mt, PGA_WRITEABLE); 2242 } 2243 } 2244 if (l2b != NULL) { 2245 KASSERT(l2b->l2b_occupancy == L2_PTE_NUM_TOTAL, 2246 ("pmap_remove_pages: l2_bucket occupancy error")); 2247 pmap_free_l2_bucket(pmap, l2b, L2_PTE_NUM_TOTAL); 2248 } 2249 pmap->pm_stats.resident_count -= L2_PTE_NUM_TOTAL; 2250 *pl1pd = 0; 2251 PTE_SYNC(pl1pd); 2252 } else { 2253 KASSERT(l2b != NULL, 2254 ("No L2 bucket in pmap_remove_pages")); 2255 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2256 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep)); 2257 KASSERT((vm_offset_t)m >= KERNBASE, 2258 ("Trying to access non-existent page " 2259 "va %x pte %x", va, *ptep)); 2260 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2261 if (TAILQ_EMPTY(&m->md.pv_list) && 2262 (m->flags & PG_FICTITIOUS) == 0) { 2263 pvh = pa_to_pvh(l2pte_pa(*ptep)); 2264 if (TAILQ_EMPTY(&pvh->pv_list)) 2265 vm_page_aflag_clear(m, PGA_WRITEABLE); 2266 } 2267 *ptep = 0; 2268 PTE_SYNC(ptep); 2269 pmap_free_l2_bucket(pmap, l2b, 1); 2270 pmap->pm_stats.resident_count--; 2271 } 2272 2273 /* Mark free */ 2274 PV_STAT(pv_entry_frees++); 2275 PV_STAT(pv_entry_spare++); 2276 pv_entry_count--; 2277 pc->pc_map[field] |= bitmask; 2278 } 2279 } 2280 if (allfree) { 2281 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2282 pmap_free_pv_chunk(pc); 2283 } 2284 2285 } 2286 2287 rw_wunlock(&pvh_global_lock); 2288 cpu_tlb_flushID(); 2289 cpu_cpwait(); 2290 PMAP_UNLOCK(pmap); 2291} 2292 2293 2294/*************************************************** 2295 * Low level mapping routines..... 2296 ***************************************************/ 2297 2298#ifdef ARM_HAVE_SUPERSECTIONS 2299/* Map a super section into the KVA. */ 2300 2301void 2302pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags) 2303{ 2304 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) | 2305 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL, 2306 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE) | 2307 L1_S_DOM(PMAP_DOMAIN_KERNEL); 2308 struct l1_ttable *l1; 2309 vm_offset_t va0, va_end; 2310 2311 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0, 2312 ("Not a valid super section mapping")); 2313 if (flags & SECTION_CACHE) 2314 pd |= pte_l1_s_cache_mode; 2315 else if (flags & SECTION_PT) 2316 pd |= pte_l1_s_cache_mode_pt; 2317 2318 va0 = va & L1_SUP_FRAME; 2319 va_end = va + L1_SUP_SIZE; 2320 SLIST_FOREACH(l1, &l1_list, l1_link) { 2321 va = va0; 2322 for (; va < va_end; va += L1_S_SIZE) { 2323 l1->l1_kva[L1_IDX(va)] = pd; 2324 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2325 } 2326 } 2327} 2328#endif 2329 2330/* Map a section into the KVA. */ 2331 2332void 2333pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2334{ 2335 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2336 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE) | L1_S_REF | 2337 L1_S_DOM(PMAP_DOMAIN_KERNEL); 2338 struct l1_ttable *l1; 2339 2340 KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2341 ("Not a valid section mapping")); 2342 if (flags & SECTION_CACHE) 2343 pd |= pte_l1_s_cache_mode; 2344 else if (flags & SECTION_PT) 2345 pd |= pte_l1_s_cache_mode_pt; 2346 2347 SLIST_FOREACH(l1, &l1_list, l1_link) { 2348 l1->l1_kva[L1_IDX(va)] = pd; 2349 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2350 } 2351} 2352 2353/* 2354 * Make a temporary mapping for a physical address. This is only intended 2355 * to be used for panic dumps. 2356 */ 2357void * 2358pmap_kenter_temp(vm_paddr_t pa, int i) 2359{ 2360 vm_offset_t va; 2361 2362 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 2363 pmap_kenter(va, pa); 2364 return ((void *)crashdumpmap); 2365} 2366 2367/* 2368 * add a wired page to the kva 2369 * note that in order for the mapping to take effect -- you 2370 * should do a invltlb after doing the pmap_kenter... 2371 */ 2372static PMAP_INLINE void 2373pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2374{ 2375 struct l2_bucket *l2b; 2376 pt_entry_t *ptep; 2377 pt_entry_t opte; 2378 2379 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2380 (uint32_t) va, (uint32_t) pa)); 2381 2382 2383 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2384 if (l2b == NULL) 2385 l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2386 KASSERT(l2b != NULL, ("No L2 Bucket")); 2387 2388 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2389 opte = *ptep; 2390 if (l2pte_valid(opte)) { 2391 cpu_tlb_flushD_SE(va); 2392 cpu_cpwait(); 2393 } else { 2394 if (opte == 0) 2395 l2b->l2b_occupancy++; 2396 } 2397 2398 if (flags & KENTER_CACHE) { 2399 *ptep = L2_S_PROTO | pa | pte_l2_s_cache_mode | L2_S_REF; 2400 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE, 2401 flags & KENTER_USER); 2402 } else { 2403 *ptep = L2_S_PROTO | pa | L2_S_REF; 2404 pmap_set_prot(ptep, VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, 2405 0); 2406 } 2407 2408 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2409 (uint32_t) ptep, opte, *ptep)); 2410 PTE_SYNC(ptep); 2411 cpu_cpwait(); 2412} 2413 2414void 2415pmap_kenter(vm_offset_t va, vm_paddr_t pa) 2416{ 2417 pmap_kenter_internal(va, pa, KENTER_CACHE); 2418} 2419 2420void 2421pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2422{ 2423 2424 pmap_kenter_internal(va, pa, 0); 2425} 2426 2427void 2428pmap_kenter_device(vm_offset_t va, vm_paddr_t pa) 2429{ 2430 2431 /* 2432 * XXX - Need a way for kenter_internal to handle PTE_DEVICE mapping as 2433 * a potentially different thing than PTE_NOCACHE. 2434 */ 2435 pmap_kenter_internal(va, pa, 0); 2436} 2437 2438void 2439pmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2440{ 2441 2442 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2443 /* 2444 * Call pmap_fault_fixup now, to make sure we'll have no exception 2445 * at the first use of the new address, or bad things will happen, 2446 * as we use one of these addresses in the exception handlers. 2447 */ 2448 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2449} 2450 2451vm_paddr_t 2452pmap_kextract(vm_offset_t va) 2453{ 2454 2455 if (kernel_vm_end == 0) 2456 return (0); 2457 return (pmap_extract_locked(kernel_pmap, va)); 2458} 2459 2460/* 2461 * remove a page from the kernel pagetables 2462 */ 2463void 2464pmap_kremove(vm_offset_t va) 2465{ 2466 struct l2_bucket *l2b; 2467 pt_entry_t *ptep, opte; 2468 2469 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2470 if (!l2b) 2471 return; 2472 KASSERT(l2b != NULL, ("No L2 Bucket")); 2473 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2474 opte = *ptep; 2475 if (l2pte_valid(opte)) { 2476 va = va & ~PAGE_MASK; 2477 cpu_tlb_flushD_SE(va); 2478 cpu_cpwait(); 2479 *ptep = 0; 2480 PTE_SYNC(ptep); 2481 } 2482} 2483 2484 2485/* 2486 * Used to map a range of physical addresses into kernel 2487 * virtual address space. 2488 * 2489 * The value passed in '*virt' is a suggested virtual address for 2490 * the mapping. Architectures which can support a direct-mapped 2491 * physical to virtual region can return the appropriate address 2492 * within that region, leaving '*virt' unchanged. Other 2493 * architectures should map the pages starting at '*virt' and 2494 * update '*virt' with the first usable address after the mapped 2495 * region. 2496 */ 2497vm_offset_t 2498pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2499{ 2500 vm_offset_t sva = *virt; 2501 vm_offset_t va = sva; 2502 2503 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2504 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2505 prot)); 2506 2507 while (start < end) { 2508 pmap_kenter(va, start); 2509 va += PAGE_SIZE; 2510 start += PAGE_SIZE; 2511 } 2512 *virt = va; 2513 return (sva); 2514} 2515 2516/* 2517 * Add a list of wired pages to the kva 2518 * this routine is only used for temporary 2519 * kernel mappings that do not need to have 2520 * page modification or references recorded. 2521 * Note that old mappings are simply written 2522 * over. The page *must* be wired. 2523 */ 2524void 2525pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2526{ 2527 int i; 2528 2529 for (i = 0; i < count; i++) { 2530 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2531 KENTER_CACHE); 2532 va += PAGE_SIZE; 2533 } 2534} 2535 2536 2537/* 2538 * this routine jerks page mappings from the 2539 * kernel -- it is meant only for temporary mappings. 2540 */ 2541void 2542pmap_qremove(vm_offset_t va, int count) 2543{ 2544 int i; 2545 2546 for (i = 0; i < count; i++) { 2547 if (vtophys(va)) 2548 pmap_kremove(va); 2549 2550 va += PAGE_SIZE; 2551 } 2552} 2553 2554 2555/* 2556 * pmap_object_init_pt preloads the ptes for a given object 2557 * into the specified pmap. This eliminates the blast of soft 2558 * faults on process startup and immediately after an mmap. 2559 */ 2560void 2561pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 2562 vm_pindex_t pindex, vm_size_t size) 2563{ 2564 2565 VM_OBJECT_ASSERT_WLOCKED(object); 2566 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2567 ("pmap_object_init_pt: non-device object")); 2568} 2569 2570 2571/* 2572 * pmap_is_prefaultable: 2573 * 2574 * Return whether or not the specified virtual address is elgible 2575 * for prefault. 2576 */ 2577boolean_t 2578pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2579{ 2580 pd_entry_t *pdep; 2581 pt_entry_t *ptep; 2582 2583 if (!pmap_get_pde_pte(pmap, addr, &pdep, &ptep)) 2584 return (FALSE); 2585 KASSERT((pdep != NULL && (l1pte_section_p(*pdep) || ptep != NULL)), 2586 ("Valid mapping but no pte ?")); 2587 if (*pdep != 0 && !l1pte_section_p(*pdep)) 2588 if (*ptep == 0) 2589 return (TRUE); 2590 return (FALSE); 2591} 2592 2593/* 2594 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 2595 * Returns TRUE if the mapping exists, else FALSE. 2596 * 2597 * NOTE: This function is only used by a couple of arm-specific modules. 2598 * It is not safe to take any pmap locks here, since we could be right 2599 * in the middle of debugging the pmap anyway... 2600 * 2601 * It is possible for this routine to return FALSE even though a valid 2602 * mapping does exist. This is because we don't lock, so the metadata 2603 * state may be inconsistent. 2604 * 2605 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 2606 * a "section" mapping. 2607 */ 2608boolean_t 2609pmap_get_pde_pte(pmap_t pmap, vm_offset_t va, pd_entry_t **pdp, 2610 pt_entry_t **ptp) 2611{ 2612 struct l2_dtable *l2; 2613 pd_entry_t *pl1pd, l1pd; 2614 pt_entry_t *ptep; 2615 u_short l1idx; 2616 2617 if (pmap->pm_l1 == NULL) 2618 return (FALSE); 2619 2620 l1idx = L1_IDX(va); 2621 *pdp = pl1pd = &pmap->pm_l1->l1_kva[l1idx]; 2622 l1pd = *pl1pd; 2623 2624 if (l1pte_section_p(l1pd)) { 2625 *ptp = NULL; 2626 return (TRUE); 2627 } 2628 2629 if (pmap->pm_l2 == NULL) 2630 return (FALSE); 2631 2632 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 2633 2634 if (l2 == NULL || 2635 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2636 return (FALSE); 2637 } 2638 2639 *ptp = &ptep[l2pte_index(va)]; 2640 return (TRUE); 2641} 2642 2643/* 2644 * Routine: pmap_remove_all 2645 * Function: 2646 * Removes this physical page from 2647 * all physical maps in which it resides. 2648 * Reflects back modify bits to the pager. 2649 * 2650 * Notes: 2651 * Original versions of this routine were very 2652 * inefficient because they iteratively called 2653 * pmap_remove (slow...) 2654 */ 2655void 2656pmap_remove_all(vm_page_t m) 2657{ 2658 struct md_page *pvh; 2659 pv_entry_t pv; 2660 pmap_t pmap; 2661 pt_entry_t *ptep; 2662 struct l2_bucket *l2b; 2663 boolean_t flush = FALSE; 2664 pmap_t curpmap; 2665 u_int is_exec = 0; 2666 2667 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2668 ("pmap_remove_all: page %p is not managed", m)); 2669 rw_wlock(&pvh_global_lock); 2670 if ((m->flags & PG_FICTITIOUS) != 0) 2671 goto small_mappings; 2672 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2673 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2674 pmap = PV_PMAP(pv); 2675 PMAP_LOCK(pmap); 2676 pd_entry_t *pl1pd; 2677 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)]; 2678 KASSERT((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO, 2679 ("pmap_remove_all: valid section mapping expected")); 2680 (void)pmap_demote_section(pmap, pv->pv_va); 2681 PMAP_UNLOCK(pmap); 2682 } 2683small_mappings: 2684 curpmap = vmspace_pmap(curproc->p_vmspace); 2685 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2686 pmap = PV_PMAP(pv); 2687 if (flush == FALSE && (pmap == curpmap || 2688 pmap == pmap_kernel())) 2689 flush = TRUE; 2690 2691 PMAP_LOCK(pmap); 2692 l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2693 KASSERT(l2b != NULL, ("No l2 bucket")); 2694 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2695 is_exec |= PTE_BEEN_EXECD(*ptep); 2696 *ptep = 0; 2697 if (pmap_is_current(pmap)) 2698 PTE_SYNC(ptep); 2699 pmap_free_l2_bucket(pmap, l2b, 1); 2700 pmap->pm_stats.resident_count--; 2701 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2702 if (pv->pv_flags & PVF_WIRED) 2703 pmap->pm_stats.wired_count--; 2704 pmap_free_pv_entry(pmap, pv); 2705 PMAP_UNLOCK(pmap); 2706 } 2707 2708 if (flush) { 2709 if (is_exec) 2710 cpu_tlb_flushID(); 2711 else 2712 cpu_tlb_flushD(); 2713 } 2714 vm_page_aflag_clear(m, PGA_WRITEABLE); 2715 rw_wunlock(&pvh_global_lock); 2716} 2717 2718int 2719pmap_change_attr(vm_offset_t sva, vm_size_t len, int mode) 2720{ 2721 vm_offset_t base, offset, tmpva; 2722 vm_size_t size; 2723 struct l2_bucket *l2b; 2724 pt_entry_t *ptep, pte; 2725 vm_offset_t next_bucket; 2726 2727 PMAP_LOCK(kernel_pmap); 2728 2729 base = trunc_page(sva); 2730 offset = sva & PAGE_MASK; 2731 size = roundup(offset + len, PAGE_SIZE); 2732 2733#ifdef checkit 2734 /* 2735 * Only supported on kernel virtual addresses, including the direct 2736 * map but excluding the recursive map. 2737 */ 2738 if (base < DMAP_MIN_ADDRESS) { 2739 PMAP_UNLOCK(kernel_pmap); 2740 return (EINVAL); 2741 } 2742#endif 2743 for (tmpva = base; tmpva < base + size; ) { 2744 next_bucket = L2_NEXT_BUCKET(tmpva); 2745 if (next_bucket > base + size) 2746 next_bucket = base + size; 2747 2748 l2b = pmap_get_l2_bucket(kernel_pmap, tmpva); 2749 if (l2b == NULL) { 2750 tmpva = next_bucket; 2751 continue; 2752 } 2753 2754 ptep = &l2b->l2b_kva[l2pte_index(tmpva)]; 2755 2756 if (*ptep == 0) { 2757 PMAP_UNLOCK(kernel_pmap); 2758 return(EINVAL); 2759 } 2760 2761 pte = *ptep &~ L2_S_CACHE_MASK; 2762 cpu_idcache_wbinv_range(tmpva, PAGE_SIZE); 2763 pmap_l2cache_wbinv_range(tmpva, pte & L2_S_FRAME, PAGE_SIZE); 2764 *ptep = pte; 2765 cpu_tlb_flushID_SE(tmpva); 2766 2767 dprintf("%s: for va:%x ptep:%x pte:%x\n", 2768 __func__, tmpva, (uint32_t)ptep, pte); 2769 tmpva += PAGE_SIZE; 2770 } 2771 2772 PMAP_UNLOCK(kernel_pmap); 2773 2774 return (0); 2775} 2776 2777/* 2778 * Set the physical protection on the 2779 * specified range of this map as requested. 2780 */ 2781void 2782pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2783{ 2784 struct l2_bucket *l2b; 2785 struct md_page *pvh; 2786 struct pv_entry *pve; 2787 pd_entry_t *pl1pd, l1pd; 2788 pt_entry_t *ptep, pte; 2789 vm_offset_t next_bucket; 2790 u_int is_exec, is_refd; 2791 int flush; 2792 2793 if ((prot & VM_PROT_READ) == 0) { 2794 pmap_remove(pmap, sva, eva); 2795 return; 2796 } 2797 2798 if (prot & VM_PROT_WRITE) { 2799 /* 2800 * If this is a read->write transition, just ignore it and let 2801 * vm_fault() take care of it later. 2802 */ 2803 return; 2804 } 2805 2806 rw_wlock(&pvh_global_lock); 2807 PMAP_LOCK(pmap); 2808 2809 /* 2810 * OK, at this point, we know we're doing write-protect operation. 2811 * If the pmap is active, write-back the range. 2812 */ 2813 2814 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 2815 is_exec = is_refd = 0; 2816 2817 while (sva < eva) { 2818 next_bucket = L2_NEXT_BUCKET(sva); 2819 /* 2820 * Check for large page. 2821 */ 2822 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)]; 2823 l1pd = *pl1pd; 2824 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) { 2825 KASSERT(pmap != pmap_kernel(), 2826 ("pmap_protect: trying to modify " 2827 "kernel section protections")); 2828 /* 2829 * Are we protecting the entire large page? If not, 2830 * demote the mapping and fall through. 2831 */ 2832 if (sva + L1_S_SIZE == L2_NEXT_BUCKET(sva) && 2833 eva >= L2_NEXT_BUCKET(sva)) { 2834 l1pd &= ~(L1_S_PROT_MASK | L1_S_XN); 2835 if (!(prot & VM_PROT_EXECUTE)) 2836 *pl1pd |= L1_S_XN; 2837 /* 2838 * At this point we are always setting 2839 * write-protect bit. 2840 */ 2841 l1pd |= L1_S_APX; 2842 /* All managed superpages are user pages. */ 2843 l1pd |= L1_S_PROT_U; 2844 *pl1pd = l1pd; 2845 PTE_SYNC(pl1pd); 2846 pvh = pa_to_pvh(l1pd & L1_S_FRAME); 2847 pve = pmap_find_pv(pvh, pmap, 2848 trunc_1mpage(sva)); 2849 pve->pv_flags &= ~PVF_WRITE; 2850 sva = next_bucket; 2851 continue; 2852 } else if (!pmap_demote_section(pmap, sva)) { 2853 /* The large page mapping was destroyed. */ 2854 sva = next_bucket; 2855 continue; 2856 } 2857 } 2858 if (next_bucket > eva) 2859 next_bucket = eva; 2860 l2b = pmap_get_l2_bucket(pmap, sva); 2861 if (l2b == NULL) { 2862 sva = next_bucket; 2863 continue; 2864 } 2865 2866 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2867 2868 while (sva < next_bucket) { 2869 if ((pte = *ptep) != 0 && L2_S_WRITABLE(pte)) { 2870 struct vm_page *m; 2871 2872 m = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 2873 pmap_set_prot(ptep, prot, 2874 !(pmap == pmap_kernel())); 2875 PTE_SYNC(ptep); 2876 2877 pmap_modify_pv(m, pmap, sva, PVF_WRITE, 0); 2878 2879 if (flush >= 0) { 2880 flush++; 2881 is_exec |= PTE_BEEN_EXECD(pte); 2882 is_refd |= PTE_BEEN_REFD(pte); 2883 } else { 2884 if (PTE_BEEN_EXECD(pte)) 2885 cpu_tlb_flushID_SE(sva); 2886 else if (PTE_BEEN_REFD(pte)) 2887 cpu_tlb_flushD_SE(sva); 2888 } 2889 } 2890 2891 sva += PAGE_SIZE; 2892 ptep++; 2893 } 2894 } 2895 2896 2897 if (flush) { 2898 if (is_exec) 2899 cpu_tlb_flushID(); 2900 else 2901 if (is_refd) 2902 cpu_tlb_flushD(); 2903 } 2904 rw_wunlock(&pvh_global_lock); 2905 2906 PMAP_UNLOCK(pmap); 2907} 2908 2909 2910/* 2911 * Insert the given physical page (p) at 2912 * the specified virtual address (v) in the 2913 * target physical map with the protection requested. 2914 * 2915 * If specified, the page will be wired down, meaning 2916 * that the related pte can not be reclaimed. 2917 * 2918 * NB: This is the only routine which MAY NOT lazy-evaluate 2919 * or lose information. That is, this routine must actually 2920 * insert this page into the given map NOW. 2921 */ 2922 2923void 2924pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2925 vm_prot_t prot, boolean_t wired) 2926{ 2927 2928 rw_wlock(&pvh_global_lock); 2929 PMAP_LOCK(pmap); 2930 pmap_enter_locked(pmap, va, access, m, prot, wired, M_WAITOK); 2931 PMAP_UNLOCK(pmap); 2932 rw_wunlock(&pvh_global_lock); 2933} 2934 2935/* 2936 * The pvh global and pmap locks must be held. 2937 */ 2938static void 2939pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2940 vm_prot_t prot, boolean_t wired, int flags) 2941{ 2942 struct l2_bucket *l2b = NULL; 2943 struct vm_page *om; 2944 struct pv_entry *pve = NULL; 2945 pd_entry_t *pl1pd, l1pd; 2946 pt_entry_t *ptep, npte, opte; 2947 u_int nflags; 2948 u_int is_exec, is_refd; 2949 vm_paddr_t pa; 2950 u_char user; 2951 2952 PMAP_ASSERT_LOCKED(pmap); 2953 rw_assert(&pvh_global_lock, RA_WLOCKED); 2954 if (va == vector_page) { 2955 pa = systempage.pv_pa; 2956 m = NULL; 2957 } else { 2958 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || 2959 vm_page_xbusied(m) || (flags & M_NOWAIT) != 0, 2960 ("pmap_enter_locked: page %p is not busy", m)); 2961 pa = VM_PAGE_TO_PHYS(m); 2962 } 2963 2964 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 2965 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO) 2966 panic("pmap_enter_locked: attempt pmap_enter_on 1MB page"); 2967 2968 user = 0; 2969 /* 2970 * Make sure userland mappings get the right permissions 2971 */ 2972 if (pmap != pmap_kernel() && va != vector_page) 2973 user = 1; 2974 2975 nflags = 0; 2976 2977 if (prot & VM_PROT_WRITE) 2978 nflags |= PVF_WRITE; 2979 if (wired) 2980 nflags |= PVF_WIRED; 2981 2982 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, " 2983 "prot = %x, wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, 2984 prot, wired)); 2985 2986 if (pmap == pmap_kernel()) { 2987 l2b = pmap_get_l2_bucket(pmap, va); 2988 if (l2b == NULL) 2989 l2b = pmap_grow_l2_bucket(pmap, va); 2990 } else { 2991do_l2b_alloc: 2992 l2b = pmap_alloc_l2_bucket(pmap, va); 2993 if (l2b == NULL) { 2994 if (flags & M_WAITOK) { 2995 PMAP_UNLOCK(pmap); 2996 rw_wunlock(&pvh_global_lock); 2997 VM_WAIT; 2998 rw_wlock(&pvh_global_lock); 2999 PMAP_LOCK(pmap); 3000 goto do_l2b_alloc; 3001 } 3002 return; 3003 } 3004 } 3005 3006 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3007 3008 opte = *ptep; 3009 npte = pa; 3010 is_exec = is_refd = 0; 3011 3012 if (opte) { 3013 if (l2pte_pa(opte) == pa) { 3014 /* 3015 * We're changing the attrs of an existing mapping. 3016 */ 3017 if (m != NULL) 3018 pmap_modify_pv(m, pmap, va, 3019 PVF_WRITE | PVF_WIRED, nflags); 3020 is_exec |= PTE_BEEN_EXECD(opte); 3021 is_refd |= PTE_BEEN_REFD(opte); 3022 goto validate; 3023 } 3024 if ((om = PHYS_TO_VM_PAGE(l2pte_pa(opte)))) { 3025 /* 3026 * Replacing an existing mapping with a new one. 3027 * It is part of our managed memory so we 3028 * must remove it from the PV list 3029 */ 3030 if ((pve = pmap_remove_pv(om, pmap, va))) { 3031 is_exec |= PTE_BEEN_EXECD(opte); 3032 is_refd |= PTE_BEEN_REFD(opte); 3033 3034 if (m && ((m->oflags & VPO_UNMANAGED))) 3035 pmap_free_pv_entry(pmap, pve); 3036 } 3037 } 3038 3039 } else { 3040 /* 3041 * Keep the stats up to date 3042 */ 3043 l2b->l2b_occupancy++; 3044 pmap->pm_stats.resident_count++; 3045 } 3046 3047 /* 3048 * Enter on the PV list if part of our managed memory. 3049 */ 3050 if ((m && !(m->oflags & VPO_UNMANAGED))) { 3051 if ((!pve) && (pve = pmap_get_pv_entry(pmap, FALSE)) == NULL) 3052 panic("pmap_enter: no pv entries"); 3053 3054 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3055 ("pmap_enter: managed mapping within the clean submap")); 3056 KASSERT(pve != NULL, ("No pv")); 3057 pmap_enter_pv(m, pve, pmap, va, nflags); 3058 } 3059 3060validate: 3061 /* Make the new PTE valid */ 3062 npte |= L2_S_PROTO; 3063#ifdef SMP 3064 npte |= L2_SHARED; 3065#endif 3066 /* Set defaults first - kernel read access */ 3067 npte |= L2_APX; 3068 npte |= L2_S_PROT_R; 3069 /* Set "referenced" flag */ 3070 npte |= L2_S_REF; 3071 3072 /* Now tune APs as desired */ 3073 if (user) 3074 npte |= L2_S_PROT_U; 3075 /* 3076 * If this is not a vector_page 3077 * then continue setting mapping parameters 3078 */ 3079 if (m != NULL) { 3080 if ((m->oflags & VPO_UNMANAGED) == 0) { 3081 if (prot & (VM_PROT_ALL)) { 3082 vm_page_aflag_set(m, PGA_REFERENCED); 3083 } else { 3084 /* 3085 * Need to do page referenced emulation. 3086 */ 3087 npte &= ~L2_S_REF; 3088 } 3089 } 3090 3091 if (prot & VM_PROT_WRITE) { 3092 if ((m->oflags & VPO_UNMANAGED) == 0) { 3093 vm_page_aflag_set(m, PGA_WRITEABLE); 3094 /* 3095 * XXX: Skip modified bit emulation for now. 3096 * The emulation reveals problems 3097 * that result in random failures 3098 * during memory allocation on some 3099 * platforms. 3100 * Therefore, the page is marked RW 3101 * immediately. 3102 */ 3103 npte &= ~(L2_APX); 3104 vm_page_dirty(m); 3105 } else 3106 npte &= ~(L2_APX); 3107 } 3108 if (!(prot & VM_PROT_EXECUTE)) 3109 npte |= L2_XN; 3110 3111 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 3112 npte |= pte_l2_s_cache_mode; 3113 } 3114 3115 CTR5(KTR_PMAP,"enter: pmap:%p va:%x prot:%x pte:%x->%x", 3116 pmap, va, prot, opte, npte); 3117 /* 3118 * If this is just a wiring change, the two PTEs will be 3119 * identical, so there's no need to update the page table. 3120 */ 3121 if (npte != opte) { 3122 boolean_t is_cached = pmap_is_current(pmap); 3123 3124 *ptep = npte; 3125 PTE_SYNC(ptep); 3126 if (is_cached) { 3127 /* 3128 * We only need to frob the cache/tlb if this pmap 3129 * is current 3130 */ 3131 if (L1_IDX(va) != L1_IDX(vector_page) && 3132 l2pte_valid(npte)) { 3133 /* 3134 * This mapping is likely to be accessed as 3135 * soon as we return to userland. Fix up the 3136 * L1 entry to avoid taking another 3137 * page/domain fault. 3138 */ 3139 l1pd = l2b->l2b_phys | 3140 L1_C_DOM(pmap->pm_domain) | L1_C_PROTO; 3141 if (*pl1pd != l1pd) { 3142 *pl1pd = l1pd; 3143 PTE_SYNC(pl1pd); 3144 } 3145 } 3146 } 3147 3148 if (is_exec) 3149 cpu_tlb_flushID_SE(va); 3150 else if (is_refd) 3151 cpu_tlb_flushD_SE(va); 3152 } 3153 3154 if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap)) 3155 cpu_icache_sync_range(va, PAGE_SIZE); 3156 /* 3157 * If both the l2b_occupancy and the reservation are fully 3158 * populated, then attempt promotion. 3159 */ 3160 if ((l2b->l2b_occupancy == L2_PTE_NUM_TOTAL) && 3161 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 && 3162 vm_reserv_level_iffullpop(m) == 0) 3163 pmap_promote_section(pmap, va); 3164} 3165 3166/* 3167 * Maps a sequence of resident pages belonging to the same object. 3168 * The sequence begins with the given page m_start. This page is 3169 * mapped at the given virtual address start. Each subsequent page is 3170 * mapped at a virtual address that is offset from start by the same 3171 * amount as the page is offset from m_start within the object. The 3172 * last page in the sequence is the page with the largest offset from 3173 * m_start that can be mapped at a virtual address less than the given 3174 * virtual address end. Not every virtual page between start and end 3175 * is mapped; only those for which a resident page exists with the 3176 * corresponding offset from m_start are mapped. 3177 */ 3178void 3179pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3180 vm_page_t m_start, vm_prot_t prot) 3181{ 3182 vm_offset_t va; 3183 vm_page_t m; 3184 vm_pindex_t diff, psize; 3185 vm_prot_t access; 3186 3187 VM_OBJECT_ASSERT_LOCKED(m_start->object); 3188 3189 psize = atop(end - start); 3190 m = m_start; 3191 access = prot = prot & (VM_PROT_READ | VM_PROT_EXECUTE); 3192 rw_wlock(&pvh_global_lock); 3193 PMAP_LOCK(pmap); 3194 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3195 va = start + ptoa(diff); 3196 if ((va & L1_S_OFFSET) == 0 && L2_NEXT_BUCKET(va) <= end && 3197 (VM_PAGE_TO_PHYS(m) & L1_S_OFFSET) == 0 && 3198 sp_enabled && vm_reserv_level_iffullpop(m) == 0 && 3199 pmap_enter_section(pmap, va, m, prot)) 3200 m = &m[L1_S_SIZE / PAGE_SIZE - 1]; 3201 else 3202 pmap_enter_locked(pmap, va, access, m, prot, 3203 FALSE, M_NOWAIT); 3204 m = TAILQ_NEXT(m, listq); 3205 } 3206 PMAP_UNLOCK(pmap); 3207 rw_wunlock(&pvh_global_lock); 3208} 3209 3210/* 3211 * this code makes some *MAJOR* assumptions: 3212 * 1. Current pmap & pmap exists. 3213 * 2. Not wired. 3214 * 3. Read access. 3215 * 4. No page table pages. 3216 * but is *MUCH* faster than pmap_enter... 3217 */ 3218 3219void 3220pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3221{ 3222 vm_prot_t access; 3223 3224 access = prot = prot & (VM_PROT_READ | VM_PROT_EXECUTE); 3225 rw_wlock(&pvh_global_lock); 3226 PMAP_LOCK(pmap); 3227 pmap_enter_locked(pmap, va, access, m, prot, FALSE, M_NOWAIT); 3228 PMAP_UNLOCK(pmap); 3229 rw_wunlock(&pvh_global_lock); 3230} 3231 3232/* 3233 * Routine: pmap_change_wiring 3234 * Function: Change the wiring attribute for a map/virtual-address 3235 * pair. 3236 * In/out conditions: 3237 * The mapping must already exist in the pmap. 3238 */ 3239void 3240pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3241{ 3242 struct l2_bucket *l2b; 3243 struct md_page *pvh; 3244 struct pv_entry *pve; 3245 pd_entry_t *pl1pd, l1pd; 3246 pt_entry_t *ptep, pte; 3247 vm_page_t m; 3248 3249 rw_wlock(&pvh_global_lock); 3250 PMAP_LOCK(pmap); 3251 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3252 l1pd = *pl1pd; 3253 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) { 3254 m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME); 3255 KASSERT((m != NULL) && ((m->oflags & VPO_UNMANAGED) == 0), 3256 ("pmap_change_wiring: unmanaged superpage should not " 3257 "be changed")); 3258 KASSERT(pmap != pmap_kernel(), 3259 ("pmap_change_wiring: managed kernel superpage " 3260 "should not exist")); 3261 pvh = pa_to_pvh(l1pd & L1_S_FRAME); 3262 pve = pmap_find_pv(pvh, pmap, trunc_1mpage(va)); 3263 if (!wired != ((pve->pv_flags & PVF_WIRED) == 0)) { 3264 if (!pmap_demote_section(pmap, va)) 3265 panic("pmap_change_wiring: demotion failed"); 3266 } else 3267 goto out; 3268 } 3269 l2b = pmap_get_l2_bucket(pmap, va); 3270 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3271 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3272 pte = *ptep; 3273 m = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3274 if (m != NULL) 3275 pmap_modify_pv(m, pmap, va, PVF_WIRED, 3276 wired == TRUE ? PVF_WIRED : 0); 3277out: 3278 rw_wunlock(&pvh_global_lock); 3279 PMAP_UNLOCK(pmap); 3280} 3281 3282 3283/* 3284 * Copy the range specified by src_addr/len 3285 * from the source map to the range dst_addr/len 3286 * in the destination map. 3287 * 3288 * This routine is only advisory and need not do anything. 3289 */ 3290void 3291pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3292 vm_size_t len, vm_offset_t src_addr) 3293{ 3294} 3295 3296 3297/* 3298 * Routine: pmap_extract 3299 * Function: 3300 * Extract the physical page address associated 3301 * with the given map/virtual_address pair. 3302 */ 3303vm_paddr_t 3304pmap_extract(pmap_t pmap, vm_offset_t va) 3305{ 3306 vm_paddr_t pa; 3307 3308 if (kernel_vm_end != 0) 3309 PMAP_LOCK(pmap); 3310 pa = pmap_extract_locked(pmap, va); 3311 if (kernel_vm_end != 0) 3312 PMAP_UNLOCK(pmap); 3313 return (pa); 3314} 3315 3316static vm_paddr_t 3317pmap_extract_locked(pmap_t pmap, vm_offset_t va) 3318{ 3319 struct l2_dtable *l2; 3320 pd_entry_t l1pd; 3321 pt_entry_t *ptep, pte; 3322 vm_paddr_t pa; 3323 u_int l1idx; 3324 3325 if (kernel_vm_end != 0 && pmap != kernel_pmap) 3326 PMAP_ASSERT_LOCKED(pmap); 3327 l1idx = L1_IDX(va); 3328 l1pd = pmap->pm_l1->l1_kva[l1idx]; 3329 if (l1pte_section_p(l1pd)) { 3330 /* 3331 * These should only happen for the kernel pmap. 3332 */ 3333 KASSERT(pmap == kernel_pmap, ("unexpected section")); 3334 /* XXX: what to do about the bits > 32 ? */ 3335 if (l1pd & L1_S_SUPERSEC) 3336 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3337 else 3338 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3339 } else { 3340 /* 3341 * Note that we can't rely on the validity of the L1 3342 * descriptor as an indication that a mapping exists. 3343 * We have to look it up in the L2 dtable. 3344 */ 3345 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3346 if (l2 == NULL || 3347 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) 3348 return (0); 3349 pte = ptep[l2pte_index(va)]; 3350 if (pte == 0) 3351 return (0); 3352 switch (pte & L2_TYPE_MASK) { 3353 case L2_TYPE_L: 3354 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3355 break; 3356 default: 3357 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3358 break; 3359 } 3360 } 3361 return (pa); 3362} 3363 3364/* 3365 * Atomically extract and hold the physical page with the given 3366 * pmap and virtual address pair if that mapping permits the given 3367 * protection. 3368 * 3369 */ 3370vm_page_t 3371pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3372{ 3373 struct l2_dtable *l2; 3374 pd_entry_t l1pd; 3375 pt_entry_t *ptep, pte; 3376 vm_paddr_t pa, paddr; 3377 vm_page_t m = NULL; 3378 u_int l1idx; 3379 l1idx = L1_IDX(va); 3380 paddr = 0; 3381 3382 PMAP_LOCK(pmap); 3383retry: 3384 l1pd = pmap->pm_l1->l1_kva[l1idx]; 3385 if (l1pte_section_p(l1pd)) { 3386 /* XXX: what to do about the bits > 32 ? */ 3387 if (l1pd & L1_S_SUPERSEC) 3388 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3389 else 3390 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3391 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3392 goto retry; 3393 if (L1_S_WRITABLE(l1pd) || (prot & VM_PROT_WRITE) == 0) { 3394 m = PHYS_TO_VM_PAGE(pa); 3395 vm_page_hold(m); 3396 } 3397 } else { 3398 /* 3399 * Note that we can't rely on the validity of the L1 3400 * descriptor as an indication that a mapping exists. 3401 * We have to look it up in the L2 dtable. 3402 */ 3403 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3404 3405 if (l2 == NULL || 3406 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3407 PMAP_UNLOCK(pmap); 3408 return (NULL); 3409 } 3410 3411 ptep = &ptep[l2pte_index(va)]; 3412 pte = *ptep; 3413 3414 if (pte == 0) { 3415 PMAP_UNLOCK(pmap); 3416 return (NULL); 3417 } else if ((prot & VM_PROT_WRITE) && (pte & L2_APX)) { 3418 PMAP_UNLOCK(pmap); 3419 return (NULL); 3420 } else { 3421 switch (pte & L2_TYPE_MASK) { 3422 case L2_TYPE_L: 3423 panic("extract and hold section mapping"); 3424 break; 3425 default: 3426 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3427 break; 3428 } 3429 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3430 goto retry; 3431 m = PHYS_TO_VM_PAGE(pa); 3432 vm_page_hold(m); 3433 } 3434 3435 } 3436 3437 PMAP_UNLOCK(pmap); 3438 PA_UNLOCK_COND(paddr); 3439 return (m); 3440} 3441 3442/* 3443 * Initialize a preallocated and zeroed pmap structure, 3444 * such as one in a vmspace structure. 3445 */ 3446 3447int 3448pmap_pinit(pmap_t pmap) 3449{ 3450 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3451 3452 pmap_alloc_l1(pmap); 3453 bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3454 3455 CPU_ZERO(&pmap->pm_active); 3456 3457 TAILQ_INIT(&pmap->pm_pvchunk); 3458 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3459 pmap->pm_stats.resident_count = 1; 3460 if (vector_page < KERNBASE) { 3461 pmap_enter(pmap, vector_page, 3462 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa), 3463 VM_PROT_READ, 1); 3464 } 3465 return (1); 3466} 3467 3468 3469/*************************************************** 3470 * Superpage management routines. 3471 ***************************************************/ 3472 3473static PMAP_INLINE struct pv_entry * 3474pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 3475{ 3476 pv_entry_t pv; 3477 3478 rw_assert(&pvh_global_lock, RA_WLOCKED); 3479 3480 pv = pmap_find_pv(pvh, pmap, va); 3481 if (pv != NULL) 3482 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 3483 3484 return (pv); 3485} 3486 3487static void 3488pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 3489{ 3490 pv_entry_t pv; 3491 3492 pv = pmap_pvh_remove(pvh, pmap, va); 3493 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 3494 pmap_free_pv_entry(pmap, pv); 3495} 3496 3497static boolean_t 3498pmap_pv_insert_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 3499{ 3500 struct md_page *pvh; 3501 pv_entry_t pv; 3502 3503 rw_assert(&pvh_global_lock, RA_WLOCKED); 3504 if (pv_entry_count < pv_entry_high_water && 3505 (pv = pmap_get_pv_entry(pmap, TRUE)) != NULL) { 3506 pv->pv_va = va; 3507 pvh = pa_to_pvh(pa); 3508 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 3509 return (TRUE); 3510 } else 3511 return (FALSE); 3512} 3513 3514/* 3515 * Create the pv entries for each of the pages within a superpage. 3516 */ 3517static void 3518pmap_pv_demote_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 3519{ 3520 struct md_page *pvh; 3521 pv_entry_t pve, pv; 3522 vm_offset_t va_last; 3523 vm_page_t m; 3524 3525 rw_assert(&pvh_global_lock, RA_WLOCKED); 3526 KASSERT((pa & L1_S_OFFSET) == 0, 3527 ("pmap_pv_demote_section: pa is not 1mpage aligned")); 3528 3529 /* 3530 * Transfer the 1mpage's pv entry for this mapping to the first 3531 * page's pv list. 3532 */ 3533 pvh = pa_to_pvh(pa); 3534 va = trunc_1mpage(va); 3535 pv = pmap_pvh_remove(pvh, pmap, va); 3536 KASSERT(pv != NULL, ("pmap_pv_demote_section: pv not found")); 3537 m = PHYS_TO_VM_PAGE(pa); 3538 TAILQ_INSERT_HEAD(&m->md.pv_list, pv, pv_list); 3539 /* Instantiate the remaining pv entries. */ 3540 va_last = L2_NEXT_BUCKET(va) - PAGE_SIZE; 3541 do { 3542 m++; 3543 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3544 ("pmap_pv_demote_section: page %p is not managed", m)); 3545 va += PAGE_SIZE; 3546 pve = pmap_get_pv_entry(pmap, FALSE); 3547 pmap_enter_pv(m, pve, pmap, va, pv->pv_flags); 3548 } while (va < va_last); 3549} 3550 3551static void 3552pmap_pv_promote_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 3553{ 3554 struct md_page *pvh; 3555 pv_entry_t pv; 3556 vm_offset_t va_last; 3557 vm_page_t m; 3558 3559 rw_assert(&pvh_global_lock, RA_WLOCKED); 3560 KASSERT((pa & L1_S_OFFSET) == 0, 3561 ("pmap_pv_promote_section: pa is not 1mpage aligned")); 3562 3563 /* 3564 * Transfer the first page's pv entry for this mapping to the 3565 * 1mpage's pv list. Aside from avoiding the cost of a call 3566 * to get_pv_entry(), a transfer avoids the possibility that 3567 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim() 3568 * removes one of the mappings that is being promoted. 3569 */ 3570 m = PHYS_TO_VM_PAGE(pa); 3571 va = trunc_1mpage(va); 3572 pv = pmap_pvh_remove(&m->md, pmap, va); 3573 KASSERT(pv != NULL, ("pmap_pv_promote_section: pv not found")); 3574 pvh = pa_to_pvh(pa); 3575 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 3576 /* Free the remaining pv entries in the newly mapped section pages */ 3577 va_last = L2_NEXT_BUCKET(va) - PAGE_SIZE; 3578 do { 3579 m++; 3580 va += PAGE_SIZE; 3581 /* 3582 * Don't care the flags, first pv contains sufficient 3583 * information for all of the pages so nothing is really lost. 3584 */ 3585 pmap_pvh_free(&m->md, pmap, va); 3586 } while (va < va_last); 3587} 3588 3589/* 3590 * Tries to create a 1MB page mapping. Returns TRUE if successful and 3591 * FALSE otherwise. Fails if (1) page is unmanageg, kernel pmap or vectors 3592 * page, (2) a mapping already exists at the specified virtual address, or 3593 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3594 */ 3595static boolean_t 3596pmap_enter_section(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3597{ 3598 pd_entry_t *pl1pd; 3599 vm_offset_t pa; 3600 struct l2_bucket *l2b; 3601 3602 rw_assert(&pvh_global_lock, RA_WLOCKED); 3603 PMAP_ASSERT_LOCKED(pmap); 3604 3605 /* Skip kernel, vectors page and unmanaged mappings */ 3606 if ((pmap == pmap_kernel()) || (L1_IDX(va) == L1_IDX(vector_page)) || 3607 ((m->oflags & VPO_UNMANAGED) != 0)) { 3608 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx" 3609 " in pmap %p", va, pmap); 3610 return (FALSE); 3611 } 3612 /* 3613 * Check whether this is a valid section superpage entry or 3614 * there is a l2_bucket associated with that L1 page directory. 3615 */ 3616 va = trunc_1mpage(va); 3617 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3618 l2b = pmap_get_l2_bucket(pmap, va); 3619 if ((*pl1pd & L1_S_PROTO) || (l2b != NULL)) { 3620 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx" 3621 " in pmap %p", va, pmap); 3622 return (FALSE); 3623 } 3624 pa = VM_PAGE_TO_PHYS(m); 3625 /* 3626 * Abort this mapping if its PV entry could not be created. 3627 */ 3628 if (!pmap_pv_insert_section(pmap, va, VM_PAGE_TO_PHYS(m))) { 3629 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx" 3630 " in pmap %p", va, pmap); 3631 return (FALSE); 3632 } 3633 /* 3634 * Increment counters. 3635 */ 3636 pmap->pm_stats.resident_count += L2_PTE_NUM_TOTAL; 3637 /* 3638 * Despite permissions, mark the superpage read-only. 3639 */ 3640 prot &= ~VM_PROT_WRITE; 3641 /* 3642 * Map the superpage. 3643 */ 3644 pmap_map_section(pmap, va, pa, prot, FALSE); 3645 3646 pmap_section_mappings++; 3647 CTR2(KTR_PMAP, "pmap_enter_section: success for va %#lx" 3648 " in pmap %p", va, pmap); 3649 return (TRUE); 3650} 3651 3652/* 3653 * pmap_remove_section: do the things to unmap a superpage in a process 3654 */ 3655static void 3656pmap_remove_section(pmap_t pmap, vm_offset_t sva) 3657{ 3658 struct md_page *pvh; 3659 struct l2_bucket *l2b; 3660 pd_entry_t *pl1pd, l1pd; 3661 vm_offset_t eva, va; 3662 vm_page_t m; 3663 3664 PMAP_ASSERT_LOCKED(pmap); 3665 if ((pmap == pmap_kernel()) || (L1_IDX(sva) == L1_IDX(vector_page))) 3666 return; 3667 3668 KASSERT((sva & L1_S_OFFSET) == 0, 3669 ("pmap_remove_section: sva is not 1mpage aligned")); 3670 3671 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)]; 3672 l1pd = *pl1pd; 3673 3674 m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME); 3675 KASSERT((m != NULL && ((m->oflags & VPO_UNMANAGED) == 0)), 3676 ("pmap_remove_section: no corresponding vm_page or " 3677 "page unmanaged")); 3678 3679 pmap->pm_stats.resident_count -= L2_PTE_NUM_TOTAL; 3680 pvh = pa_to_pvh(l1pd & L1_S_FRAME); 3681 pmap_pvh_free(pvh, pmap, sva); 3682 eva = L2_NEXT_BUCKET(sva); 3683 for (va = sva, m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME); 3684 va < eva; va += PAGE_SIZE, m++) { 3685 /* 3686 * Mark base pages referenced but skip marking them dirty. 3687 * If the superpage is writeable, hence all base pages were 3688 * already marked as dirty in pmap_fault_fixup() before 3689 * promotion. Reference bit however, might not have been set 3690 * for each base page when the superpage was created at once, 3691 * not as a result of promotion. 3692 */ 3693 if (L1_S_REFERENCED(l1pd)) 3694 vm_page_aflag_set(m, PGA_REFERENCED); 3695 if (TAILQ_EMPTY(&m->md.pv_list) && 3696 TAILQ_EMPTY(&pvh->pv_list)) 3697 vm_page_aflag_clear(m, PGA_WRITEABLE); 3698 } 3699 3700 l2b = pmap_get_l2_bucket(pmap, sva); 3701 if (l2b != NULL) { 3702 KASSERT(l2b->l2b_occupancy == L2_PTE_NUM_TOTAL, 3703 ("pmap_remove_section: l2_bucket occupancy error")); 3704 pmap_free_l2_bucket(pmap, l2b, L2_PTE_NUM_TOTAL); 3705 /* 3706 * Now invalidate L1 slot as it was not invalidated in 3707 * pmap_free_l2_bucket() due to L1_TYPE mismatch. 3708 */ 3709 *pl1pd = 0; 3710 PTE_SYNC(pl1pd); 3711 } 3712} 3713 3714/* 3715 * Tries to promote the 256, contiguous 4KB page mappings that are 3716 * within a single l2_bucket to a single 1MB section mapping. 3717 * For promotion to occur, two conditions must be met: (1) the 4KB page 3718 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3719 * mappings must have identical characteristics. 3720 */ 3721static void 3722pmap_promote_section(pmap_t pmap, vm_offset_t va) 3723{ 3724 pt_entry_t *firstptep, firstpte, oldpte, pa, *pte; 3725 vm_page_t m, oldm; 3726 vm_offset_t first_va, old_va; 3727 struct l2_bucket *l2b = NULL; 3728 vm_prot_t prot; 3729 struct pv_entry *pve, *first_pve; 3730 3731 PMAP_ASSERT_LOCKED(pmap); 3732 3733 prot = VM_PROT_ALL; 3734 /* 3735 * Skip promoting kernel pages. This is justified by following: 3736 * 1. Kernel is already mapped using section mappings in each pmap 3737 * 2. Managed mappings within the kernel are not to be promoted anyway 3738 */ 3739 if (pmap == pmap_kernel()) { 3740 pmap_section_p_failures++; 3741 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x" 3742 " in pmap %p", va, pmap); 3743 return; 3744 } 3745 /* Do not attemp to promote vectors pages */ 3746 if (L1_IDX(va) == L1_IDX(vector_page)) { 3747 pmap_section_p_failures++; 3748 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x" 3749 " in pmap %p", va, pmap); 3750 return; 3751 } 3752 /* 3753 * Examine the first PTE in the specified l2_bucket. Abort if this PTE 3754 * is either invalid, unused, or does not map the first 4KB physical 3755 * page within 1MB page. 3756 */ 3757 first_va = trunc_1mpage(va); 3758 l2b = pmap_get_l2_bucket(pmap, first_va); 3759 KASSERT(l2b != NULL, ("pmap_promote_section: trying to promote " 3760 "not existing l2 bucket")); 3761 firstptep = &l2b->l2b_kva[0]; 3762 3763 firstpte = *firstptep; 3764 if ((l2pte_pa(firstpte) & L1_S_OFFSET) != 0) { 3765 pmap_section_p_failures++; 3766 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x" 3767 " in pmap %p", va, pmap); 3768 return; 3769 } 3770 3771 if ((firstpte & (L2_S_PROTO | L2_S_REF)) != (L2_S_PROTO | L2_S_REF)) { 3772 pmap_section_p_failures++; 3773 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x" 3774 " in pmap %p", va, pmap); 3775 return; 3776 } 3777 /* 3778 * ARM uses pv_entry to mark particular mapping WIRED so don't promote 3779 * unmanaged pages since it is impossible to determine, whether the 3780 * page is wired or not if there is no corresponding pv_entry. 3781 */ 3782 m = PHYS_TO_VM_PAGE(l2pte_pa(firstpte)); 3783 if (m && ((m->oflags & VPO_UNMANAGED) != 0)) { 3784 pmap_section_p_failures++; 3785 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x" 3786 " in pmap %p", va, pmap); 3787 return; 3788 } 3789 first_pve = pmap_find_pv(&m->md, pmap, first_va); 3790 /* 3791 * PTE is modified only on write due to modified bit 3792 * emulation. If the entry is referenced and writable 3793 * then it is modified and we don't clear write enable. 3794 * Otherwise, writing is disabled in PTE anyway and 3795 * we just configure protections for the section mapping 3796 * that is going to be created. 3797 */ 3798 if (!L2_S_WRITABLE(firstpte) && (first_pve->pv_flags & PVF_WRITE)) { 3799 first_pve->pv_flags &= ~PVF_WRITE; 3800 prot &= ~VM_PROT_WRITE; 3801 } 3802 3803 if (!L2_S_EXECUTABLE(firstpte)) 3804 prot &= ~VM_PROT_EXECUTE; 3805 3806 /* 3807 * Examine each of the other PTEs in the specified l2_bucket. 3808 * Abort if this PTE maps an unexpected 4KB physical page or 3809 * does not have identical characteristics to the first PTE. 3810 */ 3811 pa = l2pte_pa(firstpte) + ((L2_PTE_NUM_TOTAL - 1) * PAGE_SIZE); 3812 old_va = L2_NEXT_BUCKET(first_va) - PAGE_SIZE; 3813 3814 for (pte = (firstptep + L2_PTE_NUM_TOTAL - 1); pte > firstptep; pte--) { 3815 oldpte = *pte; 3816 if (l2pte_pa(oldpte) != pa) { 3817 pmap_section_p_failures++; 3818 CTR2(KTR_PMAP, "pmap_promote_section: failure for " 3819 "va %#x in pmap %p", va, pmap); 3820 return; 3821 } 3822 if ((oldpte & L2_S_PROMOTE) != (firstpte & L2_S_PROMOTE)) { 3823 pmap_section_p_failures++; 3824 CTR2(KTR_PMAP, "pmap_promote_section: failure for " 3825 "va %#x in pmap %p", va, pmap); 3826 return; 3827 } 3828 oldm = PHYS_TO_VM_PAGE(l2pte_pa(oldpte)); 3829 if (oldm && ((oldm->oflags & VPO_UNMANAGED) != 0)) { 3830 pmap_section_p_failures++; 3831 CTR2(KTR_PMAP, "pmap_promote_section: failure for " 3832 "va %#x in pmap %p", va, pmap); 3833 return; 3834 } 3835 3836 pve = pmap_find_pv(&oldm->md, pmap, old_va); 3837 if (pve == NULL) { 3838 pmap_section_p_failures++; 3839 CTR2(KTR_PMAP, "pmap_promote_section: failure for " 3840 "va %#x old_va %x - no pve", va, old_va); 3841 return; 3842 } 3843 3844 if (!L2_S_WRITABLE(oldpte) && (pve->pv_flags & PVF_WRITE)) 3845 pve->pv_flags &= ~PVF_WRITE; 3846 3847 old_va -= PAGE_SIZE; 3848 pa -= PAGE_SIZE; 3849 } 3850 /* 3851 * Promote the pv entries. 3852 */ 3853 pmap_pv_promote_section(pmap, first_va, l2pte_pa(firstpte)); 3854 /* 3855 * Map the superpage. 3856 */ 3857 pmap_map_section(pmap, first_va, l2pte_pa(firstpte), prot, TRUE); 3858 pmap_section_promotions++; 3859 CTR2(KTR_PMAP, "pmap_promote_section: success for va %#x" 3860 " in pmap %p", first_va, pmap); 3861} 3862 3863/* 3864 * Fills a l2_bucket with mappings to consecutive physical pages. 3865 */ 3866static void 3867pmap_fill_l2b(struct l2_bucket *l2b, pt_entry_t newpte) 3868{ 3869 pt_entry_t *ptep; 3870 int i; 3871 3872 for (i = 0; i < L2_PTE_NUM_TOTAL; i++) { 3873 ptep = &l2b->l2b_kva[i]; 3874 *ptep = newpte; 3875 PTE_SYNC(ptep); 3876 3877 newpte += PAGE_SIZE; 3878 } 3879 3880 l2b->l2b_occupancy = L2_PTE_NUM_TOTAL; 3881} 3882 3883/* 3884 * Tries to demote a 1MB section mapping. If demotion fails, the 3885 * 1MB section mapping is invalidated. 3886 */ 3887static boolean_t 3888pmap_demote_section(pmap_t pmap, vm_offset_t va) 3889{ 3890 struct l2_bucket *l2b; 3891 struct pv_entry *l1pdpve; 3892 struct md_page *pvh; 3893 pd_entry_t *pl1pd, l1pd; 3894 pt_entry_t *firstptep, newpte; 3895 vm_offset_t pa; 3896 vm_page_t m; 3897 3898 PMAP_ASSERT_LOCKED(pmap); 3899 /* 3900 * According to assumptions described in pmap_promote_section, 3901 * kernel is and always should be mapped using 1MB section mappings. 3902 * What more, managed kernel pages were not to be promoted. 3903 */ 3904 KASSERT(pmap != pmap_kernel() && L1_IDX(va) != L1_IDX(vector_page), 3905 ("pmap_demote_section: forbidden section mapping")); 3906 3907 va = trunc_1mpage(va); 3908 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3909 l1pd = *pl1pd; 3910 KASSERT((l1pd & L1_TYPE_MASK) == L1_S_PROTO, 3911 ("pmap_demote_section: not section or invalid section")); 3912 3913 pa = l1pd & L1_S_FRAME; 3914 m = PHYS_TO_VM_PAGE(pa); 3915 KASSERT((m != NULL && (m->oflags & VPO_UNMANAGED) == 0), 3916 ("pmap_demote_section: no vm_page for selected superpage or" 3917 "unmanaged")); 3918 3919 pvh = pa_to_pvh(pa); 3920 l1pdpve = pmap_find_pv(pvh, pmap, va); 3921 KASSERT(l1pdpve != NULL, ("pmap_demote_section: no pv entry for " 3922 "managed page")); 3923 3924 l2b = pmap_get_l2_bucket(pmap, va); 3925 if (l2b == NULL) { 3926 KASSERT((l1pdpve->pv_flags & PVF_WIRED) == 0, 3927 ("pmap_demote_section: No l2_bucket for wired mapping")); 3928 /* 3929 * Invalidate the 1MB section mapping and return 3930 * "failure" if the mapping was never accessed or the 3931 * allocation of the new l2_bucket fails. 3932 */ 3933 if (!L1_S_REFERENCED(l1pd) || 3934 (l2b = pmap_alloc_l2_bucket(pmap, va)) == NULL) { 3935 /* Unmap and invalidate superpage. */ 3936 pmap_remove_section(pmap, trunc_1mpage(va)); 3937 CTR2(KTR_PMAP, "pmap_demote_section: failure for " 3938 "va %#x in pmap %p", va, pmap); 3939 return (FALSE); 3940 } 3941 } 3942 3943 /* 3944 * Now we should have corresponding l2_bucket available. 3945 * Let's process it to recreate 256 PTEs for each base page 3946 * within superpage. 3947 */ 3948 newpte = pa | L1_S_DEMOTE(l1pd); 3949 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 3950 newpte |= pte_l2_s_cache_mode; 3951 3952 /* 3953 * If the l2_bucket is new, initialize it. 3954 */ 3955 if (l2b->l2b_occupancy == 0) 3956 pmap_fill_l2b(l2b, newpte); 3957 else { 3958 firstptep = &l2b->l2b_kva[0]; 3959 KASSERT(l2pte_pa(*firstptep) == (pa), 3960 ("pmap_demote_section: firstpte and newpte map different " 3961 "physical addresses")); 3962 /* 3963 * If the mapping has changed attributes, update the page table 3964 * entries. 3965 */ 3966 if ((*firstptep & L2_S_PROMOTE) != (L1_S_DEMOTE(l1pd))) 3967 pmap_fill_l2b(l2b, newpte); 3968 } 3969 /* Demote PV entry */ 3970 pmap_pv_demote_section(pmap, va, pa); 3971 3972 /* Now fix-up L1 */ 3973 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | L1_C_PROTO; 3974 *pl1pd = l1pd; 3975 PTE_SYNC(pl1pd); 3976 3977 pmap_section_demotions++; 3978 CTR2(KTR_PMAP, "pmap_demote_section: success for va %#x" 3979 " in pmap %p", va, pmap); 3980 return (TRUE); 3981} 3982 3983/*************************************************** 3984 * page management routines. 3985 ***************************************************/ 3986 3987/* 3988 * We are in a serious low memory condition. Resort to 3989 * drastic measures to free some pages so we can allocate 3990 * another pv entry chunk. 3991 */ 3992static vm_page_t 3993pmap_pv_reclaim(pmap_t locked_pmap) 3994{ 3995 struct pch newtail; 3996 struct pv_chunk *pc; 3997 struct l2_bucket *l2b = NULL; 3998 pmap_t pmap; 3999 pd_entry_t *pl1pd; 4000 pt_entry_t *ptep; 4001 pv_entry_t pv; 4002 vm_offset_t va; 4003 vm_page_t free, m, m_pc; 4004 uint32_t inuse; 4005 int bit, field, freed, idx; 4006 4007 PMAP_ASSERT_LOCKED(locked_pmap); 4008 pmap = NULL; 4009 free = m_pc = NULL; 4010 TAILQ_INIT(&newtail); 4011 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 4012 free == NULL)) { 4013 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 4014 if (pmap != pc->pc_pmap) { 4015 if (pmap != NULL) { 4016 cpu_tlb_flushID(); 4017 cpu_cpwait(); 4018 if (pmap != locked_pmap) 4019 PMAP_UNLOCK(pmap); 4020 } 4021 pmap = pc->pc_pmap; 4022 /* Avoid deadlock and lock recursion. */ 4023 if (pmap > locked_pmap) 4024 PMAP_LOCK(pmap); 4025 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 4026 pmap = NULL; 4027 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 4028 continue; 4029 } 4030 } 4031 4032 /* 4033 * Destroy every non-wired, 4 KB page mapping in the chunk. 4034 */ 4035 freed = 0; 4036 for (field = 0; field < _NPCM; field++) { 4037 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 4038 inuse != 0; inuse &= ~(1UL << bit)) { 4039 bit = ffs(inuse) - 1; 4040 idx = field * sizeof(inuse) * NBBY + bit; 4041 pv = &pc->pc_pventry[idx]; 4042 va = pv->pv_va; 4043 4044 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 4045 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO) 4046 continue; 4047 if (pv->pv_flags & PVF_WIRED) 4048 continue; 4049 4050 l2b = pmap_get_l2_bucket(pmap, va); 4051 KASSERT(l2b != NULL, ("No l2 bucket")); 4052 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4053 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep)); 4054 KASSERT((vm_offset_t)m >= KERNBASE, 4055 ("Trying to access non-existent page " 4056 "va %x pte %x", va, *ptep)); 4057 *ptep = 0; 4058 PTE_SYNC(ptep); 4059 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4060 if (TAILQ_EMPTY(&m->md.pv_list)) 4061 vm_page_aflag_clear(m, PGA_WRITEABLE); 4062 pc->pc_map[field] |= 1UL << bit; 4063 freed++; 4064 } 4065 } 4066 4067 if (freed == 0) { 4068 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 4069 continue; 4070 } 4071 /* Every freed mapping is for a 4 KB page. */ 4072 pmap->pm_stats.resident_count -= freed; 4073 PV_STAT(pv_entry_frees += freed); 4074 PV_STAT(pv_entry_spare += freed); 4075 pv_entry_count -= freed; 4076 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4077 for (field = 0; field < _NPCM; field++) 4078 if (pc->pc_map[field] != pc_freemask[field]) { 4079 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 4080 pc_list); 4081 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 4082 4083 /* 4084 * One freed pv entry in locked_pmap is 4085 * sufficient. 4086 */ 4087 if (pmap == locked_pmap) 4088 goto out; 4089 break; 4090 } 4091 if (field == _NPCM) { 4092 PV_STAT(pv_entry_spare -= _NPCPV); 4093 PV_STAT(pc_chunk_count--); 4094 PV_STAT(pc_chunk_frees++); 4095 /* Entire chunk is free; return it. */ 4096 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4097 pmap_qremove((vm_offset_t)pc, 1); 4098 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4099 break; 4100 } 4101 } 4102out: 4103 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 4104 if (pmap != NULL) { 4105 cpu_tlb_flushID(); 4106 cpu_cpwait(); 4107 if (pmap != locked_pmap) 4108 PMAP_UNLOCK(pmap); 4109 } 4110 return (m_pc); 4111} 4112 4113/* 4114 * free the pv_entry back to the free list 4115 */ 4116static void 4117pmap_free_pv_entry(pmap_t pmap, pv_entry_t pv) 4118{ 4119 struct pv_chunk *pc; 4120 int bit, field, idx; 4121 4122 rw_assert(&pvh_global_lock, RA_WLOCKED); 4123 PMAP_ASSERT_LOCKED(pmap); 4124 PV_STAT(pv_entry_frees++); 4125 PV_STAT(pv_entry_spare++); 4126 pv_entry_count--; 4127 pc = pv_to_chunk(pv); 4128 idx = pv - &pc->pc_pventry[0]; 4129 field = idx / (sizeof(u_long) * NBBY); 4130 bit = idx % (sizeof(u_long) * NBBY); 4131 pc->pc_map[field] |= 1ul << bit; 4132 for (idx = 0; idx < _NPCM; idx++) 4133 if (pc->pc_map[idx] != pc_freemask[idx]) { 4134 /* 4135 * 98% of the time, pc is already at the head of the 4136 * list. If it isn't already, move it to the head. 4137 */ 4138 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 4139 pc)) { 4140 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4141 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 4142 pc_list); 4143 } 4144 return; 4145 } 4146 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4147 pmap_free_pv_chunk(pc); 4148} 4149 4150static void 4151pmap_free_pv_chunk(struct pv_chunk *pc) 4152{ 4153 vm_page_t m; 4154 4155 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 4156 PV_STAT(pv_entry_spare -= _NPCPV); 4157 PV_STAT(pc_chunk_count--); 4158 PV_STAT(pc_chunk_frees++); 4159 /* entire chunk is free, return it */ 4160 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4161 pmap_qremove((vm_offset_t)pc, 1); 4162 vm_page_unwire(m, 0); 4163 vm_page_free(m); 4164 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4165 4166} 4167 4168static pv_entry_t 4169pmap_get_pv_entry(pmap_t pmap, boolean_t try) 4170{ 4171 static const struct timeval printinterval = { 60, 0 }; 4172 static struct timeval lastprint; 4173 struct pv_chunk *pc; 4174 pv_entry_t pv; 4175 vm_page_t m; 4176 int bit, field, idx; 4177 4178 rw_assert(&pvh_global_lock, RA_WLOCKED); 4179 PMAP_ASSERT_LOCKED(pmap); 4180 PV_STAT(pv_entry_allocs++); 4181 pv_entry_count++; 4182 4183 if (pv_entry_count > pv_entry_high_water) 4184 if (ratecheck(&lastprint, &printinterval)) 4185 printf("%s: Approaching the limit on PV entries.\n", 4186 __func__); 4187retry: 4188 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 4189 if (pc != NULL) { 4190 for (field = 0; field < _NPCM; field++) { 4191 if (pc->pc_map[field]) { 4192 bit = ffs(pc->pc_map[field]) - 1; 4193 break; 4194 } 4195 } 4196 if (field < _NPCM) { 4197 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit; 4198 pv = &pc->pc_pventry[idx]; 4199 pc->pc_map[field] &= ~(1ul << bit); 4200 /* If this was the last item, move it to tail */ 4201 for (field = 0; field < _NPCM; field++) 4202 if (pc->pc_map[field] != 0) { 4203 PV_STAT(pv_entry_spare--); 4204 return (pv); /* not full, return */ 4205 } 4206 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4207 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 4208 PV_STAT(pv_entry_spare--); 4209 return (pv); 4210 } 4211 } 4212 /* 4213 * Access to the ptelist "pv_vafree" is synchronized by the pvh 4214 * global lock. If "pv_vafree" is currently non-empty, it will 4215 * remain non-empty until pmap_ptelist_alloc() completes. 4216 */ 4217 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 4218 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 4219 if (try) { 4220 pv_entry_count--; 4221 PV_STAT(pc_chunk_tryfail++); 4222 return (NULL); 4223 } 4224 m = pmap_pv_reclaim(pmap); 4225 if (m == NULL) 4226 goto retry; 4227 } 4228 PV_STAT(pc_chunk_count++); 4229 PV_STAT(pc_chunk_allocs++); 4230 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 4231 pmap_qenter((vm_offset_t)pc, &m, 1); 4232 pc->pc_pmap = pmap; 4233 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 4234 for (field = 1; field < _NPCM; field++) 4235 pc->pc_map[field] = pc_freemask[field]; 4236 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 4237 pv = &pc->pc_pventry[0]; 4238 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 4239 PV_STAT(pv_entry_spare += _NPCPV - 1); 4240 return (pv); 4241} 4242 4243/* 4244 * Remove the given range of addresses from the specified map. 4245 * 4246 * It is assumed that the start and end are properly 4247 * rounded to the page size. 4248 */ 4249#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 4250void 4251pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 4252{ 4253 struct l2_bucket *l2b; 4254 vm_offset_t next_bucket; 4255 pd_entry_t *pl1pd, l1pd; 4256 pt_entry_t *ptep; 4257 u_int total; 4258 u_int mappings, is_exec, is_refd; 4259 int flushall = 0; 4260 4261 4262 /* 4263 * we lock in the pmap => pv_head direction 4264 */ 4265 4266 rw_wlock(&pvh_global_lock); 4267 PMAP_LOCK(pmap); 4268 total = 0; 4269 while (sva < eva) { 4270 /* 4271 * Check for large page. 4272 */ 4273 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)]; 4274 l1pd = *pl1pd; 4275 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) { 4276 KASSERT((l1pd & L1_S_DOM_MASK) != 4277 L1_S_DOM(PMAP_DOMAIN_KERNEL), ("pmap_remove: " 4278 "Trying to remove kernel section mapping")); 4279 /* 4280 * Are we removing the entire large page? If not, 4281 * demote the mapping and fall through. 4282 */ 4283 if (sva + L1_S_SIZE == L2_NEXT_BUCKET(sva) && 4284 eva >= L2_NEXT_BUCKET(sva)) { 4285 pmap_remove_section(pmap, sva); 4286 sva = L2_NEXT_BUCKET(sva); 4287 continue; 4288 } else if (!pmap_demote_section(pmap, sva)) { 4289 /* The large page mapping was destroyed. */ 4290 sva = L2_NEXT_BUCKET(sva); 4291 continue; 4292 } 4293 } 4294 /* 4295 * Do one L2 bucket's worth at a time. 4296 */ 4297 next_bucket = L2_NEXT_BUCKET(sva); 4298 if (next_bucket > eva) 4299 next_bucket = eva; 4300 4301 l2b = pmap_get_l2_bucket(pmap, sva); 4302 if (l2b == NULL) { 4303 sva = next_bucket; 4304 continue; 4305 } 4306 4307 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4308 mappings = 0; 4309 4310 while (sva < next_bucket) { 4311 struct vm_page *m; 4312 pt_entry_t pte; 4313 vm_paddr_t pa; 4314 4315 pte = *ptep; 4316 4317 if (pte == 0) { 4318 /* 4319 * Nothing here, move along 4320 */ 4321 sva += PAGE_SIZE; 4322 ptep++; 4323 continue; 4324 } 4325 4326 pmap->pm_stats.resident_count--; 4327 pa = l2pte_pa(pte); 4328 is_exec = 0; 4329 is_refd = 1; 4330 4331 /* 4332 * Update flags. In a number of circumstances, 4333 * we could cluster a lot of these and do a 4334 * number of sequential pages in one go. 4335 */ 4336 if ((m = PHYS_TO_VM_PAGE(pa)) != NULL) { 4337 struct pv_entry *pve; 4338 4339 pve = pmap_remove_pv(m, pmap, sva); 4340 if (pve) { 4341 is_exec = PTE_BEEN_EXECD(pte); 4342 is_refd = PTE_BEEN_REFD(pte); 4343 pmap_free_pv_entry(pmap, pve); 4344 } 4345 } 4346 4347 if (pmap_is_current(pmap)) { 4348 total++; 4349 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) { 4350 if (is_exec) 4351 cpu_tlb_flushID_SE(sva); 4352 else if (is_refd) 4353 cpu_tlb_flushD_SE(sva); 4354 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) 4355 flushall = 1; 4356 } 4357 *ptep = 0; 4358 PTE_SYNC(ptep); 4359 4360 sva += PAGE_SIZE; 4361 ptep++; 4362 mappings++; 4363 } 4364 4365 pmap_free_l2_bucket(pmap, l2b, mappings); 4366 } 4367 4368 rw_wunlock(&pvh_global_lock); 4369 if (flushall) 4370 cpu_tlb_flushID(); 4371 PMAP_UNLOCK(pmap); 4372} 4373 4374/* 4375 * pmap_zero_page() 4376 * 4377 * Zero a given physical page by mapping it at a page hook point. 4378 * In doing the zero page op, the page we zero is mapped cachable, as with 4379 * StrongARM accesses to non-cached pages are non-burst making writing 4380 * _any_ bulk data very slow. 4381 */ 4382static void 4383pmap_zero_page_gen(vm_page_t m, int off, int size) 4384{ 4385 4386 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 4387 if (!TAILQ_EMPTY(&m->md.pv_list)) 4388 panic("pmap_zero_page: page has mappings"); 4389 4390 mtx_lock(&cmtx); 4391 /* 4392 * Hook in the page, zero it, invalidate the TLB as needed. 4393 * 4394 * Note the temporary zero-page mapping must be a non-cached page in 4395 * order to work without corruption when write-allocate is enabled. 4396 */ 4397 *cdst_pte = L2_S_PROTO | phys | pte_l2_s_cache_mode | L2_S_REF; 4398 pmap_set_prot(cdst_pte, VM_PROT_WRITE, 0); 4399 PTE_SYNC(cdst_pte); 4400 cpu_tlb_flushD_SE(cdstp); 4401 cpu_cpwait(); 4402 if (off || size != PAGE_SIZE) 4403 bzero((void *)(cdstp + off), size); 4404 else 4405 bzero_page(cdstp); 4406 4407 /* 4408 * Although aliasing is not possible if we use 4409 * cdstp temporary mappings with memory that 4410 * will be mapped later as non-cached or with write-through 4411 * caches we might end up overwriting it when calling wbinv_all 4412 * So make sure caches are clean after copy operation 4413 */ 4414 cpu_idcache_wbinv_range(cdstp, size); 4415 pmap_l2cache_wbinv_range(cdstp, phys, size); 4416 4417 mtx_unlock(&cmtx); 4418} 4419 4420/* 4421 * pmap_zero_page zeros the specified hardware page by mapping 4422 * the page into KVM and using bzero to clear its contents. 4423 */ 4424void 4425pmap_zero_page(vm_page_t m) 4426{ 4427 pmap_zero_page_gen(m, 0, PAGE_SIZE); 4428} 4429 4430 4431/* 4432 * pmap_zero_page_area zeros the specified hardware page by mapping 4433 * the page into KVM and using bzero to clear its contents. 4434 * 4435 * off and size may not cover an area beyond a single hardware page. 4436 */ 4437void 4438pmap_zero_page_area(vm_page_t m, int off, int size) 4439{ 4440 4441 pmap_zero_page_gen(m, off, size); 4442} 4443 4444 4445/* 4446 * pmap_zero_page_idle zeros the specified hardware page by mapping 4447 * the page into KVM and using bzero to clear its contents. This 4448 * is intended to be called from the vm_pagezero process only and 4449 * outside of Giant. 4450 */ 4451void 4452pmap_zero_page_idle(vm_page_t m) 4453{ 4454 4455 pmap_zero_page(m); 4456} 4457 4458/* 4459 * pmap_copy_page copies the specified (machine independent) 4460 * page by mapping the page into virtual memory and using 4461 * bcopy to copy the page, one machine dependent page at a 4462 * time. 4463 */ 4464 4465/* 4466 * pmap_copy_page() 4467 * 4468 * Copy one physical page into another, by mapping the pages into 4469 * hook points. The same comment regarding cachability as in 4470 * pmap_zero_page also applies here. 4471 */ 4472void 4473pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4474{ 4475 /* 4476 * Hold the source page's lock for the duration of the copy 4477 * so that no other mappings can be created while we have a 4478 * potentially aliased mapping. 4479 * Map the pages into the page hook points, copy them, and purge 4480 * the cache for the appropriate page. Invalidate the TLB 4481 * as required. 4482 */ 4483 mtx_lock(&cmtx); 4484 4485 /* For ARMv6 using System bit is deprecated and mapping with AP 4486 * bits set to 0x0 makes page not accessible. csrc_pte is mapped 4487 * read/write until proper mapping defines are created for ARMv6. 4488 */ 4489 *csrc_pte = L2_S_PROTO | src | pte_l2_s_cache_mode | L2_S_REF; 4490 pmap_set_prot(csrc_pte, VM_PROT_READ, 0); 4491 PTE_SYNC(csrc_pte); 4492 4493 *cdst_pte = L2_S_PROTO | dst | pte_l2_s_cache_mode | L2_S_REF; 4494 pmap_set_prot(cdst_pte, VM_PROT_READ | VM_PROT_WRITE, 0); 4495 PTE_SYNC(cdst_pte); 4496 4497 cpu_tlb_flushD_SE(csrcp); 4498 cpu_tlb_flushD_SE(cdstp); 4499 cpu_cpwait(); 4500 4501 /* 4502 * Although aliasing is not possible if we use 4503 * cdstp temporary mappings with memory that 4504 * will be mapped later as non-cached or with write-through 4505 * caches we might end up overwriting it when calling wbinv_all 4506 * So make sure caches are clean after copy operation 4507 */ 4508 bcopy_page(csrcp, cdstp); 4509 4510 cpu_idcache_wbinv_range(cdstp, PAGE_SIZE); 4511 pmap_l2cache_wbinv_range(cdstp, dst, PAGE_SIZE); 4512 4513 mtx_unlock(&cmtx); 4514} 4515 4516int unmapped_buf_allowed = 1; 4517 4518void 4519pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4520 vm_offset_t b_offset, int xfersize) 4521{ 4522 vm_page_t a_pg, b_pg; 4523 vm_offset_t a_pg_offset, b_pg_offset; 4524 int cnt; 4525 4526 mtx_lock(&cmtx); 4527 while (xfersize > 0) { 4528 a_pg = ma[a_offset >> PAGE_SHIFT]; 4529 a_pg_offset = a_offset & PAGE_MASK; 4530 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4531 b_pg = mb[b_offset >> PAGE_SHIFT]; 4532 b_pg_offset = b_offset & PAGE_MASK; 4533 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4534 *csrc_pte = L2_S_PROTO | VM_PAGE_TO_PHYS(a_pg) | 4535 pte_l2_s_cache_mode | L2_S_REF; 4536 pmap_set_prot(csrc_pte, VM_PROT_READ, 0); 4537 PTE_SYNC(csrc_pte); 4538 *cdst_pte = L2_S_PROTO | VM_PAGE_TO_PHYS(b_pg) | 4539 pte_l2_s_cache_mode | L2_S_REF; 4540 pmap_set_prot(cdst_pte, VM_PROT_READ | VM_PROT_WRITE, 0); 4541 PTE_SYNC(cdst_pte); 4542 cpu_tlb_flushD_SE(csrcp); 4543 cpu_tlb_flushD_SE(cdstp); 4544 cpu_cpwait(); 4545 bcopy((char *)csrcp + a_pg_offset, (char *)cdstp + b_pg_offset, 4546 cnt); 4547 cpu_idcache_wbinv_range(cdstp + b_pg_offset, cnt); 4548 pmap_l2cache_wbinv_range(cdstp + b_pg_offset, 4549 VM_PAGE_TO_PHYS(b_pg) + b_pg_offset, cnt); 4550 xfersize -= cnt; 4551 a_offset += cnt; 4552 b_offset += cnt; 4553 } 4554 mtx_unlock(&cmtx); 4555} 4556 4557void 4558pmap_copy_page(vm_page_t src, vm_page_t dst) 4559{ 4560 4561 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size && 4562 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4563 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4564 return; 4565 4566 pmap_copy_page_generic(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4567} 4568 4569/* 4570 * this routine returns true if a physical page resides 4571 * in the given pmap. 4572 */ 4573boolean_t 4574pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4575{ 4576 struct md_page *pvh; 4577 pv_entry_t pv; 4578 int loops = 0; 4579 boolean_t rv; 4580 4581 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4582 ("pmap_page_exists_quick: page %p is not managed", m)); 4583 rv = FALSE; 4584 rw_wlock(&pvh_global_lock); 4585 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4586 if (PV_PMAP(pv) == pmap) { 4587 rv = TRUE; 4588 break; 4589 } 4590 loops++; 4591 if (loops >= 16) 4592 break; 4593 } 4594 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 4595 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4596 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4597 if (PV_PMAP(pv) == pmap) { 4598 rv = TRUE; 4599 break; 4600 } 4601 loops++; 4602 if (loops >= 16) 4603 break; 4604 } 4605 } 4606 rw_wunlock(&pvh_global_lock); 4607 return (rv); 4608} 4609 4610/* 4611 * pmap_page_wired_mappings: 4612 * 4613 * Return the number of managed mappings to the given physical page 4614 * that are wired. 4615 */ 4616int 4617pmap_page_wired_mappings(vm_page_t m) 4618{ 4619 int count; 4620 4621 count = 0; 4622 if ((m->oflags & VPO_UNMANAGED) != 0) 4623 return (count); 4624 rw_wlock(&pvh_global_lock); 4625 count = pmap_pvh_wired_mappings(&m->md, count); 4626 if ((m->flags & PG_FICTITIOUS) == 0) { 4627 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), 4628 count); 4629 } 4630 rw_wunlock(&pvh_global_lock); 4631 return (count); 4632} 4633 4634/* 4635 * pmap_pvh_wired_mappings: 4636 * 4637 * Return the updated number "count" of managed mappings that are wired. 4638 */ 4639static int 4640pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4641{ 4642 pv_entry_t pv; 4643 4644 rw_assert(&pvh_global_lock, RA_WLOCKED); 4645 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4646 if ((pv->pv_flags & PVF_WIRED) != 0) 4647 count++; 4648 } 4649 return (count); 4650} 4651 4652/* 4653 * Returns TRUE if any of the given mappings were referenced and FALSE 4654 * otherwise. Both page and section mappings are supported. 4655 */ 4656static boolean_t 4657pmap_is_referenced_pvh(struct md_page *pvh) 4658{ 4659 struct l2_bucket *l2b; 4660 pv_entry_t pv; 4661 pd_entry_t *pl1pd; 4662 pt_entry_t *ptep; 4663 pmap_t pmap; 4664 boolean_t rv; 4665 4666 rw_assert(&pvh_global_lock, RA_WLOCKED); 4667 rv = FALSE; 4668 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4669 pmap = PV_PMAP(pv); 4670 PMAP_LOCK(pmap); 4671 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)]; 4672 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO) 4673 rv = L1_S_REFERENCED(*pl1pd); 4674 else { 4675 l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 4676 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 4677 rv = L2_S_REFERENCED(*ptep); 4678 } 4679 PMAP_UNLOCK(pmap); 4680 if (rv) 4681 break; 4682 } 4683 return (rv); 4684} 4685 4686/* 4687 * pmap_is_referenced: 4688 * 4689 * Return whether or not the specified physical page was referenced 4690 * in any physical maps. 4691 */ 4692boolean_t 4693pmap_is_referenced(vm_page_t m) 4694{ 4695 boolean_t rv; 4696 4697 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4698 ("pmap_is_referenced: page %p is not managed", m)); 4699 rw_wlock(&pvh_global_lock); 4700 rv = pmap_is_referenced_pvh(&m->md) || 4701 ((m->flags & PG_FICTITIOUS) == 0 && 4702 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4703 rw_wunlock(&pvh_global_lock); 4704 return (rv); 4705} 4706 4707/* 4708 * pmap_ts_referenced: 4709 * 4710 * Return the count of reference bits for a page, clearing all of them. 4711 */ 4712int 4713pmap_ts_referenced(vm_page_t m) 4714{ 4715 4716 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4717 ("pmap_ts_referenced: page %p is not managed", m)); 4718 return (pmap_clearbit(m, PVF_REF)); 4719} 4720 4721/* 4722 * Returns TRUE if any of the given mappings were used to modify 4723 * physical memory. Otherwise, returns FALSE. Both page and 1MB section 4724 * mappings are supported. 4725 */ 4726static boolean_t 4727pmap_is_modified_pvh(struct md_page *pvh) 4728{ 4729 pd_entry_t *pl1pd; 4730 struct l2_bucket *l2b; 4731 pv_entry_t pv; 4732 pt_entry_t *ptep; 4733 pmap_t pmap; 4734 boolean_t rv; 4735 4736 rw_assert(&pvh_global_lock, RA_WLOCKED); 4737 rv = FALSE; 4738 4739 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4740 pmap = PV_PMAP(pv); 4741 PMAP_LOCK(pmap); 4742 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)]; 4743 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO) 4744 rv = L1_S_WRITABLE(*pl1pd); 4745 else { 4746 l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 4747 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 4748 rv = L2_S_WRITABLE(*ptep); 4749 } 4750 PMAP_UNLOCK(pmap); 4751 if (rv) 4752 break; 4753 } 4754 4755 return (rv); 4756} 4757 4758boolean_t 4759pmap_is_modified(vm_page_t m) 4760{ 4761 boolean_t rv; 4762 4763 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4764 ("pmap_is_modified: page %p is not managed", m)); 4765 /* 4766 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4767 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 4768 * is clear, no PTEs can have APX cleared. 4769 */ 4770 VM_OBJECT_ASSERT_WLOCKED(m->object); 4771 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4772 return (FALSE); 4773 rw_wlock(&pvh_global_lock); 4774 rv = pmap_is_modified_pvh(&m->md) || 4775 ((m->flags & PG_FICTITIOUS) == 0 && 4776 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4777 rw_wunlock(&pvh_global_lock); 4778 return (rv); 4779} 4780 4781/* 4782 * Apply the given advice to the specified range of addresses within the 4783 * given pmap. Depending on the advice, clear the referenced and/or 4784 * modified flags in each mapping. 4785 */ 4786void 4787pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4788{ 4789 struct l2_bucket *l2b; 4790 struct pv_entry *pve; 4791 pd_entry_t *pl1pd, l1pd; 4792 pt_entry_t *ptep, opte, pte; 4793 vm_offset_t next_bucket; 4794 vm_page_t m; 4795 4796 if (advice != MADV_DONTNEED && advice != MADV_FREE) 4797 return; 4798 rw_wlock(&pvh_global_lock); 4799 PMAP_LOCK(pmap); 4800 for (; sva < eva; sva = next_bucket) { 4801 next_bucket = L2_NEXT_BUCKET(sva); 4802 if (next_bucket < sva) 4803 next_bucket = eva; 4804 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)]; 4805 l1pd = *pl1pd; 4806 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) { 4807 if (pmap == pmap_kernel()) 4808 continue; 4809 if (!pmap_demote_section(pmap, sva)) { 4810 /* 4811 * The large page mapping was destroyed. 4812 */ 4813 continue; 4814 } 4815 /* 4816 * Unless the page mappings are wired, remove the 4817 * mapping to a single page so that a subsequent 4818 * access may repromote. Since the underlying 4819 * l2_bucket is fully populated, this removal 4820 * never frees an entire l2_bucket. 4821 */ 4822 l2b = pmap_get_l2_bucket(pmap, sva); 4823 KASSERT(l2b != NULL, 4824 ("pmap_advise: no l2 bucket for " 4825 "va 0x%#x, pmap 0x%p", sva, pmap)); 4826 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4827 opte = *ptep; 4828 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep)); 4829 KASSERT(m != NULL, 4830 ("pmap_advise: no vm_page for demoted superpage")); 4831 pve = pmap_find_pv(&m->md, pmap, sva); 4832 KASSERT(pve != NULL, 4833 ("pmap_advise: no PV entry for managed mapping")); 4834 if ((pve->pv_flags & PVF_WIRED) == 0) { 4835 pmap_free_l2_bucket(pmap, l2b, 1); 4836 pve = pmap_remove_pv(m, pmap, sva); 4837 pmap_free_pv_entry(pmap, pve); 4838 *ptep = 0; 4839 PTE_SYNC(ptep); 4840 if (pmap_is_current(pmap)) { 4841 if (PTE_BEEN_EXECD(opte)) 4842 cpu_tlb_flushID_SE(sva); 4843 else if (PTE_BEEN_REFD(opte)) 4844 cpu_tlb_flushD_SE(sva); 4845 } 4846 } 4847 } 4848 if (next_bucket > eva) 4849 next_bucket = eva; 4850 l2b = pmap_get_l2_bucket(pmap, sva); 4851 if (l2b == NULL) 4852 continue; 4853 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4854 sva != next_bucket; ptep++, sva += PAGE_SIZE) { 4855 opte = pte = *ptep; 4856 if ((opte & L2_S_PROTO) == 0) 4857 continue; 4858 m = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4859 if (m == NULL || (m->oflags & VPO_UNMANAGED) != 0) 4860 continue; 4861 else if (L2_S_WRITABLE(opte)) { 4862 if (advice == MADV_DONTNEED) { 4863 /* 4864 * Don't need to mark the page 4865 * dirty as it was already marked as 4866 * such in pmap_fault_fixup() or 4867 * pmap_enter_locked(). 4868 * Just clear the state. 4869 */ 4870 } else 4871 pte |= L2_APX; 4872 4873 pte &= ~L2_S_REF; 4874 *ptep = pte; 4875 PTE_SYNC(ptep); 4876 } else if (L2_S_REFERENCED(opte)) { 4877 pte &= ~L2_S_REF; 4878 *ptep = pte; 4879 PTE_SYNC(ptep); 4880 } else 4881 continue; 4882 if (pmap_is_current(pmap)) { 4883 if (PTE_BEEN_EXECD(opte)) 4884 cpu_tlb_flushID_SE(sva); 4885 else if (PTE_BEEN_REFD(opte)) 4886 cpu_tlb_flushD_SE(sva); 4887 } 4888 } 4889 } 4890 rw_wunlock(&pvh_global_lock); 4891 PMAP_UNLOCK(pmap); 4892} 4893 4894/* 4895 * Clear the modify bits on the specified physical page. 4896 */ 4897void 4898pmap_clear_modify(vm_page_t m) 4899{ 4900 4901 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4902 ("pmap_clear_modify: page %p is not managed", m)); 4903 VM_OBJECT_ASSERT_WLOCKED(m->object); 4904 KASSERT(!vm_page_xbusied(m), 4905 ("pmap_clear_modify: page %p is exclusive busied", m)); 4906 4907 /* 4908 * If the page is not PGA_WRITEABLE, then no mappings can be modified. 4909 * If the object containing the page is locked and the page is not 4910 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4911 */ 4912 if ((m->aflags & PGA_WRITEABLE) == 0) 4913 return; 4914 if (pmap_is_modified(m)) 4915 pmap_clearbit(m, PVF_MOD); 4916} 4917 4918 4919/* 4920 * Clear the write and modified bits in each of the given page's mappings. 4921 */ 4922void 4923pmap_remove_write(vm_page_t m) 4924{ 4925 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4926 ("pmap_remove_write: page %p is not managed", m)); 4927 4928 /* 4929 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4930 * set by another thread while the object is locked. Thus, 4931 * if PGA_WRITEABLE is clear, no page table entries need updating. 4932 */ 4933 VM_OBJECT_ASSERT_WLOCKED(m->object); 4934 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0) 4935 pmap_clearbit(m, PVF_WRITE); 4936} 4937 4938 4939/* 4940 * perform the pmap work for mincore 4941 */ 4942int 4943pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4944{ 4945 struct l2_bucket *l2b; 4946 pd_entry_t *pl1pd, l1pd; 4947 pt_entry_t *ptep, pte; 4948 vm_paddr_t pa; 4949 vm_page_t m; 4950 int val; 4951 boolean_t managed; 4952 4953 PMAP_LOCK(pmap); 4954retry: 4955 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(addr)]; 4956 l1pd = *pl1pd; 4957 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) { 4958 pa = (l1pd & L1_S_FRAME); 4959 val = MINCORE_SUPER | MINCORE_INCORE; 4960 if (L1_S_WRITABLE(l1pd)) 4961 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4962 managed = FALSE; 4963 m = PHYS_TO_VM_PAGE(pa); 4964 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0) 4965 managed = TRUE; 4966 if (managed) { 4967 if (L1_S_REFERENCED(l1pd)) 4968 val |= MINCORE_REFERENCED | 4969 MINCORE_REFERENCED_OTHER; 4970 } 4971 } else { 4972 l2b = pmap_get_l2_bucket(pmap, addr); 4973 if (l2b == NULL) { 4974 val = 0; 4975 goto out; 4976 } 4977 ptep = &l2b->l2b_kva[l2pte_index(addr)]; 4978 pte = *ptep; 4979 if (!l2pte_valid(pte)) { 4980 val = 0; 4981 goto out; 4982 } 4983 val = MINCORE_INCORE; 4984 if (L2_S_WRITABLE(pte)) 4985 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4986 managed = FALSE; 4987 pa = l2pte_pa(pte); 4988 m = PHYS_TO_VM_PAGE(pa); 4989 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0) 4990 managed = TRUE; 4991 if (managed) { 4992 if (L2_S_REFERENCED(pte)) 4993 val |= MINCORE_REFERENCED | 4994 MINCORE_REFERENCED_OTHER; 4995 } 4996 } 4997 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4998 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 4999 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5000 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5001 goto retry; 5002 } else 5003out: 5004 PA_UNLOCK_COND(*locked_pa); 5005 PMAP_UNLOCK(pmap); 5006 return (val); 5007} 5008 5009void 5010pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz) 5011{ 5012} 5013 5014/* 5015 * Increase the starting virtual address of the given mapping if a 5016 * different alignment might result in more superpage mappings. 5017 */ 5018void 5019pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5020 vm_offset_t *addr, vm_size_t size) 5021{ 5022} 5023 5024/* 5025 * pmap_map_section: 5026 * 5027 * Create a single section mapping. 5028 */ 5029void 5030pmap_map_section(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_prot_t prot, 5031 boolean_t ref) 5032{ 5033 pd_entry_t *pl1pd, l1pd; 5034 pd_entry_t fl; 5035 5036 KASSERT(((va | pa) & L1_S_OFFSET) == 0, 5037 ("Not a valid section mapping")); 5038 5039 fl = pte_l1_s_cache_mode; 5040 5041 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 5042 l1pd = L1_S_PROTO | pa | L1_S_PROT(PTE_USER, prot) | fl | 5043 L1_S_DOM(pmap->pm_domain); 5044 5045 /* Mark page referenced if this section is a result of a promotion. */ 5046 if (ref == TRUE) 5047 l1pd |= L1_S_REF; 5048#ifdef SMP 5049 l1pd |= L1_SHARED; 5050#endif 5051 *pl1pd = l1pd; 5052 PTE_SYNC(pl1pd); 5053} 5054 5055/* 5056 * pmap_link_l2pt: 5057 * 5058 * Link the L2 page table specified by l2pv.pv_pa into the L1 5059 * page table at the slot for "va". 5060 */ 5061void 5062pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 5063{ 5064 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5065 u_int slot = va >> L1_S_SHIFT; 5066 5067 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5068 5069#ifdef VERBOSE_INIT_ARM 5070 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 5071#endif 5072 5073 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5074 PTE_SYNC(&pde[slot]); 5075 5076 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5077 5078} 5079 5080/* 5081 * pmap_map_entry 5082 * 5083 * Create a single page mapping. 5084 */ 5085void 5086pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 5087 int cache) 5088{ 5089 pd_entry_t *pde = (pd_entry_t *) l1pt; 5090 pt_entry_t fl; 5091 pt_entry_t *ptep; 5092 5093 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 5094 5095 fl = l2s_mem_types[cache]; 5096 5097 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5098 panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 5099 5100 ptep = (pt_entry_t *)kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5101 5102 if (ptep == NULL) 5103 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 5104 5105 ptep[l2pte_index(va)] = L2_S_PROTO | pa | fl | L2_S_REF; 5106 pmap_set_prot(&ptep[l2pte_index(va)], prot, 0); 5107 PTE_SYNC(&ptep[l2pte_index(va)]); 5108} 5109 5110/* 5111 * pmap_map_chunk: 5112 * 5113 * Map a chunk of memory using the most efficient mappings 5114 * possible (section. large page, small page) into the 5115 * provided L1 and L2 tables at the specified virtual address. 5116 */ 5117vm_size_t 5118pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 5119 vm_size_t size, int prot, int type) 5120{ 5121 pd_entry_t *pde = (pd_entry_t *) l1pt; 5122 pt_entry_t *ptep, f1, f2s, f2l; 5123 vm_size_t resid; 5124 int i; 5125 5126 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5127 5128 if (l1pt == 0) 5129 panic("pmap_map_chunk: no L1 table provided"); 5130 5131#ifdef VERBOSE_INIT_ARM 5132 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 5133 "prot=0x%x type=%d\n", pa, va, size, resid, prot, type); 5134#endif 5135 5136 f1 = l1_mem_types[type]; 5137 f2l = l2l_mem_types[type]; 5138 f2s = l2s_mem_types[type]; 5139 5140 size = resid; 5141 5142 while (resid > 0) { 5143 /* See if we can use a section mapping. */ 5144 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5145#ifdef VERBOSE_INIT_ARM 5146 printf("S"); 5147#endif 5148 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5149 L1_S_PROT(PTE_KERNEL, prot | VM_PROT_EXECUTE) | 5150 f1 | L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_S_REF; 5151 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5152 va += L1_S_SIZE; 5153 pa += L1_S_SIZE; 5154 resid -= L1_S_SIZE; 5155 continue; 5156 } 5157 5158 /* 5159 * Ok, we're going to use an L2 table. Make sure 5160 * one is actually in the corresponding L1 slot 5161 * for the current VA. 5162 */ 5163 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5164 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 5165 5166 ptep = (pt_entry_t *) kernel_pt_lookup( 5167 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5168 if (ptep == NULL) 5169 panic("pmap_map_chunk: can't find L2 table for VA" 5170 "0x%08x", va); 5171 /* See if we can use a L2 large page mapping. */ 5172 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5173#ifdef VERBOSE_INIT_ARM 5174 printf("L"); 5175#endif 5176 for (i = 0; i < 16; i++) { 5177 ptep[l2pte_index(va) + i] = 5178 L2_L_PROTO | pa | 5179 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5180 PTE_SYNC(&ptep[l2pte_index(va) + i]); 5181 } 5182 va += L2_L_SIZE; 5183 pa += L2_L_SIZE; 5184 resid -= L2_L_SIZE; 5185 continue; 5186 } 5187 5188 /* Use a small page mapping. */ 5189#ifdef VERBOSE_INIT_ARM 5190 printf("P"); 5191#endif 5192 ptep[l2pte_index(va)] = L2_S_PROTO | pa | f2s | L2_S_REF; 5193 pmap_set_prot(&ptep[l2pte_index(va)], prot, 0); 5194 PTE_SYNC(&ptep[l2pte_index(va)]); 5195 va += PAGE_SIZE; 5196 pa += PAGE_SIZE; 5197 resid -= PAGE_SIZE; 5198 } 5199#ifdef VERBOSE_INIT_ARM 5200 printf("\n"); 5201#endif 5202 return (size); 5203 5204} 5205 5206int 5207pmap_dmap_iscurrent(pmap_t pmap) 5208{ 5209 return(pmap_is_current(pmap)); 5210} 5211 5212void 5213pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 5214{ 5215 /* 5216 * Remember the memattr in a field that gets used to set the appropriate 5217 * bits in the PTEs as mappings are established. 5218 */ 5219 m->md.pv_memattr = ma; 5220 5221 /* 5222 * It appears that this function can only be called before any mappings 5223 * for the page are established on ARM. If this ever changes, this code 5224 * will need to walk the pv_list and make each of the existing mappings 5225 * uncacheable, being careful to sync caches and PTEs (and maybe 5226 * invalidate TLB?) for any current mapping it modifies. 5227 */ 5228 if (TAILQ_FIRST(&m->md.pv_list) != NULL) 5229 panic("Can't change memattr on page with existing mappings"); 5230} 5231