xhci.c revision 278278
1/* $FreeBSD: stable/10/sys/dev/usb/controller/xhci.c 278278 2015-02-05 20:03:02Z hselasky $ */ 2/*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36/* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43#ifdef USB_GLOBAL_INCLUDE_FILE 44#include USB_GLOBAL_INCLUDE_FILE 45#else 46#include <sys/stdint.h> 47#include <sys/stddef.h> 48#include <sys/param.h> 49#include <sys/queue.h> 50#include <sys/types.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/bus.h> 54#include <sys/module.h> 55#include <sys/lock.h> 56#include <sys/mutex.h> 57#include <sys/condvar.h> 58#include <sys/sysctl.h> 59#include <sys/sx.h> 60#include <sys/unistd.h> 61#include <sys/callout.h> 62#include <sys/malloc.h> 63#include <sys/priv.h> 64 65#include <dev/usb/usb.h> 66#include <dev/usb/usbdi.h> 67 68#define USB_DEBUG_VAR xhcidebug 69 70#include <dev/usb/usb_core.h> 71#include <dev/usb/usb_debug.h> 72#include <dev/usb/usb_busdma.h> 73#include <dev/usb/usb_process.h> 74#include <dev/usb/usb_transfer.h> 75#include <dev/usb/usb_device.h> 76#include <dev/usb/usb_hub.h> 77#include <dev/usb/usb_util.h> 78 79#include <dev/usb/usb_controller.h> 80#include <dev/usb/usb_bus.h> 81#endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83#include <dev/usb/controller/xhci.h> 84#include <dev/usb/controller/xhcireg.h> 85 86#define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92static int xhcistreams; 93SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97#ifdef USB_DEBUG 98static int xhcidebug; 99static int xhciroute; 100static int xhcipolling; 101 102SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 103 &xhcidebug, 0, "Debug level"); 104TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 105SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 106 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 107TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 108SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 109 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 110TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 111#else 112#define xhciroute 0 113#endif 114 115#define XHCI_INTR_ENDPT 1 116 117struct xhci_std_temp { 118 struct xhci_softc *sc; 119 struct usb_page_cache *pc; 120 struct xhci_td *td; 121 struct xhci_td *td_next; 122 uint32_t len; 123 uint32_t offset; 124 uint32_t max_packet_size; 125 uint32_t average; 126 uint16_t isoc_delta; 127 uint16_t isoc_frame; 128 uint8_t shortpkt; 129 uint8_t multishort; 130 uint8_t last_frame; 131 uint8_t trb_type; 132 uint8_t direction; 133 uint8_t tbc; 134 uint8_t tlbpc; 135 uint8_t step_td; 136 uint8_t do_isoc_sync; 137}; 138 139static void xhci_do_poll(struct usb_bus *); 140static void xhci_device_done(struct usb_xfer *, usb_error_t); 141static void xhci_root_intr(struct xhci_softc *); 142static void xhci_free_device_ext(struct usb_device *); 143static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 144 struct usb_endpoint_descriptor *); 145static usb_proc_callback_t xhci_configure_msg; 146static usb_error_t xhci_configure_device(struct usb_device *); 147static usb_error_t xhci_configure_endpoint(struct usb_device *, 148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 150 uint8_t); 151static usb_error_t xhci_configure_mask(struct usb_device *, 152 uint32_t, uint8_t); 153static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 154 uint64_t, uint8_t); 155static void xhci_endpoint_doorbell(struct usb_xfer *); 156static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 157static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 158static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 159#ifdef USB_DEBUG 160static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 161#endif 162 163extern struct usb_bus_methods xhci_bus_methods; 164 165#ifdef USB_DEBUG 166static void 167xhci_dump_trb(struct xhci_trb *trb) 168{ 169 DPRINTFN(5, "trb = %p\n", trb); 170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 173} 174 175static void 176xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 177{ 178 DPRINTFN(5, "pep = %p\n", pep); 179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 186} 187 188static void 189xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 190{ 191 DPRINTFN(5, "psl = %p\n", psl); 192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 196} 197#endif 198 199uint8_t 200xhci_use_polling(void) 201{ 202#ifdef USB_DEBUG 203 return (xhcipolling != 0); 204#else 205 return (0); 206#endif 207} 208 209static void 210xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 211{ 212 struct xhci_softc *sc = XHCI_BUS2SC(bus); 213 uint8_t i; 214 215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 217 218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 220 221 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 224 } 225} 226 227static void 228xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 229{ 230 if (sc->sc_ctx_is_64_byte) { 231 uint32_t offset; 232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 233 /* all contexts are initially 32-bytes */ 234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 236 } 237 *ptr = htole32(val); 238} 239 240static uint32_t 241xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 242{ 243 if (sc->sc_ctx_is_64_byte) { 244 uint32_t offset; 245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 246 /* all contexts are initially 32-bytes */ 247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 249 } 250 return (le32toh(*ptr)); 251} 252 253static void 254xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 255{ 256 if (sc->sc_ctx_is_64_byte) { 257 uint32_t offset; 258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 259 /* all contexts are initially 32-bytes */ 260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 262 } 263 *ptr = htole64(val); 264} 265 266#ifdef USB_DEBUG 267static uint64_t 268xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 269{ 270 if (sc->sc_ctx_is_64_byte) { 271 uint32_t offset; 272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 273 /* all contexts are initially 32-bytes */ 274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 276 } 277 return (le64toh(*ptr)); 278} 279#endif 280 281static int 282xhci_reset_command_queue_locked(struct xhci_softc *sc) 283{ 284 struct usb_page_search buf_res; 285 struct xhci_hw_root *phwr; 286 uint64_t addr; 287 uint32_t temp; 288 289 DPRINTF("\n"); 290 291 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 292 if (temp & XHCI_CRCR_LO_CRR) { 293 DPRINTF("Command ring running\n"); 294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 295 296 /* 297 * Try to abort the last command as per section 298 * 4.6.1.2 "Aborting a Command" of the XHCI 299 * specification: 300 */ 301 302 /* stop and cancel */ 303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 304 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 305 306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 307 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 308 309 /* wait 250ms */ 310 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 311 312 /* check if command ring is still running */ 313 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 314 if (temp & XHCI_CRCR_LO_CRR) { 315 DPRINTF("Comand ring still running\n"); 316 return (USB_ERR_IOERROR); 317 } 318 } 319 320 /* reset command ring */ 321 sc->sc_command_ccs = 1; 322 sc->sc_command_idx = 0; 323 324 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 325 326 /* set up command ring control base address */ 327 addr = buf_res.physaddr; 328 phwr = buf_res.buffer; 329 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 330 331 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 332 333 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 334 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 335 336 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 337 338 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 339 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 340 341 return (0); 342} 343 344usb_error_t 345xhci_start_controller(struct xhci_softc *sc) 346{ 347 struct usb_page_search buf_res; 348 struct xhci_hw_root *phwr; 349 struct xhci_dev_ctx_addr *pdctxa; 350 uint64_t addr; 351 uint32_t temp; 352 uint16_t i; 353 354 DPRINTF("\n"); 355 356 sc->sc_event_ccs = 1; 357 sc->sc_event_idx = 0; 358 sc->sc_command_ccs = 1; 359 sc->sc_command_idx = 0; 360 361 /* Reset controller */ 362 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 363 364 for (i = 0; i != 100; i++) { 365 usb_pause_mtx(NULL, hz / 100); 366 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 367 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 368 if (!temp) 369 break; 370 } 371 372 if (temp) { 373 device_printf(sc->sc_bus.parent, "Controller " 374 "reset timeout.\n"); 375 return (USB_ERR_IOERROR); 376 } 377 378 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 379 device_printf(sc->sc_bus.parent, "Controller does " 380 "not support 4K page size.\n"); 381 return (USB_ERR_IOERROR); 382 } 383 384 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 385 386 i = XHCI_HCS1_N_PORTS(temp); 387 388 if (i == 0) { 389 device_printf(sc->sc_bus.parent, "Invalid number " 390 "of ports: %u\n", i); 391 return (USB_ERR_IOERROR); 392 } 393 394 sc->sc_noport = i; 395 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 396 397 if (sc->sc_noslot > XHCI_MAX_DEVICES) 398 sc->sc_noslot = XHCI_MAX_DEVICES; 399 400 /* set up number of device slots */ 401 402 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 403 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 404 405 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 406 407 DPRINTF("Max slots: %u\n", sc->sc_noslot); 408 409 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 410 411 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 412 413 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 414 device_printf(sc->sc_bus.parent, "XHCI request " 415 "too many scratchpads\n"); 416 return (USB_ERR_NOMEM); 417 } 418 419 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 420 421 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 422 423 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 424 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 425 426 temp = XREAD4(sc, oper, XHCI_USBSTS); 427 428 /* clear interrupts */ 429 XWRITE4(sc, oper, XHCI_USBSTS, temp); 430 /* disable all device notifications */ 431 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 432 433 /* set up device context base address */ 434 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 435 pdctxa = buf_res.buffer; 436 memset(pdctxa, 0, sizeof(*pdctxa)); 437 438 addr = buf_res.physaddr; 439 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 440 441 /* slot 0 points to the table of scratchpad pointers */ 442 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 443 444 for (i = 0; i != sc->sc_noscratch; i++) { 445 struct usb_page_search buf_scp; 446 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 447 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 448 } 449 450 addr = buf_res.physaddr; 451 452 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 453 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 454 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 455 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 456 457 /* Setup event table size */ 458 459 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 460 461 DPRINTF("HCS2=0x%08x\n", temp); 462 463 temp = XHCI_HCS2_ERST_MAX(temp); 464 temp = 1U << temp; 465 if (temp > XHCI_MAX_RSEG) 466 temp = XHCI_MAX_RSEG; 467 468 sc->sc_erst_max = temp; 469 470 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 471 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 472 473 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 474 475 /* Check if we should use the default IMOD value */ 476 if (sc->sc_imod_default == 0) 477 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 478 479 /* Setup interrupt rate */ 480 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 481 482 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 483 484 phwr = buf_res.buffer; 485 addr = buf_res.physaddr; 486 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 487 488 /* reset hardware root structure */ 489 memset(phwr, 0, sizeof(*phwr)); 490 491 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 492 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 493 494 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 495 496 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 497 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 498 499 addr = (uint64_t)buf_res.physaddr; 500 501 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 502 503 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 504 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 505 506 /* Setup interrupter registers */ 507 508 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 509 temp |= XHCI_IMAN_INTR_ENA; 510 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 511 512 /* set up command ring control base address */ 513 addr = buf_res.physaddr; 514 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 515 516 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 517 518 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 519 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 520 521 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 522 523 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 524 525 /* Go! */ 526 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 527 XHCI_CMD_INTE | XHCI_CMD_HSEE); 528 529 for (i = 0; i != 100; i++) { 530 usb_pause_mtx(NULL, hz / 100); 531 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 532 if (!temp) 533 break; 534 } 535 if (temp) { 536 XWRITE4(sc, oper, XHCI_USBCMD, 0); 537 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 538 return (USB_ERR_IOERROR); 539 } 540 541 /* catch any lost interrupts */ 542 xhci_do_poll(&sc->sc_bus); 543 544 if (sc->sc_port_route != NULL) { 545 /* Route all ports to the XHCI by default */ 546 sc->sc_port_route(sc->sc_bus.parent, 547 ~xhciroute, xhciroute); 548 } 549 return (0); 550} 551 552usb_error_t 553xhci_halt_controller(struct xhci_softc *sc) 554{ 555 uint32_t temp; 556 uint16_t i; 557 558 DPRINTF("\n"); 559 560 sc->sc_capa_off = 0; 561 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 562 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 563 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 564 565 /* Halt controller */ 566 XWRITE4(sc, oper, XHCI_USBCMD, 0); 567 568 for (i = 0; i != 100; i++) { 569 usb_pause_mtx(NULL, hz / 100); 570 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 571 if (temp) 572 break; 573 } 574 575 if (!temp) { 576 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 577 return (USB_ERR_IOERROR); 578 } 579 return (0); 580} 581 582usb_error_t 583xhci_init(struct xhci_softc *sc, device_t self) 584{ 585 uint32_t temp; 586 587 DPRINTF("\n"); 588 589 /* initialize some bus fields */ 590 sc->sc_bus.parent = self; 591 592 /* set the bus revision */ 593 sc->sc_bus.usbrev = USB_REV_3_0; 594 595 /* set up the bus struct */ 596 sc->sc_bus.methods = &xhci_bus_methods; 597 598 /* set up devices array */ 599 sc->sc_bus.devices = sc->sc_devices; 600 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 601 602 /* set default cycle state in case of early interrupts */ 603 sc->sc_event_ccs = 1; 604 sc->sc_command_ccs = 1; 605 606 /* set up bus space offsets */ 607 sc->sc_capa_off = 0; 608 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 609 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 610 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 611 612 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 613 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 614 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 615 616 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 617 618 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 619 620 DPRINTF("HCS0 = 0x%08x\n", temp); 621 622 /* set up context size */ 623 if (XHCI_HCS0_CSZ(temp)) { 624 sc->sc_ctx_is_64_byte = 1; 625 } else { 626 sc->sc_ctx_is_64_byte = 0; 627 } 628 629 /* get DMA bits */ 630 sc->sc_bus.dma_bits = XHCI_HCS0_AC64(temp) ? 64 : 32; 631 632 device_printf(self, "%d bytes context size, %d-bit DMA\n", 633 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 634 635 /* get all DMA memory */ 636 if (usb_bus_mem_alloc_all(&sc->sc_bus, 637 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 638 return (ENOMEM); 639 } 640 641 /* set up command queue mutex and condition varible */ 642 cv_init(&sc->sc_cmd_cv, "CMDQ"); 643 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 644 645 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 646 sc->sc_config_msg[0].bus = &sc->sc_bus; 647 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 648 sc->sc_config_msg[1].bus = &sc->sc_bus; 649 650 return (0); 651} 652 653void 654xhci_uninit(struct xhci_softc *sc) 655{ 656 /* 657 * NOTE: At this point the control transfer process is gone 658 * and "xhci_configure_msg" is no longer called. Consequently 659 * waiting for the configuration messages to complete is not 660 * needed. 661 */ 662 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 663 664 cv_destroy(&sc->sc_cmd_cv); 665 sx_destroy(&sc->sc_cmd_sx); 666} 667 668static void 669xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 670{ 671 struct xhci_softc *sc = XHCI_BUS2SC(bus); 672 673 switch (state) { 674 case USB_HW_POWER_SUSPEND: 675 DPRINTF("Stopping the XHCI\n"); 676 xhci_halt_controller(sc); 677 break; 678 case USB_HW_POWER_SHUTDOWN: 679 DPRINTF("Stopping the XHCI\n"); 680 xhci_halt_controller(sc); 681 break; 682 case USB_HW_POWER_RESUME: 683 DPRINTF("Starting the XHCI\n"); 684 xhci_start_controller(sc); 685 break; 686 default: 687 break; 688 } 689} 690 691static usb_error_t 692xhci_generic_done_sub(struct usb_xfer *xfer) 693{ 694 struct xhci_td *td; 695 struct xhci_td *td_alt_next; 696 uint32_t len; 697 uint8_t status; 698 699 td = xfer->td_transfer_cache; 700 td_alt_next = td->alt_next; 701 702 if (xfer->aframes != xfer->nframes) 703 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 704 705 while (1) { 706 707 usb_pc_cpu_invalidate(td->page_cache); 708 709 status = td->status; 710 len = td->remainder; 711 712 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 713 xfer, (unsigned int)xfer->aframes, 714 (unsigned int)xfer->nframes, 715 (unsigned int)len, (unsigned int)td->len, 716 (unsigned int)status); 717 718 /* 719 * Verify the status length and 720 * add the length to "frlengths[]": 721 */ 722 if (len > td->len) { 723 /* should not happen */ 724 DPRINTF("Invalid status length, " 725 "0x%04x/0x%04x bytes\n", len, td->len); 726 status = XHCI_TRB_ERROR_LENGTH; 727 } else if (xfer->aframes != xfer->nframes) { 728 xfer->frlengths[xfer->aframes] += td->len - len; 729 } 730 /* Check for last transfer */ 731 if (((void *)td) == xfer->td_transfer_last) { 732 td = NULL; 733 break; 734 } 735 /* Check for transfer error */ 736 if (status != XHCI_TRB_ERROR_SHORT_PKT && 737 status != XHCI_TRB_ERROR_SUCCESS) { 738 /* the transfer is finished */ 739 td = NULL; 740 break; 741 } 742 /* Check for short transfer */ 743 if (len > 0) { 744 if (xfer->flags_int.short_frames_ok || 745 xfer->flags_int.isochronous_xfr || 746 xfer->flags_int.control_xfr) { 747 /* follow alt next */ 748 td = td->alt_next; 749 } else { 750 /* the transfer is finished */ 751 td = NULL; 752 } 753 break; 754 } 755 td = td->obj_next; 756 757 if (td->alt_next != td_alt_next) { 758 /* this USB frame is complete */ 759 break; 760 } 761 } 762 763 /* update transfer cache */ 764 765 xfer->td_transfer_cache = td; 766 767 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 768 (status != XHCI_TRB_ERROR_SHORT_PKT && 769 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 770 USB_ERR_NORMAL_COMPLETION); 771} 772 773static void 774xhci_generic_done(struct usb_xfer *xfer) 775{ 776 usb_error_t err = 0; 777 778 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 779 xfer, xfer->endpoint); 780 781 /* reset scanner */ 782 783 xfer->td_transfer_cache = xfer->td_transfer_first; 784 785 if (xfer->flags_int.control_xfr) { 786 787 if (xfer->flags_int.control_hdr) 788 err = xhci_generic_done_sub(xfer); 789 790 xfer->aframes = 1; 791 792 if (xfer->td_transfer_cache == NULL) 793 goto done; 794 } 795 796 while (xfer->aframes != xfer->nframes) { 797 798 err = xhci_generic_done_sub(xfer); 799 xfer->aframes++; 800 801 if (xfer->td_transfer_cache == NULL) 802 goto done; 803 } 804 805 if (xfer->flags_int.control_xfr && 806 !xfer->flags_int.control_act) 807 err = xhci_generic_done_sub(xfer); 808done: 809 /* transfer is complete */ 810 xhci_device_done(xfer, err); 811} 812 813static void 814xhci_activate_transfer(struct usb_xfer *xfer) 815{ 816 struct xhci_td *td; 817 818 td = xfer->td_transfer_cache; 819 820 usb_pc_cpu_invalidate(td->page_cache); 821 822 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 823 824 /* activate the transfer */ 825 826 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 827 usb_pc_cpu_flush(td->page_cache); 828 829 xhci_endpoint_doorbell(xfer); 830 } 831} 832 833static void 834xhci_skip_transfer(struct usb_xfer *xfer) 835{ 836 struct xhci_td *td; 837 struct xhci_td *td_last; 838 839 td = xfer->td_transfer_cache; 840 td_last = xfer->td_transfer_last; 841 842 td = td->alt_next; 843 844 usb_pc_cpu_invalidate(td->page_cache); 845 846 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 847 848 usb_pc_cpu_invalidate(td_last->page_cache); 849 850 /* copy LINK TRB to current waiting location */ 851 852 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 853 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 854 usb_pc_cpu_flush(td->page_cache); 855 856 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 857 usb_pc_cpu_flush(td->page_cache); 858 859 xhci_endpoint_doorbell(xfer); 860 } 861} 862 863/*------------------------------------------------------------------------* 864 * xhci_check_transfer 865 *------------------------------------------------------------------------*/ 866static void 867xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 868{ 869 struct xhci_endpoint_ext *pepext; 870 int64_t offset; 871 uint64_t td_event; 872 uint32_t temp; 873 uint32_t remainder; 874 uint16_t stream_id; 875 uint16_t i; 876 uint8_t status; 877 uint8_t halted; 878 uint8_t epno; 879 uint8_t index; 880 881 /* decode TRB */ 882 td_event = le64toh(trb->qwTrb0); 883 temp = le32toh(trb->dwTrb2); 884 885 remainder = XHCI_TRB_2_REM_GET(temp); 886 status = XHCI_TRB_2_ERROR_GET(temp); 887 stream_id = XHCI_TRB_2_STREAM_GET(temp); 888 889 temp = le32toh(trb->dwTrb3); 890 epno = XHCI_TRB_3_EP_GET(temp); 891 index = XHCI_TRB_3_SLOT_GET(temp); 892 893 /* check if error means halted */ 894 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 895 status != XHCI_TRB_ERROR_SUCCESS); 896 897 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 898 index, epno, stream_id, remainder, status); 899 900 if (index > sc->sc_noslot) { 901 DPRINTF("Invalid slot.\n"); 902 return; 903 } 904 905 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 906 DPRINTF("Invalid endpoint.\n"); 907 return; 908 } 909 910 pepext = &sc->sc_hw.devs[index].endp[epno]; 911 912 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 913 stream_id = 0; 914 DPRINTF("stream_id=0\n"); 915 } else if (stream_id >= XHCI_MAX_STREAMS) { 916 DPRINTF("Invalid stream ID.\n"); 917 return; 918 } 919 920 /* try to find the USB transfer that generated the event */ 921 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 922 struct usb_xfer *xfer; 923 struct xhci_td *td; 924 925 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 926 if (xfer == NULL) 927 continue; 928 929 td = xfer->td_transfer_cache; 930 931 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 932 (long long)td_event, 933 (long long)td->td_self, 934 (long long)td->td_self + sizeof(td->td_trb)); 935 936 /* 937 * NOTE: Some XHCI implementations might not trigger 938 * an event on the last LINK TRB so we need to 939 * consider both the last and second last event 940 * address as conditions for a successful transfer. 941 * 942 * NOTE: We assume that the XHCI will only trigger one 943 * event per chain of TRBs. 944 */ 945 946 offset = td_event - td->td_self; 947 948 if (offset >= 0 && 949 offset < (int64_t)sizeof(td->td_trb)) { 950 951 usb_pc_cpu_invalidate(td->page_cache); 952 953 /* compute rest of remainder, if any */ 954 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 955 temp = le32toh(td->td_trb[i].dwTrb2); 956 remainder += XHCI_TRB_2_BYTES_GET(temp); 957 } 958 959 DPRINTFN(5, "New remainder: %u\n", remainder); 960 961 /* clear isochronous transfer errors */ 962 if (xfer->flags_int.isochronous_xfr) { 963 if (halted) { 964 halted = 0; 965 status = XHCI_TRB_ERROR_SUCCESS; 966 remainder = td->len; 967 } 968 } 969 970 /* "td->remainder" is verified later */ 971 td->remainder = remainder; 972 td->status = status; 973 974 usb_pc_cpu_flush(td->page_cache); 975 976 /* 977 * 1) Last transfer descriptor makes the 978 * transfer done 979 */ 980 if (((void *)td) == xfer->td_transfer_last) { 981 DPRINTF("TD is last\n"); 982 xhci_generic_done(xfer); 983 break; 984 } 985 986 /* 987 * 2) Any kind of error makes the transfer 988 * done 989 */ 990 if (halted) { 991 DPRINTF("TD has I/O error\n"); 992 xhci_generic_done(xfer); 993 break; 994 } 995 996 /* 997 * 3) If there is no alternate next transfer, 998 * a short packet also makes the transfer done 999 */ 1000 if (td->remainder > 0) { 1001 if (td->alt_next == NULL) { 1002 DPRINTF( 1003 "short TD has no alternate next\n"); 1004 xhci_generic_done(xfer); 1005 break; 1006 } 1007 DPRINTF("TD has short pkt\n"); 1008 if (xfer->flags_int.short_frames_ok || 1009 xfer->flags_int.isochronous_xfr || 1010 xfer->flags_int.control_xfr) { 1011 /* follow the alt next */ 1012 xfer->td_transfer_cache = td->alt_next; 1013 xhci_activate_transfer(xfer); 1014 break; 1015 } 1016 xhci_skip_transfer(xfer); 1017 xhci_generic_done(xfer); 1018 break; 1019 } 1020 1021 /* 1022 * 4) Transfer complete - go to next TD 1023 */ 1024 DPRINTF("Following next TD\n"); 1025 xfer->td_transfer_cache = td->obj_next; 1026 xhci_activate_transfer(xfer); 1027 break; /* there should only be one match */ 1028 } 1029 } 1030} 1031 1032static int 1033xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1034{ 1035 if (sc->sc_cmd_addr == trb->qwTrb0) { 1036 DPRINTF("Received command event\n"); 1037 sc->sc_cmd_result[0] = trb->dwTrb2; 1038 sc->sc_cmd_result[1] = trb->dwTrb3; 1039 cv_signal(&sc->sc_cmd_cv); 1040 return (1); /* command match */ 1041 } 1042 return (0); 1043} 1044 1045static int 1046xhci_interrupt_poll(struct xhci_softc *sc) 1047{ 1048 struct usb_page_search buf_res; 1049 struct xhci_hw_root *phwr; 1050 uint64_t addr; 1051 uint32_t temp; 1052 int retval = 0; 1053 uint16_t i; 1054 uint8_t event; 1055 uint8_t j; 1056 uint8_t k; 1057 uint8_t t; 1058 1059 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1060 1061 phwr = buf_res.buffer; 1062 1063 /* Receive any events */ 1064 1065 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1066 1067 i = sc->sc_event_idx; 1068 j = sc->sc_event_ccs; 1069 t = 2; 1070 1071 while (1) { 1072 1073 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1074 1075 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1076 1077 if (j != k) 1078 break; 1079 1080 event = XHCI_TRB_3_TYPE_GET(temp); 1081 1082 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1083 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1084 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1085 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1086 1087 switch (event) { 1088 case XHCI_TRB_EVENT_TRANSFER: 1089 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1090 break; 1091 case XHCI_TRB_EVENT_CMD_COMPLETE: 1092 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1093 break; 1094 default: 1095 DPRINTF("Unhandled event = %u\n", event); 1096 break; 1097 } 1098 1099 i++; 1100 1101 if (i == XHCI_MAX_EVENTS) { 1102 i = 0; 1103 j ^= 1; 1104 1105 /* check for timeout */ 1106 if (!--t) 1107 break; 1108 } 1109 } 1110 1111 sc->sc_event_idx = i; 1112 sc->sc_event_ccs = j; 1113 1114 /* 1115 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1116 * latched. That means to activate the register we need to 1117 * write both the low and high double word of the 64-bit 1118 * register. 1119 */ 1120 1121 addr = (uint32_t)buf_res.physaddr; 1122 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1123 1124 /* try to clear busy bit */ 1125 addr |= XHCI_ERDP_LO_BUSY; 1126 1127 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1128 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1129 1130 return (retval); 1131} 1132 1133static usb_error_t 1134xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1135 uint16_t timeout_ms) 1136{ 1137 struct usb_page_search buf_res; 1138 struct xhci_hw_root *phwr; 1139 uint64_t addr; 1140 uint32_t temp; 1141 uint8_t i; 1142 uint8_t j; 1143 uint8_t timeout = 0; 1144 int err; 1145 1146 XHCI_CMD_ASSERT_LOCKED(sc); 1147 1148 /* get hardware root structure */ 1149 1150 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1151 1152 phwr = buf_res.buffer; 1153 1154 /* Queue command */ 1155 1156 USB_BUS_LOCK(&sc->sc_bus); 1157retry: 1158 i = sc->sc_command_idx; 1159 j = sc->sc_command_ccs; 1160 1161 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1162 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1163 (long long)le64toh(trb->qwTrb0), 1164 (long)le32toh(trb->dwTrb2), 1165 (long)le32toh(trb->dwTrb3)); 1166 1167 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1168 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1169 1170 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1171 1172 temp = trb->dwTrb3; 1173 1174 if (j) 1175 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1176 else 1177 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1178 1179 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1180 1181 phwr->hwr_commands[i].dwTrb3 = temp; 1182 1183 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1184 1185 addr = buf_res.physaddr; 1186 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1187 1188 sc->sc_cmd_addr = htole64(addr); 1189 1190 i++; 1191 1192 if (i == (XHCI_MAX_COMMANDS - 1)) { 1193 1194 if (j) { 1195 temp = htole32(XHCI_TRB_3_TC_BIT | 1196 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1197 XHCI_TRB_3_CYCLE_BIT); 1198 } else { 1199 temp = htole32(XHCI_TRB_3_TC_BIT | 1200 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1201 } 1202 1203 phwr->hwr_commands[i].dwTrb3 = temp; 1204 1205 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1206 1207 i = 0; 1208 j ^= 1; 1209 } 1210 1211 sc->sc_command_idx = i; 1212 sc->sc_command_ccs = j; 1213 1214 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1215 1216 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1217 USB_MS_TO_TICKS(timeout_ms)); 1218 1219 /* 1220 * In some error cases event interrupts are not generated. 1221 * Poll one time to see if the command has completed. 1222 */ 1223 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1224 DPRINTF("Command was completed when polling\n"); 1225 err = 0; 1226 } 1227 if (err != 0) { 1228 DPRINTF("Command timeout!\n"); 1229 /* 1230 * After some weeks of continuous operation, it has 1231 * been observed that the ASMedia Technology, ASM1042 1232 * SuperSpeed USB Host Controller can suddenly stop 1233 * accepting commands via the command queue. Try to 1234 * first reset the command queue. If that fails do a 1235 * host controller reset. 1236 */ 1237 if (timeout == 0 && 1238 xhci_reset_command_queue_locked(sc) == 0) { 1239 temp = le32toh(trb->dwTrb3); 1240 1241 /* 1242 * Avoid infinite XHCI reset loops if the set 1243 * address command fails to respond due to a 1244 * non-enumerating device: 1245 */ 1246 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1247 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1248 DPRINTF("Set address timeout\n"); 1249 } else { 1250 timeout = 1; 1251 goto retry; 1252 } 1253 } else { 1254 DPRINTF("Controller reset!\n"); 1255 usb_bus_reset_async_locked(&sc->sc_bus); 1256 } 1257 err = USB_ERR_TIMEOUT; 1258 trb->dwTrb2 = 0; 1259 trb->dwTrb3 = 0; 1260 } else { 1261 temp = le32toh(sc->sc_cmd_result[0]); 1262 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1263 err = USB_ERR_IOERROR; 1264 1265 trb->dwTrb2 = sc->sc_cmd_result[0]; 1266 trb->dwTrb3 = sc->sc_cmd_result[1]; 1267 } 1268 1269 USB_BUS_UNLOCK(&sc->sc_bus); 1270 1271 return (err); 1272} 1273 1274#if 0 1275static usb_error_t 1276xhci_cmd_nop(struct xhci_softc *sc) 1277{ 1278 struct xhci_trb trb; 1279 uint32_t temp; 1280 1281 DPRINTF("\n"); 1282 1283 trb.qwTrb0 = 0; 1284 trb.dwTrb2 = 0; 1285 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1286 1287 trb.dwTrb3 = htole32(temp); 1288 1289 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1290} 1291#endif 1292 1293static usb_error_t 1294xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1295{ 1296 struct xhci_trb trb; 1297 uint32_t temp; 1298 usb_error_t err; 1299 1300 DPRINTF("\n"); 1301 1302 trb.qwTrb0 = 0; 1303 trb.dwTrb2 = 0; 1304 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1305 1306 err = xhci_do_command(sc, &trb, 100 /* ms */); 1307 if (err) 1308 goto done; 1309 1310 temp = le32toh(trb.dwTrb3); 1311 1312 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1313 1314done: 1315 return (err); 1316} 1317 1318static usb_error_t 1319xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1320{ 1321 struct xhci_trb trb; 1322 uint32_t temp; 1323 1324 DPRINTF("\n"); 1325 1326 trb.qwTrb0 = 0; 1327 trb.dwTrb2 = 0; 1328 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1329 XHCI_TRB_3_SLOT_SET(slot_id); 1330 1331 trb.dwTrb3 = htole32(temp); 1332 1333 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1334} 1335 1336static usb_error_t 1337xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1338 uint8_t bsr, uint8_t slot_id) 1339{ 1340 struct xhci_trb trb; 1341 uint32_t temp; 1342 1343 DPRINTF("\n"); 1344 1345 trb.qwTrb0 = htole64(input_ctx); 1346 trb.dwTrb2 = 0; 1347 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1348 XHCI_TRB_3_SLOT_SET(slot_id); 1349 1350 if (bsr) 1351 temp |= XHCI_TRB_3_BSR_BIT; 1352 1353 trb.dwTrb3 = htole32(temp); 1354 1355 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1356} 1357 1358static usb_error_t 1359xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1360{ 1361 struct usb_page_search buf_inp; 1362 struct usb_page_search buf_dev; 1363 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1364 struct xhci_hw_dev *hdev; 1365 struct xhci_dev_ctx *pdev; 1366 struct xhci_endpoint_ext *pepext; 1367 uint32_t temp; 1368 uint16_t mps; 1369 usb_error_t err; 1370 uint8_t index; 1371 1372 /* the root HUB case is not handled here */ 1373 if (udev->parent_hub == NULL) 1374 return (USB_ERR_INVAL); 1375 1376 index = udev->controller_slot_id; 1377 1378 hdev = &sc->sc_hw.devs[index]; 1379 1380 if (mtx != NULL) 1381 mtx_unlock(mtx); 1382 1383 XHCI_CMD_LOCK(sc); 1384 1385 switch (hdev->state) { 1386 case XHCI_ST_DEFAULT: 1387 case XHCI_ST_ENABLED: 1388 1389 hdev->state = XHCI_ST_ENABLED; 1390 1391 /* set configure mask to slot and EP0 */ 1392 xhci_configure_mask(udev, 3, 0); 1393 1394 /* configure input slot context structure */ 1395 err = xhci_configure_device(udev); 1396 1397 if (err != 0) { 1398 DPRINTF("Could not configure device\n"); 1399 break; 1400 } 1401 1402 /* configure input endpoint context structure */ 1403 switch (udev->speed) { 1404 case USB_SPEED_LOW: 1405 case USB_SPEED_FULL: 1406 mps = 8; 1407 break; 1408 case USB_SPEED_HIGH: 1409 mps = 64; 1410 break; 1411 default: 1412 mps = 512; 1413 break; 1414 } 1415 1416 pepext = xhci_get_endpoint_ext(udev, 1417 &udev->ctrl_ep_desc); 1418 err = xhci_configure_endpoint(udev, 1419 &udev->ctrl_ep_desc, pepext, 1420 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1421 1422 if (err != 0) { 1423 DPRINTF("Could not configure default endpoint\n"); 1424 break; 1425 } 1426 1427 /* execute set address command */ 1428 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1429 1430 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1431 (address == 0), index); 1432 1433 if (err != 0) { 1434 temp = le32toh(sc->sc_cmd_result[0]); 1435 if (address == 0 && sc->sc_port_route != NULL && 1436 XHCI_TRB_2_ERROR_GET(temp) == 1437 XHCI_TRB_ERROR_PARAMETER) { 1438 /* LynxPoint XHCI - ports are not switchable */ 1439 /* Un-route all ports from the XHCI */ 1440 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1441 } 1442 DPRINTF("Could not set address " 1443 "for slot %u.\n", index); 1444 if (address != 0) 1445 break; 1446 } 1447 1448 /* update device address to new value */ 1449 1450 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1451 pdev = buf_dev.buffer; 1452 usb_pc_cpu_invalidate(&hdev->device_pc); 1453 1454 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1455 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1456 1457 /* update device state to new value */ 1458 1459 if (address != 0) 1460 hdev->state = XHCI_ST_ADDRESSED; 1461 else 1462 hdev->state = XHCI_ST_DEFAULT; 1463 break; 1464 1465 default: 1466 DPRINTF("Wrong state for set address.\n"); 1467 err = USB_ERR_IOERROR; 1468 break; 1469 } 1470 XHCI_CMD_UNLOCK(sc); 1471 1472 if (mtx != NULL) 1473 mtx_lock(mtx); 1474 1475 return (err); 1476} 1477 1478static usb_error_t 1479xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1480 uint8_t deconfigure, uint8_t slot_id) 1481{ 1482 struct xhci_trb trb; 1483 uint32_t temp; 1484 1485 DPRINTF("\n"); 1486 1487 trb.qwTrb0 = htole64(input_ctx); 1488 trb.dwTrb2 = 0; 1489 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1490 XHCI_TRB_3_SLOT_SET(slot_id); 1491 1492 if (deconfigure) 1493 temp |= XHCI_TRB_3_DCEP_BIT; 1494 1495 trb.dwTrb3 = htole32(temp); 1496 1497 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1498} 1499 1500static usb_error_t 1501xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1502 uint8_t slot_id) 1503{ 1504 struct xhci_trb trb; 1505 uint32_t temp; 1506 1507 DPRINTF("\n"); 1508 1509 trb.qwTrb0 = htole64(input_ctx); 1510 trb.dwTrb2 = 0; 1511 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1512 XHCI_TRB_3_SLOT_SET(slot_id); 1513 trb.dwTrb3 = htole32(temp); 1514 1515 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1516} 1517 1518static usb_error_t 1519xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1520 uint8_t ep_id, uint8_t slot_id) 1521{ 1522 struct xhci_trb trb; 1523 uint32_t temp; 1524 1525 DPRINTF("\n"); 1526 1527 trb.qwTrb0 = 0; 1528 trb.dwTrb2 = 0; 1529 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1530 XHCI_TRB_3_SLOT_SET(slot_id) | 1531 XHCI_TRB_3_EP_SET(ep_id); 1532 1533 if (preserve) 1534 temp |= XHCI_TRB_3_PRSV_BIT; 1535 1536 trb.dwTrb3 = htole32(temp); 1537 1538 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1539} 1540 1541static usb_error_t 1542xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1543 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1544{ 1545 struct xhci_trb trb; 1546 uint32_t temp; 1547 1548 DPRINTF("\n"); 1549 1550 trb.qwTrb0 = htole64(dequeue_ptr); 1551 1552 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1553 trb.dwTrb2 = htole32(temp); 1554 1555 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1556 XHCI_TRB_3_SLOT_SET(slot_id) | 1557 XHCI_TRB_3_EP_SET(ep_id); 1558 trb.dwTrb3 = htole32(temp); 1559 1560 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1561} 1562 1563static usb_error_t 1564xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1565 uint8_t ep_id, uint8_t slot_id) 1566{ 1567 struct xhci_trb trb; 1568 uint32_t temp; 1569 1570 DPRINTF("\n"); 1571 1572 trb.qwTrb0 = 0; 1573 trb.dwTrb2 = 0; 1574 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1575 XHCI_TRB_3_SLOT_SET(slot_id) | 1576 XHCI_TRB_3_EP_SET(ep_id); 1577 1578 if (suspend) 1579 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1580 1581 trb.dwTrb3 = htole32(temp); 1582 1583 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1584} 1585 1586static usb_error_t 1587xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1588{ 1589 struct xhci_trb trb; 1590 uint32_t temp; 1591 1592 DPRINTF("\n"); 1593 1594 trb.qwTrb0 = 0; 1595 trb.dwTrb2 = 0; 1596 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1597 XHCI_TRB_3_SLOT_SET(slot_id); 1598 1599 trb.dwTrb3 = htole32(temp); 1600 1601 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1602} 1603 1604/*------------------------------------------------------------------------* 1605 * xhci_interrupt - XHCI interrupt handler 1606 *------------------------------------------------------------------------*/ 1607void 1608xhci_interrupt(struct xhci_softc *sc) 1609{ 1610 uint32_t status; 1611 uint32_t temp; 1612 1613 USB_BUS_LOCK(&sc->sc_bus); 1614 1615 status = XREAD4(sc, oper, XHCI_USBSTS); 1616 1617 /* acknowledge interrupts, if any */ 1618 if (status != 0) { 1619 XWRITE4(sc, oper, XHCI_USBSTS, status); 1620 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1621 } 1622 1623 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1624 1625 /* force clearing of pending interrupts */ 1626 if (temp & XHCI_IMAN_INTR_PEND) 1627 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1628 1629 /* check for event(s) */ 1630 xhci_interrupt_poll(sc); 1631 1632 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1633 XHCI_STS_HSE | XHCI_STS_HCE)) { 1634 1635 if (status & XHCI_STS_PCD) { 1636 xhci_root_intr(sc); 1637 } 1638 1639 if (status & XHCI_STS_HCH) { 1640 printf("%s: host controller halted\n", 1641 __FUNCTION__); 1642 } 1643 1644 if (status & XHCI_STS_HSE) { 1645 printf("%s: host system error\n", 1646 __FUNCTION__); 1647 } 1648 1649 if (status & XHCI_STS_HCE) { 1650 printf("%s: host controller error\n", 1651 __FUNCTION__); 1652 } 1653 } 1654 USB_BUS_UNLOCK(&sc->sc_bus); 1655} 1656 1657/*------------------------------------------------------------------------* 1658 * xhci_timeout - XHCI timeout handler 1659 *------------------------------------------------------------------------*/ 1660static void 1661xhci_timeout(void *arg) 1662{ 1663 struct usb_xfer *xfer = arg; 1664 1665 DPRINTF("xfer=%p\n", xfer); 1666 1667 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1668 1669 /* transfer is transferred */ 1670 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1671} 1672 1673static void 1674xhci_do_poll(struct usb_bus *bus) 1675{ 1676 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1677 1678 USB_BUS_LOCK(&sc->sc_bus); 1679 xhci_interrupt_poll(sc); 1680 USB_BUS_UNLOCK(&sc->sc_bus); 1681} 1682 1683static void 1684xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1685{ 1686 struct usb_page_search buf_res; 1687 struct xhci_td *td; 1688 struct xhci_td *td_next; 1689 struct xhci_td *td_alt_next; 1690 struct xhci_td *td_first; 1691 uint32_t buf_offset; 1692 uint32_t average; 1693 uint32_t len_old; 1694 uint32_t npkt_off; 1695 uint32_t dword; 1696 uint8_t shortpkt_old; 1697 uint8_t precompute; 1698 uint8_t x; 1699 1700 td_alt_next = NULL; 1701 buf_offset = 0; 1702 shortpkt_old = temp->shortpkt; 1703 len_old = temp->len; 1704 npkt_off = 0; 1705 precompute = 1; 1706 1707restart: 1708 1709 td = temp->td; 1710 td_next = td_first = temp->td_next; 1711 1712 while (1) { 1713 1714 if (temp->len == 0) { 1715 1716 if (temp->shortpkt) 1717 break; 1718 1719 /* send a Zero Length Packet, ZLP, last */ 1720 1721 temp->shortpkt = 1; 1722 average = 0; 1723 1724 } else { 1725 1726 average = temp->average; 1727 1728 if (temp->len < average) { 1729 if (temp->len % temp->max_packet_size) { 1730 temp->shortpkt = 1; 1731 } 1732 average = temp->len; 1733 } 1734 } 1735 1736 if (td_next == NULL) 1737 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1738 1739 /* get next TD */ 1740 1741 td = td_next; 1742 td_next = td->obj_next; 1743 1744 /* check if we are pre-computing */ 1745 1746 if (precompute) { 1747 1748 /* update remaining length */ 1749 1750 temp->len -= average; 1751 1752 continue; 1753 } 1754 /* fill out current TD */ 1755 1756 td->len = average; 1757 td->remainder = 0; 1758 td->status = 0; 1759 1760 /* update remaining length */ 1761 1762 temp->len -= average; 1763 1764 /* reset TRB index */ 1765 1766 x = 0; 1767 1768 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1769 /* immediate data */ 1770 1771 if (average > 8) 1772 average = 8; 1773 1774 td->td_trb[0].qwTrb0 = 0; 1775 1776 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1777 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1778 average); 1779 1780 dword = XHCI_TRB_2_BYTES_SET(8) | 1781 XHCI_TRB_2_TDSZ_SET(0) | 1782 XHCI_TRB_2_IRQ_SET(0); 1783 1784 td->td_trb[0].dwTrb2 = htole32(dword); 1785 1786 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1787 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1788 1789 /* check wLength */ 1790 if (td->td_trb[0].qwTrb0 & 1791 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1792 if (td->td_trb[0].qwTrb0 & 1793 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1794 dword |= XHCI_TRB_3_TRT_IN; 1795 else 1796 dword |= XHCI_TRB_3_TRT_OUT; 1797 } 1798 1799 td->td_trb[0].dwTrb3 = htole32(dword); 1800#ifdef USB_DEBUG 1801 xhci_dump_trb(&td->td_trb[x]); 1802#endif 1803 x++; 1804 1805 } else do { 1806 1807 uint32_t npkt; 1808 1809 /* fill out buffer pointers */ 1810 1811 if (average == 0) { 1812 memset(&buf_res, 0, sizeof(buf_res)); 1813 } else { 1814 usbd_get_page(temp->pc, temp->offset + 1815 buf_offset, &buf_res); 1816 1817 /* get length to end of page */ 1818 if (buf_res.length > average) 1819 buf_res.length = average; 1820 1821 /* check for maximum length */ 1822 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1823 buf_res.length = XHCI_TD_PAGE_SIZE; 1824 1825 npkt_off += buf_res.length; 1826 } 1827 1828 /* set up npkt */ 1829 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1830 temp->max_packet_size; 1831 1832 if (npkt == 0) 1833 npkt = 1; 1834 else if (npkt > 31) 1835 npkt = 31; 1836 1837 /* fill out TRB's */ 1838 td->td_trb[x].qwTrb0 = 1839 htole64((uint64_t)buf_res.physaddr); 1840 1841 dword = 1842 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1843 XHCI_TRB_2_TDSZ_SET(npkt) | 1844 XHCI_TRB_2_IRQ_SET(0); 1845 1846 td->td_trb[x].dwTrb2 = htole32(dword); 1847 1848 switch (temp->trb_type) { 1849 case XHCI_TRB_TYPE_ISOCH: 1850 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1851 XHCI_TRB_3_TBC_SET(temp->tbc) | 1852 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1853 if (td != td_first) { 1854 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1855 } else if (temp->do_isoc_sync != 0) { 1856 temp->do_isoc_sync = 0; 1857 /* wait until "isoc_frame" */ 1858 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1859 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1860 } else { 1861 /* start data transfer at next interval */ 1862 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1863 XHCI_TRB_3_ISO_SIA_BIT; 1864 } 1865 if (temp->direction == UE_DIR_IN) 1866 dword |= XHCI_TRB_3_ISP_BIT; 1867 break; 1868 case XHCI_TRB_TYPE_DATA_STAGE: 1869 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1870 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1871 if (temp->direction == UE_DIR_IN) 1872 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1873 break; 1874 case XHCI_TRB_TYPE_STATUS_STAGE: 1875 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1876 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1877 if (temp->direction == UE_DIR_IN) 1878 dword |= XHCI_TRB_3_DIR_IN; 1879 break; 1880 default: /* XHCI_TRB_TYPE_NORMAL */ 1881 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1882 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1883 if (temp->direction == UE_DIR_IN) 1884 dword |= XHCI_TRB_3_ISP_BIT; 1885 break; 1886 } 1887 td->td_trb[x].dwTrb3 = htole32(dword); 1888 1889 average -= buf_res.length; 1890 buf_offset += buf_res.length; 1891#ifdef USB_DEBUG 1892 xhci_dump_trb(&td->td_trb[x]); 1893#endif 1894 x++; 1895 1896 } while (average != 0); 1897 1898 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1899 1900 /* store number of data TRB's */ 1901 1902 td->ntrb = x; 1903 1904 DPRINTF("NTRB=%u\n", x); 1905 1906 /* fill out link TRB */ 1907 1908 if (td_next != NULL) { 1909 /* link the current TD with the next one */ 1910 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1911 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1912 } else { 1913 /* this field will get updated later */ 1914 DPRINTF("NOLINK\n"); 1915 } 1916 1917 dword = XHCI_TRB_2_IRQ_SET(0); 1918 1919 td->td_trb[x].dwTrb2 = htole32(dword); 1920 1921 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1922 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1923 /* 1924 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1925 * frame only receives a single short packet event 1926 * by setting the CHAIN bit in the LINK field. In 1927 * addition some XHCI controllers have problems 1928 * sending a ZLP unless the CHAIN-BIT is set in 1929 * the LINK TRB. 1930 */ 1931 XHCI_TRB_3_CHAIN_BIT; 1932 1933 td->td_trb[x].dwTrb3 = htole32(dword); 1934 1935 td->alt_next = td_alt_next; 1936#ifdef USB_DEBUG 1937 xhci_dump_trb(&td->td_trb[x]); 1938#endif 1939 usb_pc_cpu_flush(td->page_cache); 1940 } 1941 1942 if (precompute) { 1943 precompute = 0; 1944 1945 /* set up alt next pointer, if any */ 1946 if (temp->last_frame) { 1947 td_alt_next = NULL; 1948 } else { 1949 /* we use this field internally */ 1950 td_alt_next = td_next; 1951 } 1952 1953 /* restore */ 1954 temp->shortpkt = shortpkt_old; 1955 temp->len = len_old; 1956 goto restart; 1957 } 1958 1959 /* 1960 * Remove cycle bit from the first TRB if we are 1961 * stepping them: 1962 */ 1963 if (temp->step_td != 0) { 1964 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1965 usb_pc_cpu_flush(td_first->page_cache); 1966 } 1967 1968 /* clear TD SIZE to zero, hence this is the last TRB */ 1969 /* remove chain bit because this is the last data TRB in the chain */ 1970 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1971 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1972 /* remove CHAIN-BIT from last LINK TRB */ 1973 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1974 1975 usb_pc_cpu_flush(td->page_cache); 1976 1977 temp->td = td; 1978 temp->td_next = td_next; 1979} 1980 1981static void 1982xhci_setup_generic_chain(struct usb_xfer *xfer) 1983{ 1984 struct xhci_std_temp temp; 1985 struct xhci_td *td; 1986 uint32_t x; 1987 uint32_t y; 1988 uint8_t mult; 1989 1990 temp.do_isoc_sync = 0; 1991 temp.step_td = 0; 1992 temp.tbc = 0; 1993 temp.tlbpc = 0; 1994 temp.average = xfer->max_hc_frame_size; 1995 temp.max_packet_size = xfer->max_packet_size; 1996 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1997 temp.pc = NULL; 1998 temp.last_frame = 0; 1999 temp.offset = 0; 2000 temp.multishort = xfer->flags_int.isochronous_xfr || 2001 xfer->flags_int.control_xfr || 2002 xfer->flags_int.short_frames_ok; 2003 2004 /* toggle the DMA set we are using */ 2005 xfer->flags_int.curr_dma_set ^= 1; 2006 2007 /* get next DMA set */ 2008 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2009 2010 temp.td = NULL; 2011 temp.td_next = td; 2012 2013 xfer->td_transfer_first = td; 2014 xfer->td_transfer_cache = td; 2015 2016 if (xfer->flags_int.isochronous_xfr) { 2017 uint8_t shift; 2018 2019 /* compute multiplier for ISOCHRONOUS transfers */ 2020 mult = xfer->endpoint->ecomp ? 2021 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2022 : 0; 2023 /* check for USB 2.0 multiplier */ 2024 if (mult == 0) { 2025 mult = (xfer->endpoint->edesc-> 2026 wMaxPacketSize[1] >> 3) & 3; 2027 } 2028 /* range check */ 2029 if (mult > 2) 2030 mult = 3; 2031 else 2032 mult++; 2033 2034 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2035 2036 DPRINTF("MFINDEX=0x%08x\n", x); 2037 2038 switch (usbd_get_speed(xfer->xroot->udev)) { 2039 case USB_SPEED_FULL: 2040 shift = 3; 2041 temp.isoc_delta = 8; /* 1ms */ 2042 x += temp.isoc_delta - 1; 2043 x &= ~(temp.isoc_delta - 1); 2044 break; 2045 default: 2046 shift = usbd_xfer_get_fps_shift(xfer); 2047 temp.isoc_delta = 1U << shift; 2048 x += temp.isoc_delta - 1; 2049 x &= ~(temp.isoc_delta - 1); 2050 /* simple frame load balancing */ 2051 x += xfer->endpoint->usb_uframe; 2052 break; 2053 } 2054 2055 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2056 2057 if ((xfer->endpoint->is_synced == 0) || 2058 (y < (xfer->nframes << shift)) || 2059 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2060 /* 2061 * If there is data underflow or the pipe 2062 * queue is empty we schedule the transfer a 2063 * few frames ahead of the current frame 2064 * position. Else two isochronous transfers 2065 * might overlap. 2066 */ 2067 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2068 xfer->endpoint->is_synced = 1; 2069 temp.do_isoc_sync = 1; 2070 2071 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2072 } 2073 2074 /* compute isochronous completion time */ 2075 2076 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2077 2078 xfer->isoc_time_complete = 2079 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2080 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2081 2082 x = 0; 2083 temp.isoc_frame = xfer->endpoint->isoc_next; 2084 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2085 2086 xfer->endpoint->isoc_next += xfer->nframes << shift; 2087 2088 } else if (xfer->flags_int.control_xfr) { 2089 2090 /* check if we should prepend a setup message */ 2091 2092 if (xfer->flags_int.control_hdr) { 2093 2094 temp.len = xfer->frlengths[0]; 2095 temp.pc = xfer->frbuffers + 0; 2096 temp.shortpkt = temp.len ? 1 : 0; 2097 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2098 temp.direction = 0; 2099 2100 /* check for last frame */ 2101 if (xfer->nframes == 1) { 2102 /* no STATUS stage yet, SETUP is last */ 2103 if (xfer->flags_int.control_act) 2104 temp.last_frame = 1; 2105 } 2106 2107 xhci_setup_generic_chain_sub(&temp); 2108 } 2109 x = 1; 2110 mult = 1; 2111 temp.isoc_delta = 0; 2112 temp.isoc_frame = 0; 2113 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2114 } else { 2115 x = 0; 2116 mult = 1; 2117 temp.isoc_delta = 0; 2118 temp.isoc_frame = 0; 2119 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2120 } 2121 2122 if (x != xfer->nframes) { 2123 /* set up page_cache pointer */ 2124 temp.pc = xfer->frbuffers + x; 2125 /* set endpoint direction */ 2126 temp.direction = UE_GET_DIR(xfer->endpointno); 2127 } 2128 2129 while (x != xfer->nframes) { 2130 2131 /* DATA0 / DATA1 message */ 2132 2133 temp.len = xfer->frlengths[x]; 2134 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2135 x != 0 && temp.multishort == 0); 2136 2137 x++; 2138 2139 if (x == xfer->nframes) { 2140 if (xfer->flags_int.control_xfr) { 2141 /* no STATUS stage yet, DATA is last */ 2142 if (xfer->flags_int.control_act) 2143 temp.last_frame = 1; 2144 } else { 2145 temp.last_frame = 1; 2146 } 2147 } 2148 if (temp.len == 0) { 2149 2150 /* make sure that we send an USB packet */ 2151 2152 temp.shortpkt = 0; 2153 2154 temp.tbc = 0; 2155 temp.tlbpc = mult - 1; 2156 2157 } else if (xfer->flags_int.isochronous_xfr) { 2158 2159 uint8_t tdpc; 2160 2161 /* 2162 * Isochronous transfers don't have short 2163 * packet termination: 2164 */ 2165 2166 temp.shortpkt = 1; 2167 2168 /* isochronous transfers have a transfer limit */ 2169 2170 if (temp.len > xfer->max_frame_size) 2171 temp.len = xfer->max_frame_size; 2172 2173 /* compute TD packet count */ 2174 tdpc = (temp.len + xfer->max_packet_size - 1) / 2175 xfer->max_packet_size; 2176 2177 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2178 temp.tlbpc = (tdpc % mult); 2179 2180 if (temp.tlbpc == 0) 2181 temp.tlbpc = mult - 1; 2182 else 2183 temp.tlbpc--; 2184 } else { 2185 2186 /* regular data transfer */ 2187 2188 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2189 } 2190 2191 xhci_setup_generic_chain_sub(&temp); 2192 2193 if (xfer->flags_int.isochronous_xfr) { 2194 temp.offset += xfer->frlengths[x - 1]; 2195 temp.isoc_frame += temp.isoc_delta; 2196 } else { 2197 /* get next Page Cache pointer */ 2198 temp.pc = xfer->frbuffers + x; 2199 } 2200 } 2201 2202 /* check if we should append a status stage */ 2203 2204 if (xfer->flags_int.control_xfr && 2205 !xfer->flags_int.control_act) { 2206 2207 /* 2208 * Send a DATA1 message and invert the current 2209 * endpoint direction. 2210 */ 2211 temp.step_td = (xfer->nframes != 0); 2212 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2213 temp.len = 0; 2214 temp.pc = NULL; 2215 temp.shortpkt = 0; 2216 temp.last_frame = 1; 2217 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2218 2219 xhci_setup_generic_chain_sub(&temp); 2220 } 2221 2222 td = temp.td; 2223 2224 /* must have at least one frame! */ 2225 2226 xfer->td_transfer_last = td; 2227 2228 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2229} 2230 2231static void 2232xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2233{ 2234 struct usb_page_search buf_res; 2235 struct xhci_dev_ctx_addr *pdctxa; 2236 2237 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2238 2239 pdctxa = buf_res.buffer; 2240 2241 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2242 2243 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2244 2245 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2246} 2247 2248static usb_error_t 2249xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2250{ 2251 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2252 struct usb_page_search buf_inp; 2253 struct xhci_input_dev_ctx *pinp; 2254 uint32_t temp; 2255 uint8_t index; 2256 uint8_t x; 2257 2258 index = udev->controller_slot_id; 2259 2260 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2261 2262 pinp = buf_inp.buffer; 2263 2264 if (drop) { 2265 mask &= XHCI_INCTX_NON_CTRL_MASK; 2266 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2267 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2268 } else { 2269 /* 2270 * Some hardware requires that we drop the endpoint 2271 * context before adding it again: 2272 */ 2273 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2274 mask & XHCI_INCTX_NON_CTRL_MASK); 2275 2276 /* Add new endpoint context */ 2277 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2278 2279 /* find most significant set bit */ 2280 for (x = 31; x != 1; x--) { 2281 if (mask & (1 << x)) 2282 break; 2283 } 2284 2285 /* adjust */ 2286 x--; 2287 2288 /* figure out the maximum number of contexts */ 2289 if (x > sc->sc_hw.devs[index].context_num) 2290 sc->sc_hw.devs[index].context_num = x; 2291 else 2292 x = sc->sc_hw.devs[index].context_num; 2293 2294 /* update number of contexts */ 2295 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2296 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2297 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2298 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2299 } 2300 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2301 return (0); 2302} 2303 2304static usb_error_t 2305xhci_configure_endpoint(struct usb_device *udev, 2306 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2307 uint16_t interval, uint8_t max_packet_count, 2308 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2309 uint16_t max_frame_size, uint8_t ep_mode) 2310{ 2311 struct usb_page_search buf_inp; 2312 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2313 struct xhci_input_dev_ctx *pinp; 2314 uint64_t ring_addr = pepext->physaddr; 2315 uint32_t temp; 2316 uint8_t index; 2317 uint8_t epno; 2318 uint8_t type; 2319 2320 index = udev->controller_slot_id; 2321 2322 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2323 2324 pinp = buf_inp.buffer; 2325 2326 epno = edesc->bEndpointAddress; 2327 type = edesc->bmAttributes & UE_XFERTYPE; 2328 2329 if (type == UE_CONTROL) 2330 epno |= UE_DIR_IN; 2331 2332 epno = XHCI_EPNO2EPID(epno); 2333 2334 if (epno == 0) 2335 return (USB_ERR_NO_PIPE); /* invalid */ 2336 2337 if (max_packet_count == 0) 2338 return (USB_ERR_BAD_BUFSIZE); 2339 2340 max_packet_count--; 2341 2342 if (mult == 0) 2343 return (USB_ERR_BAD_BUFSIZE); 2344 2345 /* store endpoint mode */ 2346 pepext->trb_ep_mode = ep_mode; 2347 usb_pc_cpu_flush(pepext->page_cache); 2348 2349 if (ep_mode == USB_EP_MODE_STREAMS) { 2350 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2351 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2352 XHCI_EPCTX_0_LSA_SET(1); 2353 2354 ring_addr += sizeof(struct xhci_trb) * 2355 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2356 } else { 2357 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2358 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2359 XHCI_EPCTX_0_LSA_SET(0); 2360 2361 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2362 } 2363 2364 switch (udev->speed) { 2365 case USB_SPEED_FULL: 2366 case USB_SPEED_LOW: 2367 /* 1ms -> 125us */ 2368 fps_shift += 3; 2369 break; 2370 default: 2371 break; 2372 } 2373 2374 switch (type) { 2375 case UE_INTERRUPT: 2376 if (fps_shift > 3) 2377 fps_shift--; 2378 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2379 break; 2380 case UE_ISOCHRONOUS: 2381 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2382 2383 switch (udev->speed) { 2384 case USB_SPEED_SUPER: 2385 if (mult > 3) 2386 mult = 3; 2387 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2388 max_packet_count /= mult; 2389 break; 2390 default: 2391 break; 2392 } 2393 break; 2394 default: 2395 break; 2396 } 2397 2398 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2399 2400 temp = 2401 XHCI_EPCTX_1_HID_SET(0) | 2402 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2403 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2404 2405 /* 2406 * Always enable the "three strikes and you are gone" feature 2407 * except for ISOCHRONOUS endpoints. This is suggested by 2408 * section 4.3.3 in the XHCI specification about device slot 2409 * initialisation. 2410 */ 2411 if (type != UE_ISOCHRONOUS) 2412 temp |= XHCI_EPCTX_1_CERR_SET(3); 2413 2414 switch (type) { 2415 case UE_CONTROL: 2416 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2417 break; 2418 case UE_ISOCHRONOUS: 2419 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2420 break; 2421 case UE_BULK: 2422 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2423 break; 2424 default: 2425 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2426 break; 2427 } 2428 2429 /* check for IN direction */ 2430 if (epno & 1) 2431 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2432 2433 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2434 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2435 2436 switch (edesc->bmAttributes & UE_XFERTYPE) { 2437 case UE_INTERRUPT: 2438 case UE_ISOCHRONOUS: 2439 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2440 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2441 max_frame_size)); 2442 break; 2443 case UE_CONTROL: 2444 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2445 break; 2446 default: 2447 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2448 break; 2449 } 2450 2451 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2452 2453#ifdef USB_DEBUG 2454 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2455#endif 2456 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2457 2458 return (0); /* success */ 2459} 2460 2461static usb_error_t 2462xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2463{ 2464 struct xhci_endpoint_ext *pepext; 2465 struct usb_endpoint_ss_comp_descriptor *ecomp; 2466 usb_stream_t x; 2467 2468 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2469 xfer->endpoint->edesc); 2470 2471 ecomp = xfer->endpoint->ecomp; 2472 2473 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2474 uint64_t temp; 2475 2476 /* halt any transfers */ 2477 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2478 2479 /* compute start of TRB ring for stream "x" */ 2480 temp = pepext->physaddr + 2481 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2482 XHCI_SCTX_0_SCT_SEC_TR_RING; 2483 2484 /* make tree structure */ 2485 pepext->trb[(XHCI_MAX_TRANSFERS * 2486 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2487 2488 /* reserved fields */ 2489 pepext->trb[(XHCI_MAX_TRANSFERS * 2490 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2491 pepext->trb[(XHCI_MAX_TRANSFERS * 2492 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2493 } 2494 usb_pc_cpu_flush(pepext->page_cache); 2495 2496 return (xhci_configure_endpoint(xfer->xroot->udev, 2497 xfer->endpoint->edesc, pepext, 2498 xfer->interval, xfer->max_packet_count, 2499 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2500 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2501 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2502} 2503 2504static usb_error_t 2505xhci_configure_device(struct usb_device *udev) 2506{ 2507 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2508 struct usb_page_search buf_inp; 2509 struct usb_page_cache *pcinp; 2510 struct xhci_input_dev_ctx *pinp; 2511 struct usb_device *hubdev; 2512 uint32_t temp; 2513 uint32_t route; 2514 uint32_t rh_port; 2515 uint8_t is_hub; 2516 uint8_t index; 2517 uint8_t depth; 2518 2519 index = udev->controller_slot_id; 2520 2521 DPRINTF("index=%u\n", index); 2522 2523 pcinp = &sc->sc_hw.devs[index].input_pc; 2524 2525 usbd_get_page(pcinp, 0, &buf_inp); 2526 2527 pinp = buf_inp.buffer; 2528 2529 rh_port = 0; 2530 route = 0; 2531 2532 /* figure out route string and root HUB port number */ 2533 2534 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2535 2536 if (hubdev->parent_hub == NULL) 2537 break; 2538 2539 depth = hubdev->parent_hub->depth; 2540 2541 /* 2542 * NOTE: HS/FS/LS devices and the SS root HUB can have 2543 * more than 15 ports 2544 */ 2545 2546 rh_port = hubdev->port_no; 2547 2548 if (depth == 0) 2549 break; 2550 2551 if (rh_port > 15) 2552 rh_port = 15; 2553 2554 if (depth < 6) 2555 route |= rh_port << (4 * (depth - 1)); 2556 } 2557 2558 DPRINTF("Route=0x%08x\n", route); 2559 2560 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2561 XHCI_SCTX_0_CTX_NUM_SET( 2562 sc->sc_hw.devs[index].context_num + 1); 2563 2564 switch (udev->speed) { 2565 case USB_SPEED_LOW: 2566 temp |= XHCI_SCTX_0_SPEED_SET(2); 2567 if (udev->parent_hs_hub != NULL && 2568 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2569 UDPROTO_HSHUBMTT) { 2570 DPRINTF("Device inherits MTT\n"); 2571 temp |= XHCI_SCTX_0_MTT_SET(1); 2572 } 2573 break; 2574 case USB_SPEED_HIGH: 2575 temp |= XHCI_SCTX_0_SPEED_SET(3); 2576 if (sc->sc_hw.devs[index].nports != 0 && 2577 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2578 DPRINTF("HUB supports MTT\n"); 2579 temp |= XHCI_SCTX_0_MTT_SET(1); 2580 } 2581 break; 2582 case USB_SPEED_FULL: 2583 temp |= XHCI_SCTX_0_SPEED_SET(1); 2584 if (udev->parent_hs_hub != NULL && 2585 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2586 UDPROTO_HSHUBMTT) { 2587 DPRINTF("Device inherits MTT\n"); 2588 temp |= XHCI_SCTX_0_MTT_SET(1); 2589 } 2590 break; 2591 default: 2592 temp |= XHCI_SCTX_0_SPEED_SET(4); 2593 break; 2594 } 2595 2596 is_hub = sc->sc_hw.devs[index].nports != 0 && 2597 (udev->speed == USB_SPEED_SUPER || 2598 udev->speed == USB_SPEED_HIGH); 2599 2600 if (is_hub) 2601 temp |= XHCI_SCTX_0_HUB_SET(1); 2602 2603 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2604 2605 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2606 2607 if (is_hub) { 2608 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2609 sc->sc_hw.devs[index].nports); 2610 } 2611 2612 switch (udev->speed) { 2613 case USB_SPEED_SUPER: 2614 switch (sc->sc_hw.devs[index].state) { 2615 case XHCI_ST_ADDRESSED: 2616 case XHCI_ST_CONFIGURED: 2617 /* enable power save */ 2618 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2619 break; 2620 default: 2621 /* disable power save */ 2622 break; 2623 } 2624 break; 2625 default: 2626 break; 2627 } 2628 2629 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2630 2631 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2632 2633 if (is_hub) { 2634 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2635 sc->sc_hw.devs[index].tt); 2636 } 2637 2638 hubdev = udev->parent_hs_hub; 2639 2640 /* check if we should activate the transaction translator */ 2641 switch (udev->speed) { 2642 case USB_SPEED_FULL: 2643 case USB_SPEED_LOW: 2644 if (hubdev != NULL) { 2645 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2646 hubdev->controller_slot_id); 2647 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2648 udev->hs_port_no); 2649 } 2650 break; 2651 default: 2652 break; 2653 } 2654 2655 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2656 2657 /* 2658 * These fields should be initialized to zero, according to 2659 * XHCI section 6.2.2 - slot context: 2660 */ 2661 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2662 XHCI_SCTX_3_SLOT_STATE_SET(0); 2663 2664 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2665 2666#ifdef USB_DEBUG 2667 xhci_dump_device(sc, &pinp->ctx_slot); 2668#endif 2669 usb_pc_cpu_flush(pcinp); 2670 2671 return (0); /* success */ 2672} 2673 2674static usb_error_t 2675xhci_alloc_device_ext(struct usb_device *udev) 2676{ 2677 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2678 struct usb_page_search buf_dev; 2679 struct usb_page_search buf_ep; 2680 struct xhci_trb *trb; 2681 struct usb_page_cache *pc; 2682 struct usb_page *pg; 2683 uint64_t addr; 2684 uint8_t index; 2685 uint8_t i; 2686 2687 index = udev->controller_slot_id; 2688 2689 pc = &sc->sc_hw.devs[index].device_pc; 2690 pg = &sc->sc_hw.devs[index].device_pg; 2691 2692 /* need to initialize the page cache */ 2693 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2694 2695 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2696 (2 * sizeof(struct xhci_dev_ctx)) : 2697 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2698 goto error; 2699 2700 usbd_get_page(pc, 0, &buf_dev); 2701 2702 pc = &sc->sc_hw.devs[index].input_pc; 2703 pg = &sc->sc_hw.devs[index].input_pg; 2704 2705 /* need to initialize the page cache */ 2706 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2707 2708 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2709 (2 * sizeof(struct xhci_input_dev_ctx)) : 2710 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2711 goto error; 2712 } 2713 2714 /* initialize all endpoint LINK TRBs */ 2715 2716 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2717 2718 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2719 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2720 2721 /* need to initialize the page cache */ 2722 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2723 2724 if (usb_pc_alloc_mem(pc, pg, 2725 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2726 goto error; 2727 } 2728 2729 /* lookup endpoint TRB ring */ 2730 usbd_get_page(pc, 0, &buf_ep); 2731 2732 /* get TRB pointer */ 2733 trb = buf_ep.buffer; 2734 trb += XHCI_MAX_TRANSFERS - 1; 2735 2736 /* get TRB start address */ 2737 addr = buf_ep.physaddr; 2738 2739 /* create LINK TRB */ 2740 trb->qwTrb0 = htole64(addr); 2741 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2742 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2743 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2744 2745 usb_pc_cpu_flush(pc); 2746 } 2747 2748 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2749 2750 return (0); 2751 2752error: 2753 xhci_free_device_ext(udev); 2754 2755 return (USB_ERR_NOMEM); 2756} 2757 2758static void 2759xhci_free_device_ext(struct usb_device *udev) 2760{ 2761 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2762 uint8_t index; 2763 uint8_t i; 2764 2765 index = udev->controller_slot_id; 2766 xhci_set_slot_pointer(sc, index, 0); 2767 2768 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2769 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2770 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2771 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2772} 2773 2774static struct xhci_endpoint_ext * 2775xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2776{ 2777 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2778 struct xhci_endpoint_ext *pepext; 2779 struct usb_page_cache *pc; 2780 struct usb_page_search buf_ep; 2781 uint8_t epno; 2782 uint8_t index; 2783 2784 epno = edesc->bEndpointAddress; 2785 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2786 epno |= UE_DIR_IN; 2787 2788 epno = XHCI_EPNO2EPID(epno); 2789 2790 index = udev->controller_slot_id; 2791 2792 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2793 2794 usbd_get_page(pc, 0, &buf_ep); 2795 2796 pepext = &sc->sc_hw.devs[index].endp[epno]; 2797 pepext->page_cache = pc; 2798 pepext->trb = buf_ep.buffer; 2799 pepext->physaddr = buf_ep.physaddr; 2800 2801 return (pepext); 2802} 2803 2804static void 2805xhci_endpoint_doorbell(struct usb_xfer *xfer) 2806{ 2807 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2808 uint8_t epno; 2809 uint8_t index; 2810 2811 epno = xfer->endpointno; 2812 if (xfer->flags_int.control_xfr) 2813 epno |= UE_DIR_IN; 2814 2815 epno = XHCI_EPNO2EPID(epno); 2816 index = xfer->xroot->udev->controller_slot_id; 2817 2818 if (xfer->xroot->udev->flags.self_suspended == 0) { 2819 XWRITE4(sc, door, XHCI_DOORBELL(index), 2820 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2821 } 2822} 2823 2824static void 2825xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2826{ 2827 struct xhci_endpoint_ext *pepext; 2828 2829 if (xfer->flags_int.bandwidth_reclaimed) { 2830 xfer->flags_int.bandwidth_reclaimed = 0; 2831 2832 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2833 xfer->endpoint->edesc); 2834 2835 pepext->trb_used[xfer->stream_id]--; 2836 2837 pepext->xfer[xfer->qh_pos] = NULL; 2838 2839 if (error && pepext->trb_running != 0) { 2840 pepext->trb_halted = 1; 2841 pepext->trb_running = 0; 2842 } 2843 } 2844} 2845 2846static usb_error_t 2847xhci_transfer_insert(struct usb_xfer *xfer) 2848{ 2849 struct xhci_td *td_first; 2850 struct xhci_td *td_last; 2851 struct xhci_trb *trb_link; 2852 struct xhci_endpoint_ext *pepext; 2853 uint64_t addr; 2854 usb_stream_t id; 2855 uint8_t i; 2856 uint8_t inext; 2857 uint8_t trb_limit; 2858 2859 DPRINTFN(8, "\n"); 2860 2861 id = xfer->stream_id; 2862 2863 /* check if already inserted */ 2864 if (xfer->flags_int.bandwidth_reclaimed) { 2865 DPRINTFN(8, "Already in schedule\n"); 2866 return (0); 2867 } 2868 2869 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2870 xfer->endpoint->edesc); 2871 2872 td_first = xfer->td_transfer_first; 2873 td_last = xfer->td_transfer_last; 2874 addr = pepext->physaddr; 2875 2876 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2877 case UE_CONTROL: 2878 case UE_INTERRUPT: 2879 /* single buffered */ 2880 trb_limit = 1; 2881 break; 2882 default: 2883 /* multi buffered */ 2884 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2885 break; 2886 } 2887 2888 if (pepext->trb_used[id] >= trb_limit) { 2889 DPRINTFN(8, "Too many TDs queued.\n"); 2890 return (USB_ERR_NOMEM); 2891 } 2892 2893 /* check for stopped condition, after putting transfer on interrupt queue */ 2894 if (pepext->trb_running == 0) { 2895 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2896 2897 DPRINTFN(8, "Not running\n"); 2898 2899 /* start configuration */ 2900 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2901 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2902 return (0); 2903 } 2904 2905 pepext->trb_used[id]++; 2906 2907 /* get current TRB index */ 2908 i = pepext->trb_index[id]; 2909 2910 /* get next TRB index */ 2911 inext = (i + 1); 2912 2913 /* the last entry of the ring is a hardcoded link TRB */ 2914 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2915 inext = 0; 2916 2917 /* store next TRB index, before stream ID offset is added */ 2918 pepext->trb_index[id] = inext; 2919 2920 /* offset for stream */ 2921 i += id * XHCI_MAX_TRANSFERS; 2922 inext += id * XHCI_MAX_TRANSFERS; 2923 2924 /* compute terminating return address */ 2925 addr += (inext * sizeof(struct xhci_trb)); 2926 2927 /* compute link TRB pointer */ 2928 trb_link = td_last->td_trb + td_last->ntrb; 2929 2930 /* update next pointer of last link TRB */ 2931 trb_link->qwTrb0 = htole64(addr); 2932 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2933 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2934 XHCI_TRB_3_CYCLE_BIT | 2935 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2936 2937#ifdef USB_DEBUG 2938 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2939#endif 2940 usb_pc_cpu_flush(td_last->page_cache); 2941 2942 /* write ahead chain end marker */ 2943 2944 pepext->trb[inext].qwTrb0 = 0; 2945 pepext->trb[inext].dwTrb2 = 0; 2946 pepext->trb[inext].dwTrb3 = 0; 2947 2948 /* update next pointer of link TRB */ 2949 2950 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2951 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2952 2953#ifdef USB_DEBUG 2954 xhci_dump_trb(&pepext->trb[i]); 2955#endif 2956 usb_pc_cpu_flush(pepext->page_cache); 2957 2958 /* toggle cycle bit which activates the transfer chain */ 2959 2960 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2961 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2962 2963 usb_pc_cpu_flush(pepext->page_cache); 2964 2965 DPRINTF("qh_pos = %u\n", i); 2966 2967 pepext->xfer[i] = xfer; 2968 2969 xfer->qh_pos = i; 2970 2971 xfer->flags_int.bandwidth_reclaimed = 1; 2972 2973 xhci_endpoint_doorbell(xfer); 2974 2975 return (0); 2976} 2977 2978static void 2979xhci_root_intr(struct xhci_softc *sc) 2980{ 2981 uint16_t i; 2982 2983 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2984 2985 /* clear any old interrupt data */ 2986 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2987 2988 for (i = 1; i <= sc->sc_noport; i++) { 2989 /* pick out CHANGE bits from the status register */ 2990 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2991 XHCI_PS_CSC | XHCI_PS_PEC | 2992 XHCI_PS_OCC | XHCI_PS_WRC | 2993 XHCI_PS_PRC | XHCI_PS_PLC | 2994 XHCI_PS_CEC)) { 2995 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2996 DPRINTF("port %d changed\n", i); 2997 } 2998 } 2999 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3000 sizeof(sc->sc_hub_idata)); 3001} 3002 3003/*------------------------------------------------------------------------* 3004 * xhci_device_done - XHCI done handler 3005 * 3006 * NOTE: This function can be called two times in a row on 3007 * the same USB transfer. From close and from interrupt. 3008 *------------------------------------------------------------------------*/ 3009static void 3010xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3011{ 3012 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3013 xfer, xfer->endpoint, error); 3014 3015 /* remove transfer from HW queue */ 3016 xhci_transfer_remove(xfer, error); 3017 3018 /* dequeue transfer and start next transfer */ 3019 usbd_transfer_done(xfer, error); 3020} 3021 3022/*------------------------------------------------------------------------* 3023 * XHCI data transfer support (generic type) 3024 *------------------------------------------------------------------------*/ 3025static void 3026xhci_device_generic_open(struct usb_xfer *xfer) 3027{ 3028 if (xfer->flags_int.isochronous_xfr) { 3029 switch (xfer->xroot->udev->speed) { 3030 case USB_SPEED_FULL: 3031 break; 3032 default: 3033 usb_hs_bandwidth_alloc(xfer); 3034 break; 3035 } 3036 } 3037} 3038 3039static void 3040xhci_device_generic_close(struct usb_xfer *xfer) 3041{ 3042 DPRINTF("\n"); 3043 3044 xhci_device_done(xfer, USB_ERR_CANCELLED); 3045 3046 if (xfer->flags_int.isochronous_xfr) { 3047 switch (xfer->xroot->udev->speed) { 3048 case USB_SPEED_FULL: 3049 break; 3050 default: 3051 usb_hs_bandwidth_free(xfer); 3052 break; 3053 } 3054 } 3055} 3056 3057static void 3058xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3059 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3060{ 3061 struct usb_xfer *xfer; 3062 3063 /* check if there is a current transfer */ 3064 xfer = ep->endpoint_q[stream_id].curr; 3065 if (xfer == NULL) 3066 return; 3067 3068 /* 3069 * Check if the current transfer is started and then pickup 3070 * the next one, if any. Else wait for next start event due to 3071 * block on failure feature. 3072 */ 3073 if (!xfer->flags_int.bandwidth_reclaimed) 3074 return; 3075 3076 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3077 if (xfer == NULL) { 3078 /* 3079 * In case of enter we have to consider that the 3080 * transfer is queued by the USB core after the enter 3081 * method is called. 3082 */ 3083 xfer = enter_xfer; 3084 3085 if (xfer == NULL) 3086 return; 3087 } 3088 3089 /* try to multi buffer */ 3090 xhci_transfer_insert(xfer); 3091} 3092 3093static void 3094xhci_device_generic_enter(struct usb_xfer *xfer) 3095{ 3096 DPRINTF("\n"); 3097 3098 /* set up TD's and QH */ 3099 xhci_setup_generic_chain(xfer); 3100 3101 xhci_device_generic_multi_enter(xfer->endpoint, 3102 xfer->stream_id, xfer); 3103} 3104 3105static void 3106xhci_device_generic_start(struct usb_xfer *xfer) 3107{ 3108 DPRINTF("\n"); 3109 3110 /* try to insert xfer on HW queue */ 3111 xhci_transfer_insert(xfer); 3112 3113 /* try to multi buffer */ 3114 xhci_device_generic_multi_enter(xfer->endpoint, 3115 xfer->stream_id, NULL); 3116 3117 /* add transfer last on interrupt queue */ 3118 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3119 3120 /* start timeout, if any */ 3121 if (xfer->timeout != 0) 3122 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3123} 3124 3125struct usb_pipe_methods xhci_device_generic_methods = 3126{ 3127 .open = xhci_device_generic_open, 3128 .close = xhci_device_generic_close, 3129 .enter = xhci_device_generic_enter, 3130 .start = xhci_device_generic_start, 3131}; 3132 3133/*------------------------------------------------------------------------* 3134 * xhci root HUB support 3135 *------------------------------------------------------------------------* 3136 * Simulate a hardware HUB by handling all the necessary requests. 3137 *------------------------------------------------------------------------*/ 3138 3139#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3140 3141static const 3142struct usb_device_descriptor xhci_devd = 3143{ 3144 .bLength = sizeof(xhci_devd), 3145 .bDescriptorType = UDESC_DEVICE, /* type */ 3146 HSETW(.bcdUSB, 0x0300), /* USB version */ 3147 .bDeviceClass = UDCLASS_HUB, /* class */ 3148 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3149 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3150 .bMaxPacketSize = 9, /* max packet size */ 3151 HSETW(.idVendor, 0x0000), /* vendor */ 3152 HSETW(.idProduct, 0x0000), /* product */ 3153 HSETW(.bcdDevice, 0x0100), /* device version */ 3154 .iManufacturer = 1, 3155 .iProduct = 2, 3156 .iSerialNumber = 0, 3157 .bNumConfigurations = 1, /* # of configurations */ 3158}; 3159 3160static const 3161struct xhci_bos_desc xhci_bosd = { 3162 .bosd = { 3163 .bLength = sizeof(xhci_bosd.bosd), 3164 .bDescriptorType = UDESC_BOS, 3165 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3166 .bNumDeviceCaps = 3, 3167 }, 3168 .usb2extd = { 3169 .bLength = sizeof(xhci_bosd.usb2extd), 3170 .bDescriptorType = 1, 3171 .bDevCapabilityType = 2, 3172 .bmAttributes[0] = 2, 3173 }, 3174 .usbdcd = { 3175 .bLength = sizeof(xhci_bosd.usbdcd), 3176 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3177 .bDevCapabilityType = 3, 3178 .bmAttributes = 0, /* XXX */ 3179 HSETW(.wSpeedsSupported, 0x000C), 3180 .bFunctionalitySupport = 8, 3181 .bU1DevExitLat = 255, /* dummy - not used */ 3182 .wU2DevExitLat = { 0x00, 0x08 }, 3183 }, 3184 .cidd = { 3185 .bLength = sizeof(xhci_bosd.cidd), 3186 .bDescriptorType = 1, 3187 .bDevCapabilityType = 4, 3188 .bReserved = 0, 3189 .bContainerID = 0, /* XXX */ 3190 }, 3191}; 3192 3193static const 3194struct xhci_config_desc xhci_confd = { 3195 .confd = { 3196 .bLength = sizeof(xhci_confd.confd), 3197 .bDescriptorType = UDESC_CONFIG, 3198 .wTotalLength[0] = sizeof(xhci_confd), 3199 .bNumInterface = 1, 3200 .bConfigurationValue = 1, 3201 .iConfiguration = 0, 3202 .bmAttributes = UC_SELF_POWERED, 3203 .bMaxPower = 0 /* max power */ 3204 }, 3205 .ifcd = { 3206 .bLength = sizeof(xhci_confd.ifcd), 3207 .bDescriptorType = UDESC_INTERFACE, 3208 .bNumEndpoints = 1, 3209 .bInterfaceClass = UICLASS_HUB, 3210 .bInterfaceSubClass = UISUBCLASS_HUB, 3211 .bInterfaceProtocol = 0, 3212 }, 3213 .endpd = { 3214 .bLength = sizeof(xhci_confd.endpd), 3215 .bDescriptorType = UDESC_ENDPOINT, 3216 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3217 .bmAttributes = UE_INTERRUPT, 3218 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3219 .bInterval = 255, 3220 }, 3221 .endpcd = { 3222 .bLength = sizeof(xhci_confd.endpcd), 3223 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3224 .bMaxBurst = 0, 3225 .bmAttributes = 0, 3226 }, 3227}; 3228 3229static const 3230struct usb_hub_ss_descriptor xhci_hubd = { 3231 .bLength = sizeof(xhci_hubd), 3232 .bDescriptorType = UDESC_SS_HUB, 3233}; 3234 3235static usb_error_t 3236xhci_roothub_exec(struct usb_device *udev, 3237 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3238{ 3239 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3240 const char *str_ptr; 3241 const void *ptr; 3242 uint32_t port; 3243 uint32_t v; 3244 uint16_t len; 3245 uint16_t i; 3246 uint16_t value; 3247 uint16_t index; 3248 uint8_t j; 3249 usb_error_t err; 3250 3251 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3252 3253 /* buffer reset */ 3254 ptr = (const void *)&sc->sc_hub_desc; 3255 len = 0; 3256 err = 0; 3257 3258 value = UGETW(req->wValue); 3259 index = UGETW(req->wIndex); 3260 3261 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3262 "wValue=0x%04x wIndex=0x%04x\n", 3263 req->bmRequestType, req->bRequest, 3264 UGETW(req->wLength), value, index); 3265 3266#define C(x,y) ((x) | ((y) << 8)) 3267 switch (C(req->bRequest, req->bmRequestType)) { 3268 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3269 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3270 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3271 /* 3272 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3273 * for the integrated root hub. 3274 */ 3275 break; 3276 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3277 len = 1; 3278 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3279 break; 3280 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3281 switch (value >> 8) { 3282 case UDESC_DEVICE: 3283 if ((value & 0xff) != 0) { 3284 err = USB_ERR_IOERROR; 3285 goto done; 3286 } 3287 len = sizeof(xhci_devd); 3288 ptr = (const void *)&xhci_devd; 3289 break; 3290 3291 case UDESC_BOS: 3292 if ((value & 0xff) != 0) { 3293 err = USB_ERR_IOERROR; 3294 goto done; 3295 } 3296 len = sizeof(xhci_bosd); 3297 ptr = (const void *)&xhci_bosd; 3298 break; 3299 3300 case UDESC_CONFIG: 3301 if ((value & 0xff) != 0) { 3302 err = USB_ERR_IOERROR; 3303 goto done; 3304 } 3305 len = sizeof(xhci_confd); 3306 ptr = (const void *)&xhci_confd; 3307 break; 3308 3309 case UDESC_STRING: 3310 switch (value & 0xff) { 3311 case 0: /* Language table */ 3312 str_ptr = "\001"; 3313 break; 3314 3315 case 1: /* Vendor */ 3316 str_ptr = sc->sc_vendor; 3317 break; 3318 3319 case 2: /* Product */ 3320 str_ptr = "XHCI root HUB"; 3321 break; 3322 3323 default: 3324 str_ptr = ""; 3325 break; 3326 } 3327 3328 len = usb_make_str_desc( 3329 sc->sc_hub_desc.temp, 3330 sizeof(sc->sc_hub_desc.temp), 3331 str_ptr); 3332 break; 3333 3334 default: 3335 err = USB_ERR_IOERROR; 3336 goto done; 3337 } 3338 break; 3339 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3340 len = 1; 3341 sc->sc_hub_desc.temp[0] = 0; 3342 break; 3343 case C(UR_GET_STATUS, UT_READ_DEVICE): 3344 len = 2; 3345 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3346 break; 3347 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3348 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3349 len = 2; 3350 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3351 break; 3352 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3353 if (value >= XHCI_MAX_DEVICES) { 3354 err = USB_ERR_IOERROR; 3355 goto done; 3356 } 3357 break; 3358 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3359 if (value != 0 && value != 1) { 3360 err = USB_ERR_IOERROR; 3361 goto done; 3362 } 3363 sc->sc_conf = value; 3364 break; 3365 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3366 break; 3367 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3368 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3369 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3370 err = USB_ERR_IOERROR; 3371 goto done; 3372 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3373 break; 3374 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3375 break; 3376 /* Hub requests */ 3377 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3378 break; 3379 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3380 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3381 3382 if ((index < 1) || 3383 (index > sc->sc_noport)) { 3384 err = USB_ERR_IOERROR; 3385 goto done; 3386 } 3387 port = XHCI_PORTSC(index); 3388 3389 v = XREAD4(sc, oper, port); 3390 i = XHCI_PS_PLS_GET(v); 3391 v &= ~XHCI_PS_CLEAR; 3392 3393 switch (value) { 3394 case UHF_C_BH_PORT_RESET: 3395 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3396 break; 3397 case UHF_C_PORT_CONFIG_ERROR: 3398 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3399 break; 3400 case UHF_C_PORT_SUSPEND: 3401 case UHF_C_PORT_LINK_STATE: 3402 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3403 break; 3404 case UHF_C_PORT_CONNECTION: 3405 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3406 break; 3407 case UHF_C_PORT_ENABLE: 3408 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3409 break; 3410 case UHF_C_PORT_OVER_CURRENT: 3411 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3412 break; 3413 case UHF_C_PORT_RESET: 3414 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3415 break; 3416 case UHF_PORT_ENABLE: 3417 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3418 break; 3419 case UHF_PORT_POWER: 3420 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3421 break; 3422 case UHF_PORT_INDICATOR: 3423 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3424 break; 3425 case UHF_PORT_SUSPEND: 3426 3427 /* U3 -> U15 */ 3428 if (i == 3) { 3429 XWRITE4(sc, oper, port, v | 3430 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3431 } 3432 3433 /* wait 20ms for resume sequence to complete */ 3434 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3435 3436 /* U0 */ 3437 XWRITE4(sc, oper, port, v | 3438 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3439 break; 3440 default: 3441 err = USB_ERR_IOERROR; 3442 goto done; 3443 } 3444 break; 3445 3446 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3447 if ((value & 0xff) != 0) { 3448 err = USB_ERR_IOERROR; 3449 goto done; 3450 } 3451 3452 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3453 3454 sc->sc_hub_desc.hubd = xhci_hubd; 3455 3456 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3457 3458 if (XHCI_HCS0_PPC(v)) 3459 i = UHD_PWR_INDIVIDUAL; 3460 else 3461 i = UHD_PWR_GANGED; 3462 3463 if (XHCI_HCS0_PIND(v)) 3464 i |= UHD_PORT_IND; 3465 3466 i |= UHD_OC_INDIVIDUAL; 3467 3468 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3469 3470 /* see XHCI section 5.4.9: */ 3471 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3472 3473 for (j = 1; j <= sc->sc_noport; j++) { 3474 3475 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3476 if (v & XHCI_PS_DR) { 3477 sc->sc_hub_desc.hubd. 3478 DeviceRemovable[j / 8] |= 1U << (j % 8); 3479 } 3480 } 3481 len = sc->sc_hub_desc.hubd.bLength; 3482 break; 3483 3484 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3485 len = 16; 3486 memset(sc->sc_hub_desc.temp, 0, 16); 3487 break; 3488 3489 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3490 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3491 3492 if ((index < 1) || 3493 (index > sc->sc_noport)) { 3494 err = USB_ERR_IOERROR; 3495 goto done; 3496 } 3497 3498 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3499 3500 DPRINTFN(9, "port status=0x%08x\n", v); 3501 3502 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3503 3504 switch (XHCI_PS_SPEED_GET(v)) { 3505 case 3: 3506 i |= UPS_HIGH_SPEED; 3507 break; 3508 case 2: 3509 i |= UPS_LOW_SPEED; 3510 break; 3511 case 1: 3512 /* FULL speed */ 3513 break; 3514 default: 3515 i |= UPS_OTHER_SPEED; 3516 break; 3517 } 3518 3519 if (v & XHCI_PS_CCS) 3520 i |= UPS_CURRENT_CONNECT_STATUS; 3521 if (v & XHCI_PS_PED) 3522 i |= UPS_PORT_ENABLED; 3523 if (v & XHCI_PS_OCA) 3524 i |= UPS_OVERCURRENT_INDICATOR; 3525 if (v & XHCI_PS_PR) 3526 i |= UPS_RESET; 3527 if (v & XHCI_PS_PP) { 3528 /* 3529 * The USB 3.0 RH is using the 3530 * USB 2.0's power bit 3531 */ 3532 i |= UPS_PORT_POWER; 3533 } 3534 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3535 3536 i = 0; 3537 if (v & XHCI_PS_CSC) 3538 i |= UPS_C_CONNECT_STATUS; 3539 if (v & XHCI_PS_PEC) 3540 i |= UPS_C_PORT_ENABLED; 3541 if (v & XHCI_PS_OCC) 3542 i |= UPS_C_OVERCURRENT_INDICATOR; 3543 if (v & XHCI_PS_WRC) 3544 i |= UPS_C_BH_PORT_RESET; 3545 if (v & XHCI_PS_PRC) 3546 i |= UPS_C_PORT_RESET; 3547 if (v & XHCI_PS_PLC) 3548 i |= UPS_C_PORT_LINK_STATE; 3549 if (v & XHCI_PS_CEC) 3550 i |= UPS_C_PORT_CONFIG_ERROR; 3551 3552 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3553 len = sizeof(sc->sc_hub_desc.ps); 3554 break; 3555 3556 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3557 err = USB_ERR_IOERROR; 3558 goto done; 3559 3560 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3561 break; 3562 3563 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3564 3565 i = index >> 8; 3566 index &= 0x00FF; 3567 3568 if ((index < 1) || 3569 (index > sc->sc_noport)) { 3570 err = USB_ERR_IOERROR; 3571 goto done; 3572 } 3573 3574 port = XHCI_PORTSC(index); 3575 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3576 3577 switch (value) { 3578 case UHF_PORT_U1_TIMEOUT: 3579 if (XHCI_PS_SPEED_GET(v) != 4) { 3580 err = USB_ERR_IOERROR; 3581 goto done; 3582 } 3583 port = XHCI_PORTPMSC(index); 3584 v = XREAD4(sc, oper, port); 3585 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3586 v |= XHCI_PM3_U1TO_SET(i); 3587 XWRITE4(sc, oper, port, v); 3588 break; 3589 case UHF_PORT_U2_TIMEOUT: 3590 if (XHCI_PS_SPEED_GET(v) != 4) { 3591 err = USB_ERR_IOERROR; 3592 goto done; 3593 } 3594 port = XHCI_PORTPMSC(index); 3595 v = XREAD4(sc, oper, port); 3596 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3597 v |= XHCI_PM3_U2TO_SET(i); 3598 XWRITE4(sc, oper, port, v); 3599 break; 3600 case UHF_BH_PORT_RESET: 3601 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3602 break; 3603 case UHF_PORT_LINK_STATE: 3604 XWRITE4(sc, oper, port, v | 3605 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3606 /* 4ms settle time */ 3607 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3608 break; 3609 case UHF_PORT_ENABLE: 3610 DPRINTFN(3, "set port enable %d\n", index); 3611 break; 3612 case UHF_PORT_SUSPEND: 3613 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3614 j = XHCI_PS_SPEED_GET(v); 3615 if ((j < 1) || (j > 3)) { 3616 /* non-supported speed */ 3617 err = USB_ERR_IOERROR; 3618 goto done; 3619 } 3620 XWRITE4(sc, oper, port, v | 3621 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3622 break; 3623 case UHF_PORT_RESET: 3624 DPRINTFN(6, "reset port %d\n", index); 3625 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3626 break; 3627 case UHF_PORT_POWER: 3628 DPRINTFN(3, "set port power %d\n", index); 3629 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3630 break; 3631 case UHF_PORT_TEST: 3632 DPRINTFN(3, "set port test %d\n", index); 3633 break; 3634 case UHF_PORT_INDICATOR: 3635 DPRINTFN(3, "set port indicator %d\n", index); 3636 3637 v &= ~XHCI_PS_PIC_SET(3); 3638 v |= XHCI_PS_PIC_SET(1); 3639 3640 XWRITE4(sc, oper, port, v); 3641 break; 3642 default: 3643 err = USB_ERR_IOERROR; 3644 goto done; 3645 } 3646 break; 3647 3648 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3649 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3650 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3651 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3652 break; 3653 default: 3654 err = USB_ERR_IOERROR; 3655 goto done; 3656 } 3657done: 3658 *plength = len; 3659 *pptr = ptr; 3660 return (err); 3661} 3662 3663static void 3664xhci_xfer_setup(struct usb_setup_params *parm) 3665{ 3666 struct usb_page_search page_info; 3667 struct usb_page_cache *pc; 3668 struct xhci_softc *sc; 3669 struct usb_xfer *xfer; 3670 void *last_obj; 3671 uint32_t ntd; 3672 uint32_t n; 3673 3674 sc = XHCI_BUS2SC(parm->udev->bus); 3675 xfer = parm->curr_xfer; 3676 3677 /* 3678 * The proof for the "ntd" formula is illustrated like this: 3679 * 3680 * +------------------------------------+ 3681 * | | 3682 * | |remainder -> | 3683 * | +-----+---+ | 3684 * | | xxx | x | frm 0 | 3685 * | +-----+---++ | 3686 * | | xxx | xx | frm 1 | 3687 * | +-----+----+ | 3688 * | ... | 3689 * +------------------------------------+ 3690 * 3691 * "xxx" means a completely full USB transfer descriptor 3692 * 3693 * "x" and "xx" means a short USB packet 3694 * 3695 * For the remainder of an USB transfer modulo 3696 * "max_data_length" we need two USB transfer descriptors. 3697 * One to transfer the remaining data and one to finalise with 3698 * a zero length packet in case the "force_short_xfer" flag is 3699 * set. We only need two USB transfer descriptors in the case 3700 * where the transfer length of the first one is a factor of 3701 * "max_frame_size". The rest of the needed USB transfer 3702 * descriptors is given by the buffer size divided by the 3703 * maximum data payload. 3704 */ 3705 parm->hc_max_packet_size = 0x400; 3706 parm->hc_max_packet_count = 16 * 3; 3707 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3708 3709 xfer->flags_int.bdma_enable = 1; 3710 3711 usbd_transfer_setup_sub(parm); 3712 3713 if (xfer->flags_int.isochronous_xfr) { 3714 ntd = ((1 * xfer->nframes) 3715 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3716 } else if (xfer->flags_int.control_xfr) { 3717 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3718 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3719 } else { 3720 ntd = ((2 * xfer->nframes) 3721 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3722 } 3723 3724alloc_dma_set: 3725 3726 if (parm->err) 3727 return; 3728 3729 /* 3730 * Allocate queue heads and transfer descriptors 3731 */ 3732 last_obj = NULL; 3733 3734 if (usbd_transfer_setup_sub_malloc( 3735 parm, &pc, sizeof(struct xhci_td), 3736 XHCI_TD_ALIGN, ntd)) { 3737 parm->err = USB_ERR_NOMEM; 3738 return; 3739 } 3740 if (parm->buf) { 3741 for (n = 0; n != ntd; n++) { 3742 struct xhci_td *td; 3743 3744 usbd_get_page(pc + n, 0, &page_info); 3745 3746 td = page_info.buffer; 3747 3748 /* init TD */ 3749 td->td_self = page_info.physaddr; 3750 td->obj_next = last_obj; 3751 td->page_cache = pc + n; 3752 3753 last_obj = td; 3754 3755 usb_pc_cpu_flush(pc + n); 3756 } 3757 } 3758 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3759 3760 if (!xfer->flags_int.curr_dma_set) { 3761 xfer->flags_int.curr_dma_set = 1; 3762 goto alloc_dma_set; 3763 } 3764} 3765 3766static usb_error_t 3767xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3768{ 3769 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3770 struct usb_page_search buf_inp; 3771 struct usb_device *udev; 3772 struct xhci_endpoint_ext *pepext; 3773 struct usb_endpoint_descriptor *edesc; 3774 struct usb_page_cache *pcinp; 3775 usb_error_t err; 3776 usb_stream_t stream_id; 3777 uint8_t index; 3778 uint8_t epno; 3779 3780 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3781 xfer->endpoint->edesc); 3782 3783 udev = xfer->xroot->udev; 3784 index = udev->controller_slot_id; 3785 3786 pcinp = &sc->sc_hw.devs[index].input_pc; 3787 3788 usbd_get_page(pcinp, 0, &buf_inp); 3789 3790 edesc = xfer->endpoint->edesc; 3791 3792 epno = edesc->bEndpointAddress; 3793 stream_id = xfer->stream_id; 3794 3795 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3796 epno |= UE_DIR_IN; 3797 3798 epno = XHCI_EPNO2EPID(epno); 3799 3800 if (epno == 0) 3801 return (USB_ERR_NO_PIPE); /* invalid */ 3802 3803 XHCI_CMD_LOCK(sc); 3804 3805 /* configure endpoint */ 3806 3807 err = xhci_configure_endpoint_by_xfer(xfer); 3808 3809 if (err != 0) { 3810 XHCI_CMD_UNLOCK(sc); 3811 return (err); 3812 } 3813 3814 /* 3815 * Get the endpoint into the stopped state according to the 3816 * endpoint context state diagram in the XHCI specification: 3817 */ 3818 3819 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3820 3821 if (err != 0) 3822 DPRINTF("Could not stop endpoint %u\n", epno); 3823 3824 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3825 3826 if (err != 0) 3827 DPRINTF("Could not reset endpoint %u\n", epno); 3828 3829 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3830 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3831 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3832 stream_id, epno, index); 3833 3834 if (err != 0) 3835 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3836 3837 /* 3838 * Get the endpoint into the running state according to the 3839 * endpoint context state diagram in the XHCI specification: 3840 */ 3841 3842 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3843 3844 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3845 3846 if (err != 0) 3847 DPRINTF("Could not configure endpoint %u\n", epno); 3848 3849 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3850 3851 if (err != 0) 3852 DPRINTF("Could not configure endpoint %u\n", epno); 3853 3854 XHCI_CMD_UNLOCK(sc); 3855 3856 return (0); 3857} 3858 3859static void 3860xhci_xfer_unsetup(struct usb_xfer *xfer) 3861{ 3862 return; 3863} 3864 3865static void 3866xhci_start_dma_delay(struct usb_xfer *xfer) 3867{ 3868 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3869 3870 /* put transfer on interrupt queue (again) */ 3871 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3872 3873 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3874 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3875} 3876 3877static void 3878xhci_configure_msg(struct usb_proc_msg *pm) 3879{ 3880 struct xhci_softc *sc; 3881 struct xhci_endpoint_ext *pepext; 3882 struct usb_xfer *xfer; 3883 3884 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3885 3886restart: 3887 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3888 3889 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3890 xfer->endpoint->edesc); 3891 3892 if ((pepext->trb_halted != 0) || 3893 (pepext->trb_running == 0)) { 3894 3895 uint16_t i; 3896 3897 /* clear halted and running */ 3898 pepext->trb_halted = 0; 3899 pepext->trb_running = 0; 3900 3901 /* nuke remaining buffered transfers */ 3902 3903 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3904 XHCI_MAX_STREAMS); i++) { 3905 /* 3906 * NOTE: We need to use the timeout 3907 * error code here else existing 3908 * isochronous clients can get 3909 * confused: 3910 */ 3911 if (pepext->xfer[i] != NULL) { 3912 xhci_device_done(pepext->xfer[i], 3913 USB_ERR_TIMEOUT); 3914 } 3915 } 3916 3917 /* 3918 * NOTE: The USB transfer cannot vanish in 3919 * this state! 3920 */ 3921 3922 USB_BUS_UNLOCK(&sc->sc_bus); 3923 3924 xhci_configure_reset_endpoint(xfer); 3925 3926 USB_BUS_LOCK(&sc->sc_bus); 3927 3928 /* check if halted is still cleared */ 3929 if (pepext->trb_halted == 0) { 3930 pepext->trb_running = 1; 3931 memset(pepext->trb_index, 0, 3932 sizeof(pepext->trb_index)); 3933 } 3934 goto restart; 3935 } 3936 3937 if (xfer->flags_int.did_dma_delay) { 3938 3939 /* remove transfer from interrupt queue (again) */ 3940 usbd_transfer_dequeue(xfer); 3941 3942 /* we are finally done */ 3943 usb_dma_delay_done_cb(xfer); 3944 3945 /* queue changed - restart */ 3946 goto restart; 3947 } 3948 } 3949 3950 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3951 3952 /* try to insert xfer on HW queue */ 3953 xhci_transfer_insert(xfer); 3954 3955 /* try to multi buffer */ 3956 xhci_device_generic_multi_enter(xfer->endpoint, 3957 xfer->stream_id, NULL); 3958 } 3959} 3960 3961static void 3962xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3963 struct usb_endpoint *ep) 3964{ 3965 struct xhci_endpoint_ext *pepext; 3966 3967 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3968 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3969 3970 if (udev->parent_hub == NULL) { 3971 /* root HUB has special endpoint handling */ 3972 return; 3973 } 3974 3975 ep->methods = &xhci_device_generic_methods; 3976 3977 pepext = xhci_get_endpoint_ext(udev, edesc); 3978 3979 USB_BUS_LOCK(udev->bus); 3980 pepext->trb_halted = 1; 3981 pepext->trb_running = 0; 3982 USB_BUS_UNLOCK(udev->bus); 3983} 3984 3985static void 3986xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3987{ 3988 3989} 3990 3991static void 3992xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3993{ 3994 struct xhci_endpoint_ext *pepext; 3995 3996 DPRINTF("\n"); 3997 3998 if (udev->flags.usb_mode != USB_MODE_HOST) { 3999 /* not supported */ 4000 return; 4001 } 4002 if (udev->parent_hub == NULL) { 4003 /* root HUB has special endpoint handling */ 4004 return; 4005 } 4006 4007 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4008 4009 USB_BUS_LOCK(udev->bus); 4010 pepext->trb_halted = 1; 4011 pepext->trb_running = 0; 4012 USB_BUS_UNLOCK(udev->bus); 4013} 4014 4015static usb_error_t 4016xhci_device_init(struct usb_device *udev) 4017{ 4018 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4019 usb_error_t err; 4020 uint8_t temp; 4021 4022 /* no init for root HUB */ 4023 if (udev->parent_hub == NULL) 4024 return (0); 4025 4026 XHCI_CMD_LOCK(sc); 4027 4028 /* set invalid default */ 4029 4030 udev->controller_slot_id = sc->sc_noslot + 1; 4031 4032 /* try to get a new slot ID from the XHCI */ 4033 4034 err = xhci_cmd_enable_slot(sc, &temp); 4035 4036 if (err) { 4037 XHCI_CMD_UNLOCK(sc); 4038 return (err); 4039 } 4040 4041 if (temp > sc->sc_noslot) { 4042 XHCI_CMD_UNLOCK(sc); 4043 return (USB_ERR_BAD_ADDRESS); 4044 } 4045 4046 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4047 DPRINTF("slot %u already allocated.\n", temp); 4048 XHCI_CMD_UNLOCK(sc); 4049 return (USB_ERR_BAD_ADDRESS); 4050 } 4051 4052 /* store slot ID for later reference */ 4053 4054 udev->controller_slot_id = temp; 4055 4056 /* reset data structure */ 4057 4058 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4059 4060 /* set mark slot allocated */ 4061 4062 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4063 4064 err = xhci_alloc_device_ext(udev); 4065 4066 XHCI_CMD_UNLOCK(sc); 4067 4068 /* get device into default state */ 4069 4070 if (err == 0) 4071 err = xhci_set_address(udev, NULL, 0); 4072 4073 return (err); 4074} 4075 4076static void 4077xhci_device_uninit(struct usb_device *udev) 4078{ 4079 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4080 uint8_t index; 4081 4082 /* no init for root HUB */ 4083 if (udev->parent_hub == NULL) 4084 return; 4085 4086 XHCI_CMD_LOCK(sc); 4087 4088 index = udev->controller_slot_id; 4089 4090 if (index <= sc->sc_noslot) { 4091 xhci_cmd_disable_slot(sc, index); 4092 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4093 4094 /* free device extension */ 4095 xhci_free_device_ext(udev); 4096 } 4097 4098 XHCI_CMD_UNLOCK(sc); 4099} 4100 4101static void 4102xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4103{ 4104 /* 4105 * Wait until the hardware has finished any possible use of 4106 * the transfer descriptor(s) 4107 */ 4108 *pus = 2048; /* microseconds */ 4109} 4110 4111static void 4112xhci_device_resume(struct usb_device *udev) 4113{ 4114 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4115 uint8_t index; 4116 uint8_t n; 4117 uint8_t p; 4118 4119 DPRINTF("\n"); 4120 4121 /* check for root HUB */ 4122 if (udev->parent_hub == NULL) 4123 return; 4124 4125 index = udev->controller_slot_id; 4126 4127 XHCI_CMD_LOCK(sc); 4128 4129 /* blindly resume all endpoints */ 4130 4131 USB_BUS_LOCK(udev->bus); 4132 4133 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4134 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4135 XWRITE4(sc, door, XHCI_DOORBELL(index), 4136 n | XHCI_DB_SID_SET(p)); 4137 } 4138 } 4139 4140 USB_BUS_UNLOCK(udev->bus); 4141 4142 XHCI_CMD_UNLOCK(sc); 4143} 4144 4145static void 4146xhci_device_suspend(struct usb_device *udev) 4147{ 4148 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4149 uint8_t index; 4150 uint8_t n; 4151 usb_error_t err; 4152 4153 DPRINTF("\n"); 4154 4155 /* check for root HUB */ 4156 if (udev->parent_hub == NULL) 4157 return; 4158 4159 index = udev->controller_slot_id; 4160 4161 XHCI_CMD_LOCK(sc); 4162 4163 /* blindly suspend all endpoints */ 4164 4165 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4166 err = xhci_cmd_stop_ep(sc, 1, n, index); 4167 if (err != 0) { 4168 DPRINTF("Failed to suspend endpoint " 4169 "%u on slot %u (ignored).\n", n, index); 4170 } 4171 } 4172 4173 XHCI_CMD_UNLOCK(sc); 4174} 4175 4176static void 4177xhci_set_hw_power(struct usb_bus *bus) 4178{ 4179 DPRINTF("\n"); 4180} 4181 4182static void 4183xhci_device_state_change(struct usb_device *udev) 4184{ 4185 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4186 struct usb_page_search buf_inp; 4187 usb_error_t err; 4188 uint8_t index; 4189 4190 /* check for root HUB */ 4191 if (udev->parent_hub == NULL) 4192 return; 4193 4194 index = udev->controller_slot_id; 4195 4196 DPRINTF("\n"); 4197 4198 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4199 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4200 &sc->sc_hw.devs[index].tt); 4201 if (err != 0) 4202 sc->sc_hw.devs[index].nports = 0; 4203 } 4204 4205 XHCI_CMD_LOCK(sc); 4206 4207 switch (usb_get_device_state(udev)) { 4208 case USB_STATE_POWERED: 4209 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4210 break; 4211 4212 /* set default state */ 4213 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4214 4215 /* reset number of contexts */ 4216 sc->sc_hw.devs[index].context_num = 0; 4217 4218 err = xhci_cmd_reset_dev(sc, index); 4219 4220 if (err != 0) { 4221 DPRINTF("Device reset failed " 4222 "for slot %u.\n", index); 4223 } 4224 break; 4225 4226 case USB_STATE_ADDRESSED: 4227 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4228 break; 4229 4230 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4231 4232 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4233 4234 if (err) { 4235 DPRINTF("Failed to deconfigure " 4236 "slot %u.\n", index); 4237 } 4238 break; 4239 4240 case USB_STATE_CONFIGURED: 4241 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4242 break; 4243 4244 /* set configured state */ 4245 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4246 4247 /* reset number of contexts */ 4248 sc->sc_hw.devs[index].context_num = 0; 4249 4250 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4251 4252 xhci_configure_mask(udev, 3, 0); 4253 4254 err = xhci_configure_device(udev); 4255 if (err != 0) { 4256 DPRINTF("Could not configure device " 4257 "at slot %u.\n", index); 4258 } 4259 4260 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4261 if (err != 0) { 4262 DPRINTF("Could not evaluate device " 4263 "context at slot %u.\n", index); 4264 } 4265 break; 4266 4267 default: 4268 break; 4269 } 4270 XHCI_CMD_UNLOCK(sc); 4271} 4272 4273static usb_error_t 4274xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4275 uint8_t ep_mode) 4276{ 4277 switch (ep_mode) { 4278 case USB_EP_MODE_DEFAULT: 4279 return (0); 4280 case USB_EP_MODE_STREAMS: 4281 if (xhcistreams == 0 || 4282 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4283 udev->speed != USB_SPEED_SUPER) 4284 return (USB_ERR_INVAL); 4285 return (0); 4286 default: 4287 return (USB_ERR_INVAL); 4288 } 4289} 4290 4291struct usb_bus_methods xhci_bus_methods = { 4292 .endpoint_init = xhci_ep_init, 4293 .endpoint_uninit = xhci_ep_uninit, 4294 .xfer_setup = xhci_xfer_setup, 4295 .xfer_unsetup = xhci_xfer_unsetup, 4296 .get_dma_delay = xhci_get_dma_delay, 4297 .device_init = xhci_device_init, 4298 .device_uninit = xhci_device_uninit, 4299 .device_resume = xhci_device_resume, 4300 .device_suspend = xhci_device_suspend, 4301 .set_hw_power = xhci_set_hw_power, 4302 .roothub_exec = xhci_roothub_exec, 4303 .xfer_poll = xhci_do_poll, 4304 .start_dma_delay = xhci_start_dma_delay, 4305 .set_address = xhci_set_address, 4306 .clear_stall = xhci_ep_clear_stall, 4307 .device_state_change = xhci_device_state_change, 4308 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4309 .set_endpoint_mode = xhci_set_endpoint_mode, 4310}; 4311