imx_gpt.c revision 266152
1314565Smm/*- 2314565Smm * Copyright (c) 2012, 2013 The FreeBSD Foundation 3314565Smm * All rights reserved. 4314565Smm * 5314565Smm * This software was developed by Oleksandr Rybalko under sponsorship 6314565Smm * from the FreeBSD Foundation. 7314565Smm * 8314565Smm * Redistribution and use in source and binary forms, with or without 9314565Smm * modification, are permitted provided that the following conditions 10314565Smm * are met: 11314565Smm * 1. Redistributions of source code must retain the above copyright 12314565Smm * notice, this list of conditions and the following disclaimer. 13314565Smm * 2. Redistributions in binary form must reproduce the above copyright 14314565Smm * notice, this list of conditions and the following disclaimer in the 15314565Smm * documentation and/or other materials provided with the distribution. 16314565Smm * 17314565Smm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18314565Smm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19314565Smm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20314565Smm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21314565Smm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22314565Smm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23314565Smm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24314565Smm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25314565Smm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26314565Smm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27314565Smm * SUCH DAMAGE. 28314565Smm */ 29314565Smm 30314565Smm#include <sys/cdefs.h> 31314565Smm__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx_gpt.c 266152 2014-05-15 16:11:06Z ian $"); 32314565Smm 33314565Smm#include <sys/param.h> 34314565Smm#include <sys/systm.h> 35314565Smm#include <sys/bus.h> 36314565Smm#include <sys/kernel.h> 37314565Smm#include <sys/module.h> 38314565Smm#include <sys/malloc.h> 39314565Smm#include <sys/rman.h> 40314565Smm#include <sys/timeet.h> 41358090Smm#include <sys/timetc.h> 42358090Smm#include <sys/watchdog.h> 43358090Smm#include <machine/bus.h> 44314565Smm#include <machine/cpu.h> 45314565Smm#include <machine/intr.h> 46314565Smm 47314565Smm#include <machine/fdt.h> 48314565Smm#include <dev/fdt/fdt_common.h> 49314565Smm#include <dev/ofw/openfirm.h> 50314565Smm#include <dev/ofw/ofw_bus.h> 51314565Smm#include <dev/ofw/ofw_bus_subr.h> 52314565Smm 53314565Smm#include <arm/freescale/imx/imx_gptvar.h> 54314565Smm#include <arm/freescale/imx/imx_gptreg.h> 55314565Smm 56314565Smm#include <sys/kdb.h> 57314565Smm#include <arm/freescale/imx/imx51_ccmvar.h> 58314565Smm 59314565Smm#define WRITE4(_sc, _r, _v) \ 60314565Smm bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 61314565Smm#define READ4(_sc, _r) \ 62314565Smm bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 63314565Smm#define SET4(_sc, _r, _m) \ 64314565Smm WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 65314565Smm#define CLEAR4(_sc, _r, _m) \ 66314565Smm WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 67314565Smm 68314565Smmstatic u_int imx_gpt_get_timecount(struct timecounter *); 69314565Smmstatic int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 70314565Smm sbintime_t); 71314565Smmstatic int imx_gpt_timer_stop(struct eventtimer *); 72314565Smm 73314565Smmstatic int imx_gpt_intr(void *); 74314565Smmstatic int imx_gpt_probe(device_t); 75314565Smmstatic int imx_gpt_attach(device_t); 76314565Smm 77314565Smmstatic struct timecounter imx_gpt_timecounter = { 78314565Smm .tc_name = "i.MX GPT Timecounter", 79314571Smm .tc_get_timecount = imx_gpt_get_timecount, 80314571Smm .tc_counter_mask = ~0u, 81314571Smm .tc_frequency = 0, 82314571Smm .tc_quality = 1000, 83314571Smm}; 84314571Smm 85316338Smm/* Global softc pointer for use in DELAY(). */ 86316338Smmstruct imx_gpt_softc *imx_gpt_sc = NULL; 87316338Smm 88314565Smm/* 89348608Smm * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 90314565Smm * at 792mhz. It will delay a bit too long on slower processors -- that's 91348608Smm * better than not delaying long enough. In practice this is unlikely to get 92314565Smm * used much since the clock driver is one of the first to start up, and once 93314565Smm * we're attached the delay loop switches to using the timer hardware. 94314565Smm */ 95314565Smmstatic const int imx_gpt_delay_count = 78; 96314565Smm 97314565Smm/* Try to divide down an available fast clock to this frequency. */ 98314565Smm#define TARGET_FREQUENCY 10000000 99314565Smm 100314565Smm/* Don't try to set an event timer period smaller than this. */ 101314565Smm#define MIN_ET_PERIOD 10LLU 102314565Smm 103314565Smm 104314565Smmstatic struct resource_spec imx_gpt_spec[] = { 105314565Smm { SYS_RES_MEMORY, 0, RF_ACTIVE }, 106314565Smm { SYS_RES_IRQ, 0, RF_ACTIVE }, 107314565Smm { -1, 0 } 108314565Smm}; 109314565Smm 110314565Smmstatic struct ofw_compat_data compat_data[] = { 111314565Smm {"fsl,imx6q-gpt", 1}, 112314565Smm {"fsl,imx53-gpt", 1}, 113314565Smm {"fsl,imx51-gpt", 1}, 114314565Smm {"fsl,imx31-gpt", 1}, 115314565Smm {"fsl,imx27-gpt", 1}, 116314565Smm {"fsl,imx25-gpt", 1}, 117314565Smm {NULL, 0} 118358090Smm}; 119358090Smm 120358090Smmstatic int 121358090Smmimx_gpt_probe(device_t dev) 122358090Smm{ 123358090Smm 124358090Smm if (!ofw_bus_status_okay(dev)) 125358090Smm return (ENXIO); 126358090Smm 127358090Smm if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 128358090Smm device_set_desc(dev, "Freescale i.MX GPT timer"); 129358090Smm return (BUS_PROBE_DEFAULT); 130358090Smm } 131314565Smm 132314565Smm return (ENXIO); 133314565Smm} 134314565Smm 135314565Smmstatic int 136314565Smmimx_gpt_attach(device_t dev) 137314565Smm{ 138314565Smm struct imx_gpt_softc *sc; 139314565Smm int ctlreg, err; 140314565Smm uint32_t basefreq, prescale; 141314565Smm 142314565Smm sc = device_get_softc(dev); 143314565Smm 144314565Smm if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 145314565Smm device_printf(dev, "could not allocate resources\n"); 146314565Smm return (ENXIO); 147314565Smm } 148314565Smm 149314565Smm sc->sc_dev = dev; 150314565Smm sc->sc_iot = rman_get_bustag(sc->res[0]); 151358090Smm sc->sc_ioh = rman_get_bushandle(sc->res[0]); 152358090Smm 153358090Smm /* 154358090Smm * For now, just automatically choose a good clock for the hardware 155316338Smm * we're running on. Eventually we could allow selection from the fdt; 156314571Smm * the code in this driver will cope with any clock frequency. 157314571Smm */ 158314571Smm sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 159316338Smm 160316338Smm ctlreg = 0; 161314565Smm 162314565Smm switch (sc->sc_clksrc) { 163314565Smm case GPT_CR_CLKSRC_32K: 164314565Smm basefreq = 32768; 165314565Smm break; 166314565Smm case GPT_CR_CLKSRC_IPG: 167314565Smm basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); 168314565Smm break; 169314565Smm case GPT_CR_CLKSRC_IPG_HIGH: 170314565Smm basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2; 171314565Smm break; 172368708Smm case GPT_CR_CLKSRC_24M: 173368708Smm ctlreg |= GPT_CR_24MEN; 174368708Smm basefreq = 24000000; 175314571Smm break; 176314571Smm case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 177314571Smm case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 178314565Smm default: 179314565Smm device_printf(dev, "Unsupported clock source '%d'\n", 180314565Smm sc->sc_clksrc); 181314565Smm return (EINVAL); 182314565Smm } 183314565Smm 184314565Smm /* 185314565Smm * The following setup sequence is from the I.MX6 reference manual, 186314565Smm * "Selecting the clock source". First, disable the clock and 187314565Smm * interrupts. This also clears input and output mode bits and in 188314565Smm * general completes several of the early steps in the procedure. 189314565Smm */ 190314565Smm WRITE4(sc, IMX_GPT_CR, 0); 191314565Smm WRITE4(sc, IMX_GPT_IR, 0); 192314565Smm 193314565Smm /* Choose the clock and the power-saving behaviors. */ 194314565Smm ctlreg |= 195314565Smm sc->sc_clksrc | /* Use selected clock */ 196314565Smm GPT_CR_FRR | /* Just count (FreeRunner mode) */ 197314565Smm GPT_CR_STOPEN | /* Run in STOP mode */ 198314565Smm GPT_CR_DOZEEN | /* Run in DOZE mode */ 199314565Smm GPT_CR_WAITEN | /* Run in WAIT mode */ 200314565Smm GPT_CR_DBGEN; /* Run in DEBUG mode */ 201314565Smm WRITE4(sc, IMX_GPT_CR, ctlreg); 202314565Smm 203314565Smm /* 204314565Smm * The datasheet says to do the software reset after choosing the clock 205314565Smm * source. It says nothing about needing to wait for the reset to 206314565Smm * complete, but the register description does document the fact that 207314565Smm * the reset isn't complete until the SWR bit reads 0, so let's be safe. 208314565Smm * The reset also clears all registers except for a few of the bits in 209314565Smm * CR, but we'll rewrite all the CR bits when we start the counter. 210314565Smm */ 211314565Smm WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 212314565Smm while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 213314565Smm continue; 214314565Smm 215314565Smm /* Set a prescaler value that gets us near the target frequency. */ 216314565Smm if (basefreq < TARGET_FREQUENCY) { 217314565Smm prescale = 0; 218314565Smm sc->clkfreq = basefreq; 219314565Smm } else { 220314565Smm prescale = basefreq / TARGET_FREQUENCY; 221314565Smm sc->clkfreq = basefreq / prescale; 222314565Smm prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 223314565Smm } 224314565Smm WRITE4(sc, IMX_GPT_PR, prescale); 225314565Smm 226314565Smm /* Clear the status register. */ 227314565Smm WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 228314565Smm 229314565Smm /* Start the counter. */ 230314565Smm WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 231314565Smm 232314565Smm if (bootverbose) 233314565Smm device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 234314565Smm sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 235314565Smm 236314565Smm /* Setup the timer interrupt. */ 237314565Smm err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 238314565Smm NULL, sc, &sc->sc_ih); 239314565Smm if (err != 0) { 240314565Smm bus_release_resources(dev, imx_gpt_spec, sc->res); 241314565Smm device_printf(dev, "Unable to setup the clock irq handler, " 242314565Smm "err = %d\n", err); 243314565Smm return (ENXIO); 244314565Smm } 245314565Smm 246348608Smm /* Register as an eventtimer. */ 247348608Smm sc->et.et_name = "i.MXxxx GPT Eventtimer"; 248314565Smm sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 249314565Smm sc->et.et_quality = 1000; 250314565Smm sc->et.et_frequency = sc->clkfreq; 251314565Smm sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency; 252314565Smm sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 253314565Smm sc->et.et_start = imx_gpt_timer_start; 254314565Smm sc->et.et_stop = imx_gpt_timer_stop; 255314565Smm sc->et.et_priv = sc; 256314565Smm et_register(&sc->et); 257348608Smm 258348608Smm /* Register as a timecounter. */ 259314571Smm imx_gpt_timecounter.tc_frequency = sc->clkfreq; 260314571Smm tc_init(&imx_gpt_timecounter); 261314565Smm 262314565Smm /* If this is the first unit, store the softc for use in DELAY. */ 263314571Smm if (device_get_unit(dev) == 0) 264314571Smm imx_gpt_sc = sc; 265314571Smm 266314565Smm return (0); 267314565Smm} 268314565Smm 269314565Smmstatic int 270314565Smmimx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 271314565Smm{ 272314565Smm struct imx_gpt_softc *sc; 273314565Smm uint32_t ticks; 274314565Smm 275314565Smm sc = (struct imx_gpt_softc *)et->et_priv; 276314565Smm 277314565Smm if (period != 0) { 278314565Smm sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 279314565Smm /* Set expected value */ 280314565Smm WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 281314565Smm /* Enable compare register 2 Interrupt */ 282314565Smm SET4(sc, IMX_GPT_IR, GPT_IR_OF2); 283314565Smm return (0); 284314565Smm } else if (first != 0) { 285358090Smm ticks = ((uint32_t)et->et_frequency * first) >> 32; 286314565Smm /* Do not disturb, otherwise event will be lost */ 287314565Smm spinlock_enter(); 288368708Smm /* Set expected value */ 289314571Smm WRITE4(sc, IMX_GPT_OCR1, READ4(sc, IMX_GPT_CNT) + ticks); 290314571Smm /* Enable compare register 1 Interrupt */ 291314565Smm SET4(sc, IMX_GPT_IR, GPT_IR_OF1); 292314565Smm /* Now everybody can relax */ 293314565Smm spinlock_exit(); 294314565Smm return (0); 295314565Smm } 296314565Smm 297314565Smm return (EINVAL); 298314565Smm} 299314565Smm 300314565Smmstatic int 301314565Smmimx_gpt_timer_stop(struct eventtimer *et) 302314565Smm{ 303314565Smm struct imx_gpt_softc *sc; 304314565Smm 305314565Smm sc = (struct imx_gpt_softc *)et->et_priv; 306314565Smm 307314565Smm /* Disable OF2 Interrupt */ 308314565Smm CLEAR4(sc, IMX_GPT_IR, GPT_IR_OF2); 309314565Smm WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2); 310314565Smm sc->sc_period = 0; 311314565Smm 312314565Smm return (0); 313314565Smm} 314314565Smm 315314565Smmint 316348608Smmimx_gpt_get_timerfreq(struct imx_gpt_softc *sc) 317314565Smm{ 318314565Smm 319314565Smm return (sc->clkfreq); 320348608Smm} 321314565Smm 322314571Smmvoid 323314565Smmcpu_initclocks(void) 324314565Smm{ 325314565Smm 326314565Smm if (imx_gpt_sc == NULL) { 327314565Smm panic("%s: i.MX GPT driver has not been initialized!", __func__); 328314565Smm } 329358090Smm 330314565Smm cpu_initclocks_bsp(); 331314565Smm} 332358090Smm 333314565Smmstatic int 334314565Smmimx_gpt_intr(void *arg) 335314565Smm{ 336314565Smm struct imx_gpt_softc *sc; 337314565Smm uint32_t status; 338314565Smm 339314565Smm sc = (struct imx_gpt_softc *)arg; 340314565Smm 341314565Smm status = READ4(sc, IMX_GPT_SR); 342314565Smm 343314565Smm /* 344314565Smm * Clear interrupt status before invoking event callbacks. The callback 345314565Smm * often sets up a new one-shot timer event and if the interval is short 346314565Smm * enough it can fire before we get out of this function. If we cleared 347314565Smm * at the bottom we'd miss the interrupt and hang until the clock wraps. 348314565Smm */ 349314565Smm WRITE4(sc, IMX_GPT_SR, status); 350314565Smm 351314565Smm /* Handle one-shot timer events. */ 352314565Smm if (status & GPT_IR_OF1) { 353314565Smm if (sc->et.et_active) { 354314565Smm sc->et.et_event_cb(&sc->et, sc->et.et_arg); 355314565Smm } 356314565Smm } 357314565Smm 358324418Smm /* Handle periodic timer events. */ 359324418Smm if (status & GPT_IR_OF2) { 360324418Smm if (sc->et.et_active) 361314565Smm sc->et.et_event_cb(&sc->et, sc->et.et_arg); 362314565Smm if (sc->sc_period != 0) 363314565Smm WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 364314565Smm sc->sc_period); 365314565Smm } 366314565Smm 367314565Smm return (FILTER_HANDLED); 368314565Smm} 369314565Smm 370314565Smmu_int 371314565Smmimx_gpt_get_timecount(struct timecounter *tc) 372314565Smm{ 373314565Smm 374314565Smm if (imx_gpt_sc == NULL) 375314565Smm return (0); 376314571Smm 377314571Smm return (READ4(imx_gpt_sc, IMX_GPT_CNT)); 378314571Smm} 379316338Smm 380353377Smmstatic device_method_t imx_gpt_methods[] = { 381316338Smm DEVMETHOD(device_probe, imx_gpt_probe), 382316338Smm DEVMETHOD(device_attach, imx_gpt_attach), 383316338Smm 384316338Smm DEVMETHOD_END 385314565Smm}; 386314565Smm 387314565Smmstatic driver_t imx_gpt_driver = { 388316338Smm "imx_gpt", 389314571Smm imx_gpt_methods, 390314571Smm sizeof(struct imx_gpt_softc), 391314571Smm}; 392314571Smm 393314565Smmstatic devclass_t imx_gpt_devclass; 394314565Smm 395358090SmmEARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 396314565Smm 0, BUS_PASS_TIMER); 397314565Smm 398314565Smmvoid 399314565SmmDELAY(int usec) 400314565Smm{ 401314565Smm uint64_t curcnt, endcnt, startcnt, ticks; 402314565Smm 403314565Smm /* If the timer hardware is not accessible, just use a loop. */ 404314565Smm if (imx_gpt_sc == NULL) { 405314565Smm while (usec-- > 0) 406314565Smm for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 407314565Smm cpufunc_nullop(); 408314565Smm return; 409314565Smm } 410314565Smm 411314565Smm /* 412314565Smm * Calculate the tick count with 64-bit values so that it works for any 413314565Smm * clock frequency. Loop until the hardware count reaches start+ticks. 414314565Smm * If the 32-bit hardware count rolls over while we're looping, just 415314565Smm * manually do a carry into the high bits after each read; don't worry 416314565Smm * that doing this on each loop iteration is inefficient -- we're trying 417314565Smm * to waste time here. 418314565Smm */ 419314565Smm ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 420314565Smm curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 421314565Smm endcnt = startcnt + ticks; 422314565Smm while (curcnt < endcnt) { 423314565Smm curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 424314565Smm if (curcnt < startcnt) 425314565Smm curcnt += 1ULL << 32; 426314565Smm } 427314565Smm} 428314565Smm