imx6_ssi.c revision 283500 
1/*-
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * i.MX6 Synchronous Serial Interface (SSI)
29 *
30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual,
31 * Rev. 1, 04/2013
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx6_ssi.c 283500 2015-05-24 18:59:45Z ian $");
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/malloc.h>
43#include <sys/rman.h>
44#include <sys/timeet.h>
45#include <sys/timetc.h>
46
47#include <dev/sound/pcm/sound.h>
48#include <dev/sound/chip.h>
49#include <mixer_if.h>
50
51#include <dev/fdt/fdt_common.h>
52#include <dev/ofw/openfirm.h>
53#include <dev/ofw/ofw_bus.h>
54#include <dev/ofw/ofw_bus_subr.h>
55
56#include <machine/bus.h>
57#include <machine/fdt.h>
58#include <machine/cpu.h>
59#include <machine/intr.h>
60
61#include <arm/freescale/imx/imx6_sdma.h>
62#include <arm/freescale/imx/imx6_anatopvar.h>
63#include <arm/freescale/imx/imx_ccmvar.h>
64
65#define	READ4(_sc, _reg)	\
66	bus_space_read_4(_sc->bst, _sc->bsh, _reg)
67#define	WRITE4(_sc, _reg, _val)	\
68	bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
69
70#define	SSI_NCHANNELS	1
71
72/* i.MX6 SSI registers */
73
74#define	SSI_STX0	0x00 /* Transmit Data Register n */
75#define	SSI_STX1	0x04 /* Transmit Data Register n */
76#define	SSI_SRX0	0x08 /* Receive Data Register n */
77#define	SSI_SRX1	0x0C /* Receive Data Register n */
78#define	SSI_SCR		0x10 /* Control Register */
79#define	 SCR_I2S_MODE_S	5    /* I2S Mode Select. */
80#define	 SCR_I2S_MODE_M	0x3
81#define	 SCR_SYN	(1 << 4)
82#define	 SCR_NET       	(1 << 3)  /* Network mode */
83#define	 SCR_RE		(1 << 2)  /* Receive Enable. */
84#define	 SCR_TE		(1 << 1)  /* Transmit Enable. */
85#define	 SCR_SSIEN	(1 << 0)  /* SSI Enable */
86#define	SSI_SISR	0x14      /* Interrupt Status Register */
87#define	SSI_SIER	0x18      /* Interrupt Enable Register */
88#define	 SIER_RDMAE	(1 << 22) /* Receive DMA Enable. */
89#define	 SIER_RIE	(1 << 21) /* Receive Interrupt Enable. */
90#define	 SIER_TDMAE	(1 << 20) /* Transmit DMA Enable. */
91#define	 SIER_TIE	(1 << 19) /* Transmit Interrupt Enable. */
92#define	 SIER_TDE0IE	(1 << 12) /* Transmit Data Register Empty 0. */
93#define	 SIER_TUE0IE	(1 << 8)  /* Transmitter Underrun Error 0. */
94#define	 SIER_TFE0IE	(1 << 0)  /* Transmit FIFO Empty 0 IE. */
95#define	SSI_STCR	0x1C	  /* Transmit Configuration Register */
96#define	 STCR_TXBIT0	(1 << 9)  /* Transmit Bit 0 shift MSB/LSB */
97#define	 STCR_TFEN1	(1 << 8)  /* Transmit FIFO Enable 1. */
98#define	 STCR_TFEN0	(1 << 7)  /* Transmit FIFO Enable 0. */
99#define	 STCR_TFDIR	(1 << 6)  /* Transmit Frame Direction. */
100#define	 STCR_TXDIR	(1 << 5)  /* Transmit Clock Direction. */
101#define	 STCR_TSHFD	(1 << 4)  /* Transmit Shift Direction. */
102#define	 STCR_TSCKP	(1 << 3)  /* Transmit Clock Polarity. */
103#define	 STCR_TFSI	(1 << 2)  /* Transmit Frame Sync Invert. */
104#define	 STCR_TFSL	(1 << 1)  /* Transmit Frame Sync Length. */
105#define	 STCR_TEFS	(1 << 0)  /* Transmit Early Frame Sync. */
106#define	SSI_SRCR	0x20      /* Receive Configuration Register */
107#define	SSI_STCCR	0x24      /* Transmit Clock Control Register */
108#define	 STCCR_DIV2	(1 << 18) /* Divide By 2. */
109#define	 STCCR_PSR	(1 << 17) /* Divide clock by 8. */
110#define	 WL3_WL0_S	13
111#define	 WL3_WL0_M	0xf
112#define	 DC4_DC0_S	8
113#define	 DC4_DC0_M	0x1f
114#define	 PM7_PM0_S	0
115#define	 PM7_PM0_M	0xff
116#define	SSI_SRCCR	0x28	/* Receive Clock Control Register */
117#define	SSI_SFCSR	0x2C	/* FIFO Control/Status Register */
118#define	 SFCSR_RFWM1_S	20	/* Receive FIFO Empty WaterMark 1 */
119#define	 SFCSR_RFWM1_M	0xf
120#define	 SFCSR_TFWM1_S	16	/* Transmit FIFO Empty WaterMark 1 */
121#define	 SFCSR_TFWM1_M	0xf
122#define	 SFCSR_RFWM0_S	4	/* Receive FIFO Empty WaterMark 0 */
123#define	 SFCSR_RFWM0_M	0xf
124#define	 SFCSR_TFWM0_S	0	/* Transmit FIFO Empty WaterMark 0 */
125#define	 SFCSR_TFWM0_M	0xf
126#define	SSI_SACNT	0x38	/* AC97 Control Register */
127#define	SSI_SACADD	0x3C	/* AC97 Command Address Register */
128#define	SSI_SACDAT	0x40	/* AC97 Command Data Register */
129#define	SSI_SATAG	0x44	/* AC97 Tag Register */
130#define	SSI_STMSK	0x48	/* Transmit Time Slot Mask Register */
131#define	SSI_SRMSK	0x4C	/* Receive Time Slot Mask Register */
132#define	SSI_SACCST	0x50	/* AC97 Channel Status Register */
133#define	SSI_SACCEN	0x54	/* AC97 Channel Enable Register */
134#define	SSI_SACCDIS	0x58	/* AC97 Channel Disable Register */
135
136static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio");
137
138uint32_t ssi_dma_intr(void *arg, int chn);
139
140struct ssi_rate {
141	uint32_t speed;
142	uint32_t mfi; /* PLL4 Multiplication Factor Integer */
143	uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
144	uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
145	/* More dividers to configure can be added here */
146};
147
148static struct ssi_rate rate_map[] = {
149	{ 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
150	/* TODO: add more frequences */
151	{ 0, 0 },
152};
153
154/*
155 *  i.MX6 example bit clock formula
156 *
157 *  BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz =
158 *     (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
159 *             ^     ^     ^      ^    ^   ^   ^   ^   ^   ^   ^
160 *             |     |     |      |    |   |   |   |   |   |   |
161 *  Fref ------/     |     |      |    |   |   |   |   |   |   |
162 *  PLL4 div select -/     |      |    |   |   |   |   |   |   |
163 *  PLL4 num --------------/      |    |   |   |   |   |   |   |
164 *  PLL4 denom -------------------/    |   |   |   |   |   |   |
165 *  PLL4 post div ---------------------/   |   |   |   |   |   |
166 *  CCM ssi pre div (CCM_CS1CDR) ----------/   |   |   |   |   |
167 *  CCM ssi post div (CCM_CS1CDR) -------------/   |   |   |   |
168 *  SSI PM7_PM0_S ---------------------------------/   |   |   |
169 *  SSI Fixed divider ---------------------------------/   |   |
170 *  SSI DIV2 ----------------------------------------------/   |
171 *  SSI PSR (prescaler /1 or /8) ------------------------------/
172 *
173 *  MCLK (Master clock) depends on DAC, usually BCLK * 4
174 */
175
176struct sc_info {
177	struct resource		*res[2];
178	bus_space_tag_t		bst;
179	bus_space_handle_t	bsh;
180	device_t		dev;
181	struct mtx		*lock;
182	void			*ih;
183	int			pos;
184	int			dma_size;
185	bus_dma_tag_t		dma_tag;
186	bus_dmamap_t		dma_map;
187	bus_addr_t		buf_base_phys;
188	uint32_t		*buf_base;
189	struct sdma_conf	*conf;
190	struct ssi_rate		*sr;
191	struct sdma_softc	*sdma_sc;
192	int			sdma_ev_rx;
193	int			sdma_ev_tx;
194	int			sdma_channel;
195};
196
197/* Channel registers */
198struct sc_chinfo {
199	struct snd_dbuf		*buffer;
200	struct pcm_channel	*channel;
201	struct sc_pcminfo	*parent;
202
203	/* Channel information */
204	uint32_t	dir;
205	uint32_t	format;
206
207	/* Flags */
208	uint32_t	run;
209};
210
211/* PCM device private data */
212struct sc_pcminfo {
213	device_t		dev;
214	uint32_t		(*ih)(struct sc_pcminfo *scp);
215	uint32_t		chnum;
216	struct sc_chinfo	chan[SSI_NCHANNELS];
217	struct sc_info		*sc;
218};
219
220static struct resource_spec ssi_spec[] = {
221	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
222	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
223	{ -1, 0 }
224};
225
226static int setup_dma(struct sc_pcminfo *scp);
227static void setup_ssi(struct sc_info *);
228static void ssi_configure_clock(struct sc_info *);
229
230/*
231 * Mixer interface.
232 */
233
234static int
235ssimixer_init(struct snd_mixer *m)
236{
237	struct sc_pcminfo *scp;
238	struct sc_info *sc;
239	int mask;
240
241	scp = mix_getdevinfo(m);
242	sc = scp->sc;
243
244	if (sc == NULL)
245		return -1;
246
247	mask = SOUND_MASK_PCM;
248	mask |= SOUND_MASK_VOLUME;
249
250	snd_mtxlock(sc->lock);
251	pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
252	mix_setdevs(m, mask);
253	snd_mtxunlock(sc->lock);
254
255	return (0);
256}
257
258static int
259ssimixer_set(struct snd_mixer *m, unsigned dev,
260    unsigned left, unsigned right)
261{
262	struct sc_pcminfo *scp;
263
264	scp = mix_getdevinfo(m);
265
266	/* Here we can configure hardware volume on our DAC */
267
268#if 1
269	device_printf(scp->dev, "ssimixer_set() %d %d\n",
270	    left, right);
271#endif
272
273	return (0);
274}
275
276static kobj_method_t ssimixer_methods[] = {
277	KOBJMETHOD(mixer_init,      ssimixer_init),
278	KOBJMETHOD(mixer_set,       ssimixer_set),
279	KOBJMETHOD_END
280};
281MIXER_DECLARE(ssimixer);
282
283
284/*
285 * Channel interface.
286 */
287
288static void *
289ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
290    struct pcm_channel *c, int dir)
291{
292	struct sc_pcminfo *scp;
293	struct sc_chinfo *ch;
294	struct sc_info *sc;
295
296	scp = (struct sc_pcminfo *)devinfo;
297	sc = scp->sc;
298
299	snd_mtxlock(sc->lock);
300	ch = &scp->chan[0];
301	ch->dir = dir;
302	ch->run = 0;
303	ch->buffer = b;
304	ch->channel = c;
305	ch->parent = scp;
306	snd_mtxunlock(sc->lock);
307
308	if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
309		device_printf(scp->dev, "Can't setup sndbuf.\n");
310		return NULL;
311	}
312
313	return ch;
314}
315
316static int
317ssichan_free(kobj_t obj, void *data)
318{
319	struct sc_chinfo *ch = data;
320	struct sc_pcminfo *scp = ch->parent;
321	struct sc_info *sc = scp->sc;
322
323#if 0
324	device_printf(scp->dev, "ssichan_free()\n");
325#endif
326
327	snd_mtxlock(sc->lock);
328	/* TODO: free channel buffer */
329	snd_mtxunlock(sc->lock);
330
331	return (0);
332}
333
334static int
335ssichan_setformat(kobj_t obj, void *data, uint32_t format)
336{
337	struct sc_chinfo *ch = data;
338
339	ch->format = format;
340
341	return (0);
342}
343
344static uint32_t
345ssichan_setspeed(kobj_t obj, void *data, uint32_t speed)
346{
347	struct sc_pcminfo *scp;
348	struct sc_chinfo *ch;
349	struct ssi_rate *sr;
350	struct sc_info *sc;
351	int threshold;
352	int i;
353
354	ch = data;
355	scp = ch->parent;
356	sc = scp->sc;
357
358	sr = NULL;
359
360	/* First look for equal frequency. */
361	for (i = 0; rate_map[i].speed != 0; i++) {
362		if (rate_map[i].speed == speed)
363			sr = &rate_map[i];
364	}
365
366	/* If no match, just find nearest. */
367	if (sr == NULL) {
368		for (i = 0; rate_map[i].speed != 0; i++) {
369			sr = &rate_map[i];
370			threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
371			    ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
372			if (speed < threshold)
373				break;
374		}
375	}
376
377	sc->sr = sr;
378
379	ssi_configure_clock(sc);
380
381	return (sr->speed);
382}
383
384static void
385ssi_configure_clock(struct sc_info *sc)
386{
387	struct ssi_rate *sr;
388
389	sr = sc->sr;
390
391	pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
392
393	/* Configure other dividers here, if any */
394}
395
396static uint32_t
397ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
398{
399	struct sc_chinfo *ch = data;
400	struct sc_pcminfo *scp = ch->parent;
401	struct sc_info *sc = scp->sc;
402
403	sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
404
405	setup_dma(scp);
406
407	return (sndbuf_getblksz(ch->buffer));
408}
409
410uint32_t
411ssi_dma_intr(void *arg, int chn)
412{
413	struct sc_pcminfo *scp;
414	struct sdma_conf *conf;
415	struct sc_chinfo *ch;
416	struct sc_info *sc;
417	int bufsize;
418
419	scp = arg;
420	ch = &scp->chan[0];
421	sc = scp->sc;
422	conf = sc->conf;
423
424	bufsize = sndbuf_getsize(ch->buffer);
425
426	sc->pos += conf->period;
427	if (sc->pos >= bufsize)
428		sc->pos -= bufsize;
429
430	if (ch->run)
431		chn_intr(ch->channel);
432
433	return (0);
434}
435
436static int
437find_sdma_controller(struct sc_info *sc)
438{
439	struct sdma_softc *sdma_sc;
440	phandle_t node, sdma_node;
441	device_t sdma_dev;
442	int dts_value[8];
443	int len;
444
445	if ((node = ofw_bus_get_node(sc->dev)) == -1)
446		return (ENXIO);
447
448	if ((len = OF_getproplen(node, "dmas")) <= 0)
449		return (ENXIO);
450
451	OF_getprop(node, "dmas", &dts_value, len);
452
453	sc->sdma_ev_rx = fdt32_to_cpu(dts_value[1]);
454	sc->sdma_ev_tx = fdt32_to_cpu(dts_value[5]);
455
456	sdma_node = OF_node_from_xref(fdt32_to_cpu(dts_value[0]));
457
458	sdma_sc = NULL;
459
460	sdma_dev = devclass_get_device(devclass_find("sdma"), 0);
461	if (sdma_dev)
462		sdma_sc = device_get_softc(sdma_dev);
463
464	if (sdma_sc == NULL) {
465		device_printf(sc->dev, "No sDMA found. Can't operate\n");
466		return (ENXIO);
467	};
468
469	sc->sdma_sc = sdma_sc;
470
471	return (0);
472};
473
474static int
475setup_dma(struct sc_pcminfo *scp)
476{
477	struct sdma_conf *conf;
478	struct sc_chinfo *ch;
479	struct sc_info *sc;
480	int fmt;
481
482	ch = &scp->chan[0];
483	sc = scp->sc;
484	conf = sc->conf;
485
486	conf->ih = ssi_dma_intr;
487	conf->ih_user = scp;
488	conf->saddr = sc->buf_base_phys;
489	conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;
490	conf->event = sc->sdma_ev_tx; /* SDMA TX event */
491	conf->period = sndbuf_getblksz(ch->buffer);
492	conf->num_bd = sndbuf_getblkcnt(ch->buffer);
493
494	/*
495	 * Word Length
496	 * Can be 32, 24, 16 or 8 for sDMA.
497	 *
498	 * SSI supports 24 at max.
499	 */
500
501	fmt = sndbuf_getfmt(ch->buffer);
502
503	if (fmt & AFMT_16BIT) {
504		conf->word_length = 16;
505		conf->command = CMD_2BYTES;
506	} else if (fmt & AFMT_24BIT) {
507		conf->word_length = 24;
508		conf->command = CMD_3BYTES;
509	} else {
510		device_printf(sc->dev, "Unknown format\n");
511		return (-1);
512	}
513
514	return (0);
515}
516
517static int
518ssi_start(struct sc_pcminfo *scp)
519{
520	struct sc_info *sc;
521	int reg;
522
523	sc = scp->sc;
524
525	if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {
526		device_printf(sc->dev, "Can't configure sDMA\n");
527		return (-1);
528	}
529
530	/* Enable DMA interrupt */
531	reg = (SIER_TDMAE);
532	WRITE4(sc, SSI_SIER, reg);
533
534	sdma_start(sc->sdma_channel);
535
536	return (0);
537}
538
539static int
540ssi_stop(struct sc_pcminfo *scp)
541{
542	struct sc_info *sc;
543	int reg;
544
545	sc = scp->sc;
546
547	reg = READ4(sc, SSI_SIER);
548	reg &= ~(SIER_TDMAE);
549	WRITE4(sc, SSI_SIER, reg);
550
551	sdma_stop(sc->sdma_channel);
552
553	bzero(sc->buf_base, sc->dma_size);
554
555	return (0);
556}
557
558static int
559ssichan_trigger(kobj_t obj, void *data, int go)
560{
561	struct sc_pcminfo *scp;
562	struct sc_chinfo *ch;
563	struct sc_info *sc;
564
565	ch = data;
566	scp = ch->parent;
567	sc = scp->sc;
568
569	snd_mtxlock(sc->lock);
570
571	switch (go) {
572	case PCMTRIG_START:
573#if 0
574		device_printf(scp->dev, "trigger start\n");
575#endif
576		ch->run = 1;
577
578		ssi_start(scp);
579
580		break;
581
582	case PCMTRIG_STOP:
583	case PCMTRIG_ABORT:
584#if 0
585		device_printf(scp->dev, "trigger stop or abort\n");
586#endif
587		ch->run = 0;
588
589		ssi_stop(scp);
590
591		break;
592	}
593
594	snd_mtxunlock(sc->lock);
595
596	return (0);
597}
598
599static uint32_t
600ssichan_getptr(kobj_t obj, void *data)
601{
602	struct sc_pcminfo *scp;
603	struct sc_chinfo *ch;
604	struct sc_info *sc;
605
606	ch = data;
607	scp = ch->parent;
608	sc = scp->sc;
609
610	return (sc->pos);
611}
612
613static uint32_t ssi_pfmt[] = {
614	SND_FORMAT(AFMT_S24_LE, 2, 0),
615	0
616};
617
618static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0};
619
620static struct pcmchan_caps *
621ssichan_getcaps(kobj_t obj, void *data)
622{
623
624	return (&ssi_pcaps);
625}
626
627static kobj_method_t ssichan_methods[] = {
628	KOBJMETHOD(channel_init,         ssichan_init),
629	KOBJMETHOD(channel_free,         ssichan_free),
630	KOBJMETHOD(channel_setformat,    ssichan_setformat),
631	KOBJMETHOD(channel_setspeed,     ssichan_setspeed),
632	KOBJMETHOD(channel_setblocksize, ssichan_setblocksize),
633	KOBJMETHOD(channel_trigger,      ssichan_trigger),
634	KOBJMETHOD(channel_getptr,       ssichan_getptr),
635	KOBJMETHOD(channel_getcaps,      ssichan_getcaps),
636	KOBJMETHOD_END
637};
638CHANNEL_DECLARE(ssichan);
639
640static int
641ssi_probe(device_t dev)
642{
643
644	if (!ofw_bus_status_okay(dev))
645		return (ENXIO);
646
647	if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))
648		return (ENXIO);
649
650	device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)");
651	return (BUS_PROBE_DEFAULT);
652}
653
654static void
655ssi_intr(void *arg)
656{
657	struct sc_pcminfo *scp;
658	struct sc_chinfo *ch;
659	struct sc_info *sc;
660
661	scp = arg;
662	sc = scp->sc;
663	ch = &scp->chan[0];
664
665	/* We don't use SSI interrupt */
666#if 0
667	device_printf(sc->dev, "SSI Intr 0x%08x\n",
668	    READ4(sc, SSI_SISR));
669#endif
670}
671
672static void
673setup_ssi(struct sc_info *sc)
674{
675	int reg;
676
677	reg = READ4(sc, SSI_STCCR);
678	reg &= ~(WL3_WL0_M << WL3_WL0_S);
679	reg |= (0xb << WL3_WL0_S); /* 24 bit */
680	reg &= ~(DC4_DC0_M << DC4_DC0_S);
681	reg |= (1 << DC4_DC0_S); /* 2 words per frame */
682	reg &= ~(STCCR_DIV2); /* Divide by 1 */
683	reg &= ~(STCCR_PSR); /* Divide by 1 */
684	reg &= ~(PM7_PM0_M << PM7_PM0_S);
685	reg |= (1 << PM7_PM0_S); /* Divide by 2 */
686	WRITE4(sc, SSI_STCCR, reg);
687
688	reg = READ4(sc, SSI_SFCSR);
689	reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);
690	reg |= (8 << SFCSR_TFWM0_S); /* empty slots */
691	WRITE4(sc, SSI_SFCSR, reg);
692
693	reg = READ4(sc, SSI_STCR);
694	reg |= (STCR_TFEN0);
695	reg &= ~(STCR_TFEN1);
696	reg &= ~(STCR_TSHFD); /* MSB */
697	reg |= (STCR_TXBIT0);
698	reg |= (STCR_TXDIR | STCR_TFDIR);
699	reg |= (STCR_TSCKP); /* falling edge */
700	reg |= (STCR_TFSI);
701	reg &= ~(STCR_TFSI); /* active high frame sync */
702	reg &= ~(STCR_TFSL);
703	reg |= STCR_TEFS;
704	WRITE4(sc, SSI_STCR, reg);
705
706	reg = READ4(sc, SSI_SCR);
707	reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */
708	reg |= (SCR_SSIEN | SCR_TE);
709	reg |= (SCR_NET);
710	reg |= (SCR_SYN);
711	WRITE4(sc, SSI_SCR, reg);
712}
713
714static void
715ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
716{
717	bus_addr_t *addr;
718
719	if (err)
720		return;
721
722	addr = (bus_addr_t*)arg;
723	*addr = segs[0].ds_addr;
724}
725
726static int
727ssi_attach(device_t dev)
728{
729	char status[SND_STATUSLEN];
730	struct sc_pcminfo *scp;
731	struct sc_info *sc;
732	int err;
733
734	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
735	sc->dev = dev;
736	sc->sr = &rate_map[0];
737	sc->pos = 0;
738	sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);
739
740	sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc");
741	if (sc->lock == NULL) {
742		device_printf(dev, "Cant create mtx\n");
743		return (ENXIO);
744	}
745
746	if (bus_alloc_resources(dev, ssi_spec, sc->res)) {
747		device_printf(dev, "could not allocate resources\n");
748		return (ENXIO);
749	}
750
751	/* Memory interface */
752	sc->bst = rman_get_bustag(sc->res[0]);
753	sc->bsh = rman_get_bushandle(sc->res[0]);
754
755	/* SDMA */
756	if (find_sdma_controller(sc)) {
757		device_printf(dev, "could not find active SDMA\n");
758		return (ENXIO);
759	}
760
761	/* Setup PCM */
762	scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
763	scp->sc = sc;
764	scp->dev = dev;
765
766	/*
767	 * Maximum possible DMA buffer.
768	 * Will be used partialy to match 24 bit word.
769	 */
770	sc->dma_size = 131072;
771
772	/*
773	 * Must use dma_size boundary as modulo feature required.
774	 * Modulo feature allows setup circular buffer.
775	 */
776
777	err = bus_dma_tag_create(
778	    bus_get_dma_tag(sc->dev),
779	    4, sc->dma_size,		/* alignment, boundary */
780	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
781	    BUS_SPACE_MAXADDR,		/* highaddr */
782	    NULL, NULL,			/* filter, filterarg */
783	    sc->dma_size, 1,		/* maxsize, nsegments */
784	    sc->dma_size, 0,		/* maxsegsize, flags */
785	    NULL, NULL,			/* lockfunc, lockarg */
786	    &sc->dma_tag);
787
788	err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
789	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
790	if (err) {
791		device_printf(dev, "cannot allocate framebuffer\n");
792		return (ENXIO);
793	}
794
795	err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
796	    sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
797	if (err) {
798		device_printf(dev, "cannot load DMA map\n");
799		return (ENXIO);
800	}
801
802	bzero(sc->buf_base, sc->dma_size);
803
804	/* Setup interrupt handler */
805	err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
806	    NULL, ssi_intr, scp, &sc->ih);
807	if (err) {
808		device_printf(dev, "Unable to alloc interrupt resource.\n");
809		return (ENXIO);
810	}
811
812	pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
813
814	err = pcm_register(dev, scp, 1, 0);
815	if (err) {
816		device_printf(dev, "Can't register pcm.\n");
817		return (ENXIO);
818	}
819
820	scp->chnum = 0;
821	pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp);
822	scp->chnum++;
823
824	snprintf(status, SND_STATUSLEN, "at simplebus");
825	pcm_setstatus(dev, status);
826
827	mixer_init(dev, &ssimixer_class, scp);
828	setup_ssi(sc);
829
830	imx_ccm_ssi_configure(dev);
831
832	sc->sdma_channel = sdma_alloc();
833	if (sc->sdma_channel < 0) {
834		device_printf(sc->dev, "Can't get sDMA channel\n");
835		return (1);
836	}
837
838	return (0);
839}
840
841static device_method_t ssi_pcm_methods[] = {
842	DEVMETHOD(device_probe,		ssi_probe),
843	DEVMETHOD(device_attach,	ssi_attach),
844	{ 0, 0 }
845};
846
847static driver_t ssi_pcm_driver = {
848	"pcm",
849	ssi_pcm_methods,
850	PCM_SOFTC_SIZE,
851};
852
853DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0);
854MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
855MODULE_VERSION(ssi, 1);
856