if_uralreg.h revision 261455 
1/*	$FreeBSD: stable/10/sys/dev/usb/wlan/if_uralreg.h 261455 2014-02-04 03:36:42Z eadler $	*/
2
3/*-
4 * Copyright (c) 2005, 2006
5 *	Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define RAL_NOISE_FLOOR		-95
21#define RAL_RSSI_CORR		120
22
23#define RAL_RX_DESC_SIZE	(sizeof (struct ural_rx_desc))
24#define RAL_TX_DESC_SIZE	(sizeof (struct ural_tx_desc))
25#define RAL_FRAME_SIZE		0x780	/* NOTE: using 0x980 does not work */
26
27#define RAL_CONFIG_NO	1
28#define RAL_IFACE_INDEX 0
29
30#define RAL_VENDOR_REQUEST	0x01
31#define RAL_WRITE_MAC		0x02
32#define RAL_READ_MAC		0x03
33#define RAL_WRITE_MULTI_MAC	0x06
34#define RAL_READ_MULTI_MAC	0x07
35#define RAL_READ_EEPROM		0x09
36
37/*
38 * MAC registers.
39 */
40#define RAL_MAC_CSR0	0x0400	/* ASIC Version */
41#define RAL_MAC_CSR1	0x0402	/* System control */
42#define RAL_MAC_CSR2	0x0404	/* MAC addr0 */
43#define RAL_MAC_CSR3	0x0406	/* MAC addr1 */
44#define RAL_MAC_CSR4	0x0408	/* MAC addr2 */
45#define RAL_MAC_CSR5	0x040a	/* BSSID0 */
46#define RAL_MAC_CSR6	0x040c	/* BSSID1 */
47#define RAL_MAC_CSR7	0x040e	/* BSSID2 */
48#define RAL_MAC_CSR8	0x0410	/* Max frame length */
49#define RAL_MAC_CSR9	0x0412	/* Timer control */
50#define RAL_MAC_CSR10	0x0414	/* Slot time */
51#define RAL_MAC_CSR11	0x0416	/* IFS */
52#define RAL_MAC_CSR12	0x0418	/* EIFS */
53#define RAL_MAC_CSR13	0x041a	/* Power mode0 */
54#define RAL_MAC_CSR14	0x041c	/* Power mode1 */
55#define RAL_MAC_CSR15	0x041e	/* Power saving transition0 */
56#define RAL_MAC_CSR16	0x0420	/* Power saving transition1 */
57#define RAL_MAC_CSR17	0x0422	/* Power state control */
58#define RAL_MAC_CSR18	0x0424	/* Auto wake-up control */
59#define RAL_MAC_CSR19	0x0426	/* GPIO control */
60#define RAL_MAC_CSR20	0x0428	/* LED control0 */
61#define RAL_MAC_CSR22	0x042c	/* XXX not documented */
62
63/*
64 * Tx/Rx Registers.
65 */
66#define RAL_TXRX_CSR0	0x0440	/* Security control */
67#define RAL_TXRX_CSR2	0x0444	/* Rx control */
68#define RAL_TXRX_CSR5	0x044a	/* CCK Tx BBP ID0 */
69#define RAL_TXRX_CSR6	0x044c	/* CCK Tx BBP ID1 */
70#define RAL_TXRX_CSR7	0x044e	/* OFDM Tx BBP ID0 */
71#define RAL_TXRX_CSR8	0x0450	/* OFDM Tx BBP ID1 */
72#define RAL_TXRX_CSR10	0x0454	/* Auto responder control */
73#define RAL_TXRX_CSR11	0x0456	/* Auto responder basic rate */
74#define RAL_TXRX_CSR18	0x0464	/* Beacon interval */
75#define RAL_TXRX_CSR19	0x0466	/* Beacon/sync control */
76#define RAL_TXRX_CSR20	0x0468	/* Beacon alignment */
77#define RAL_TXRX_CSR21	0x046a	/* XXX not documented */
78
79/*
80 * Security registers.
81 */
82#define RAL_SEC_CSR0	0x0480	/* Shared key 0, word 0 */
83
84/*
85 * PHY registers.
86 */
87#define RAL_PHY_CSR2	0x04c4	/* Tx MAC configuration */
88#define RAL_PHY_CSR4	0x04c8	/* Interface configuration */
89#define RAL_PHY_CSR5	0x04ca	/* BBP Pre-Tx CCK */
90#define RAL_PHY_CSR6	0x04cc	/* BBP Pre-Tx OFDM */
91#define RAL_PHY_CSR7	0x04ce	/* BBP serial control */
92#define RAL_PHY_CSR8	0x04d0	/* BBP serial status */
93#define RAL_PHY_CSR9	0x04d2	/* RF serial control0 */
94#define RAL_PHY_CSR10	0x04d4	/* RF serial control1 */
95
96/*
97 * Statistics registers.
98 */
99#define RAL_STA_CSR0	0x04e0	/* FCS error */
100
101
102#define RAL_DISABLE_RX		(1 << 0)
103#define RAL_DROP_CRC		(1 << 1)
104#define RAL_DROP_PHY		(1 << 2)
105#define RAL_DROP_CTL		(1 << 3)
106#define RAL_DROP_NOT_TO_ME	(1 << 4)
107#define RAL_DROP_TODS		(1 << 5)
108#define RAL_DROP_BAD_VERSION	(1 << 6)
109#define RAL_DROP_MULTICAST	(1 << 9)
110#define RAL_DROP_BROADCAST	(1 << 10)
111
112#define RAL_SHORT_PREAMBLE	(1 << 2)
113
114#define RAL_RESET_ASIC	(1 << 0)
115#define RAL_RESET_BBP	(1 << 1)
116#define RAL_HOST_READY	(1 << 2)
117
118#define RAL_ENABLE_TSF			(1 << 0)
119#define RAL_ENABLE_TSF_SYNC(x)		(((x) & 0x3) << 1)
120#define RAL_ENABLE_TBCN			(1 << 3)
121#define RAL_ENABLE_BEACON_GENERATOR	(1 << 4)
122
123#define RAL_RF_AWAKE	(3 << 7)
124#define RAL_BBP_AWAKE	(3 << 5)
125
126#define RAL_BBP_WRITE	(1 << 15)
127#define RAL_BBP_BUSY	(1 << 0)
128
129#define RAL_RF1_AUTOTUNE	0x08000
130#define RAL_RF3_AUTOTUNE	0x00040
131
132#define RAL_RF_2522	0x00
133#define RAL_RF_2523	0x01
134#define RAL_RF_2524	0x02
135#define RAL_RF_2525	0x03
136#define RAL_RF_2525E	0x04
137#define RAL_RF_2526	0x05
138/* dual-band RF */
139#define RAL_RF_5222	0x10
140
141#define RAL_BBP_VERSION	0
142#define RAL_BBP_TX	2
143#define RAL_BBP_RX	14
144
145#define RAL_BBP_ANTA		0x00
146#define RAL_BBP_DIVERSITY	0x01
147#define RAL_BBP_ANTB		0x02
148#define RAL_BBP_ANTMASK		0x03
149#define RAL_BBP_FLIPIQ		0x04
150
151#define RAL_JAPAN_FILTER	0x08
152
153struct ural_tx_desc {
154	uint32_t	flags;
155#define RAL_TX_RETRY(x)		((x) << 4)
156#define RAL_TX_MORE_FRAG	(1 << 8)
157#define RAL_TX_ACK		(1 << 9)
158#define RAL_TX_TIMESTAMP	(1 << 10)
159#define RAL_TX_OFDM		(1 << 11)
160#define RAL_TX_NEWSEQ		(1 << 12)
161
162#define RAL_TX_IFS_MASK		0x00006000
163#define RAL_TX_IFS_BACKOFF	(0 << 13)
164#define RAL_TX_IFS_SIFS		(1 << 13)
165#define RAL_TX_IFS_NEWBACKOFF	(2 << 13)
166#define RAL_TX_IFS_NONE		(3 << 13)
167
168	uint16_t	wme;
169#define RAL_LOGCWMAX(x)		(((x) & 0xf) << 12)
170#define RAL_LOGCWMIN(x)		(((x) & 0xf) << 8)
171#define RAL_AIFSN(x)		(((x) & 0x3) << 6)
172#define RAL_IVOFFSET(x)		(((x) & 0x3f))
173
174	uint16_t	reserved1;
175	uint8_t		plcp_signal;
176	uint8_t		plcp_service;
177#define RAL_PLCP_LENGEXT	0x80
178
179	uint8_t		plcp_length_lo;
180	uint8_t		plcp_length_hi;
181	uint32_t	iv;
182	uint32_t	eiv;
183} __packed;
184
185struct ural_rx_desc {
186	uint32_t	flags;
187#define RAL_RX_CRC_ERROR	(1 << 5)
188#define RAL_RX_OFDM		(1 << 6)
189#define RAL_RX_PHY_ERROR	(1 << 7)
190
191	uint8_t		rssi;
192	uint8_t		rate;
193	uint16_t	reserved;
194
195	uint32_t	iv;
196	uint32_t	eiv;
197} __packed;
198
199#define RAL_RF_LOBUSY	(1 << 15)
200#define RAL_RF_BUSY	(1U << 31)
201#define RAL_RF_20BIT	(20 << 24)
202
203#define RAL_RF1	0
204#define RAL_RF2	2
205#define RAL_RF3	1
206#define RAL_RF4	3
207
208#define RAL_EEPROM_ADDRESS	0x0004
209#define RAL_EEPROM_TXPOWER	0x003c
210#define RAL_EEPROM_CONFIG0	0x0016
211#define RAL_EEPROM_BBP_BASE	0x001c
212