ixp425reg.h revision 261455
1/* $NetBSD: ixp425reg.h,v 1.19 2005/12/11 12:16:51 christos Exp $ */ 2/* 3 * Copyright (c) 2003 4 * Ichiro FUKUHARA <ichiro@ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD: stable/10/sys/arm/xscale/ixp425/ixp425reg.h 261455 2014-02-04 03:36:42Z eadler $ 35 * 36 */ 37 38#ifndef _IXP425REG_H_ 39#define _IXP425REG_H_ 40 41/* 42 * Physical memory map for the Intel IXP425 43 */ 44/* 45 * CC00 00FF --------------------------- 46 * SDRAM Configuration Registers 47 * CC00 0000 --------------------------- 48 * 49 * C800 BFFF --------------------------- 50 * System and Peripheral Registers 51 * C800 0000 --------------------------- 52 * Expansion Bus Configuration Registers 53 * C400 0000 --------------------------- 54 * PCI Configuration and Status Registers 55 * C000 0000 --------------------------- 56 * 57 * 6400 0000 --------------------------- 58 * Queue manager 59 * 6000 0000 --------------------------- 60 * Expansion Bus Data 61 * 5000 0000 --------------------------- 62 * PCI Data 63 * 4800 0000 --------------------------- 64 * 65 * 4000 0000 --------------------------- 66 * SDRAM 67 * 0000 0000 --------------------------- 68 */ 69 70/* 71 * Virtual memory map for the Intel IXP425/IXP435 integrated devices 72 */ 73/* 74 * FFFF FFFF --------------------------- 75 * 76 * Global cache clean area 77 * FF00 0000 --------------------------- 78 * 79 * FE00 0000 --------------------------- 80 * 16M CFI Flash (on ext bus) 81 * FD00 0000 --------------------------- 82 * 83 * FC00 0000 --------------------------- 84 * PCI Data (memory space) 85 * F800 0000 --------------------------- IXP425_PCI_MEM_VBASE 86 * 87 * F020 1000 --------------------------- 88 * SDRAM/DDR Memory Controller 89 * F020 0000 --------------------------- IXP425_MCU_VBASE 90 * 91 * F001 F000 RS485 (Cambria) CAMBRIA_RS485_VBASE 92 * F001 E000 GPS (Cambria) CAMBRIA_GPS_VBASE 93 * F001 D000 EHCI USB 2 (IXP435) IXP435_USB2_VBASE 94 * F001 C000 EHCI USB 1 (IXP435) IXP435_USB1_VBASE 95 * Queue manager 96 * F001 8000 --------------------------- IXP425_QMGR_VBASE 97 * PCI Configuration and Status 98 * F001 7000 --------------------------- IXP425_PCI_VBASE 99 * 100 * (NB: gap for future addition of EXP CS5-7) 101 * F001 4000 Expansion Bus Chip Select 4 102 * F001 3000 Expansion Bus Chip Select 3 103 * F001 2000 Expansion Bus Chip Select 2 104 * F001 1000 Expansion Bus Chip Select 1 105 * Expansion Bus Configuration 106 * F001 0000 --------------------------- IXP425_EXP_VBASE 107 * 108 * F000 C000 MAC-A (IXP435) 109 * F000 B000 USB (option on IXP425) 110 * F000 A000 MAC-B (IXP425) | MAC-C (IXP435) 111 * F000 9000 MAC-A (IXP425) 112 * F000 8000 NPE-C 113 * F000 7000 NPE-B (IXP425) 114 * F000 6000 NPE-A 115 * F000 5000 Timers 116 * F000 4000 GPIO Controller 117 * F000 3000 Interrupt Controller 118 * F000 2000 Performance Monitor Controller (PMC) 119 * F000 1000 UART 1 (IXP425) 120 * F000 0000 UART 0 121 * F000 0000 --------------------------- IXP425_IO_VBASE 122 * 123 * 0000 0000 --------------------------- 124 * 125 */ 126 127/* Physical/Virtual address for I/O space */ 128 129#define IXP425_IO_VBASE 0xf0000000UL 130#define IXP425_IO_HWBASE 0xc8000000UL 131#define IXP425_IO_SIZE 0x00010000UL 132 133/* Physical/Virtual addresss offsets */ 134#define IXP425_UART0_OFFSET 0x00000000UL 135#define IXP425_UART1_OFFSET 0x00001000UL 136#define IXP425_PMC_OFFSET 0x00002000UL 137#define IXP425_INTR_OFFSET 0x00003000UL 138#define IXP425_GPIO_OFFSET 0x00004000UL 139#define IXP425_TIMER_OFFSET 0x00005000UL 140#define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */ 141#define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */ 142#define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */ 143#define IXP425_MAC_B_OFFSET 0x00009000UL /* Ethernet MAC on NPE-B */ 144#define IXP425_MAC_C_OFFSET 0x0000a000UL /* Ethernet MAC on NPE-C */ 145#define IXP425_USB_OFFSET 0x0000b000UL 146 147#define IXP435_MAC_A_OFFSET 0x0000c000UL /* Ethernet MAC on NPE-A */ 148 149#define IXP425_REG_SIZE 0x1000 150 151/* 152 * UART 153 * UART0 0xc8000000 154 * UART1 0xc8001000 155 * 156 */ 157/* I/O space */ 158#define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) 159#define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) 160 161#define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) 162 /* 0xf0000000 */ 163#define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) 164 /* 0xf0001000 */ 165 166#define IXP425_UART_FREQ 14745600 167 168#define IXP425_UART_IER 0x01 /* interrupt enable register */ 169#define IXP425_UART_IER_RTOIE 0x10 /* receiver timeout interrupt enable */ 170#define IXP425_UART_IER_UUE 0x40 /* UART Unit enable */ 171 172/*#define IXP4XX_COM_NPORTS 8*/ 173 174/* 175 * Timers 176 */ 177#define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET) 178#define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET) 179 180#define IXP425_OST_TS 0x0000 181#define IXP425_OST_TIM0 0x0004 182#define IXP425_OST_TIM1 0x000C 183 184#define IXP425_OST_TIM0_RELOAD 0x0008 185#define IXP425_OST_TIM1_RELOAD 0x0010 186#define TIMERRELOAD_MASK 0xFFFFFFFC 187#define OST_ONESHOT_EN (1U << 1) 188#define OST_TIMER_EN (1U << 0) 189 190#define IXP425_OST_STATUS 0x0020 191#define OST_WARM_RESET (1U << 4) 192#define OST_WDOG_INT (1U << 3) 193#define OST_TS_INT (1U << 2) 194#define OST_TIM1_INT (1U << 1) 195#define OST_TIM0_INT (1U << 0) 196 197#define IXP425_OST_WDOG 0x0014 198#define IXP425_OST_WDOG_ENAB 0x0018 199#define IXP425_OST_WDOG_KEY 0x001c 200#define OST_WDOG_KEY_MAJICK 0x482e 201#define OST_WDOG_ENAB_RST_ENA (1u << 0) 202#define OST_WDOG_ENAB_INT_ENA (1u << 1) 203#define OST_WDOG_ENAB_CNT_ENA (1u << 2) 204 205/* 206 * Interrupt Controller Unit. 207 * PA 0xc8003000 208 */ 209 210#define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET 211#define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET 212 /* 0xf0003000 */ 213#define IXP425_IRQ_SIZE 0x00000020UL 214 215#define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) 216#define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) 217#define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) 218#define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) 219#define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) 220#define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) 221#define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) 222#define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) 223 224#define IXP425_INT_SW1 31 /* SW Interrupt 1 */ 225#define IXP425_INT_SW0 30 /* SW Interrupt 0 */ 226#define IXP425_INT_GPIO_12 29 /* GPIO 12 */ 227#define IXP425_INT_GPIO_11 28 /* GPIO 11 */ 228#define IXP425_INT_GPIO_10 27 /* GPIO 11 */ 229#define IXP425_INT_GPIO_9 26 /* GPIO 9 */ 230#define IXP425_INT_GPIO_8 25 /* GPIO 8 */ 231#define IXP425_INT_GPIO_7 24 /* GPIO 7 */ 232#define IXP425_INT_GPIO_6 23 /* GPIO 6 */ 233#define IXP425_INT_GPIO_5 22 /* GPIO 5 */ 234#define IXP425_INT_GPIO_4 21 /* GPIO 4 */ 235#define IXP425_INT_GPIO_3 20 /* GPIO 3 */ 236#define IXP425_INT_GPIO_2 19 /* GPIO 2 */ 237#define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */ 238#define IXP425_INT_AHB_PMU 17 /* AHB PMU */ 239#define IXP425_INT_WDOG 16 /* Watchdog Timer */ 240#define IXP425_INT_UART0 15 /* HighSpeed UART */ 241#define IXP425_INT_STAMP 14 /* Timestamp Timer */ 242#define IXP425_INT_UART1 13 /* Console UART */ 243#define IXP425_INT_USB 12 /* USB */ 244#define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ 245#define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ 246#define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ 247#define IXP425_INT_PCIINT 8 /* PCI Interrupt */ 248#define IXP425_INT_GPIO_1 7 /* GPIO 1 */ 249#define IXP425_INT_GPIO_0 6 /* GPIO 0 */ 250#define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ 251#define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ 252#define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ 253#define IXP425_INT_NPE_C 2 /* NPE C */ 254#define IXP425_INT_NPE_B 1 /* NPE B */ 255#define IXP425_INT_NPE_A 0 /* NPE A */ 256 257/* NB: IXP435 has an additional 32 IRQ's */ 258#define IXP435_INT_STATUS2 (IXP425_IRQ_VBASE + 0x20) 259#define IXP435_INT_ENABLE2 (IXP425_IRQ_VBASE + 0x24) 260#define IXP435_INT_SELECT2 (IXP425_IRQ_VBASE + 0x28) 261#define IXP435_IRQ_STATUS2 (IXP425_IRQ_VBASE + 0x2C) 262#define IXP435_FIQ_STATUS2 (IXP425_IRQ_VBASE + 0x30) 263 264#define IXP435_INT_USB0 32 /* USB Host 2.0 Host 0 */ 265#define IXP435_INT_USB1 33 /* USB Host 2.0 Host 1 */ 266#define IXP435_INT_QMGR_PER 60 /* Queue manager parity error */ 267#define IXP435_INT_ECC 61 /* Single or multi-bit ECC error */ 268 269/* 270 * software interrupt 271 */ 272#define IXP425_INT_bit31 31 273#define IXP425_INT_bit30 30 274#define IXP425_INT_bit14 14 275#define IXP425_INT_bit11 11 276 277#define IXP425_INT_HWMASK (0xffffffff & \ 278 ~((1 << IXP425_INT_bit31) | \ 279 (1 << IXP425_INT_bit30) | \ 280 (1 << IXP425_INT_bit14) | \ 281 (1 << IXP425_INT_bit11))) 282#define IXP425_INT_GPIOMASK (0x3ff800c0u) 283 284#define IXP435_INT_HWMASK ((1 << (IXP435_INT_USB0 - 32)) | \ 285 (1 << (IXP435_INT_USB1 - 32)) | \ 286 (1 << (IXP435_INT_QMGR_PER - 32)) | \ 287 (1 << (IXP435_INT_ECC - 32))) 288 289/* 290 * GPIO 291 */ 292#define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET 293#define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET 294 /* 0xf0004000 */ 295#define IXP425_GPIO_SIZE 0x00000020UL 296 297#define IXP425_GPIO_GPOUTR 0x00 298#define IXP425_GPIO_GPOER 0x04 299#define IXP425_GPIO_GPINR 0x08 300#define IXP425_GPIO_GPISR 0x0c 301#define IXP425_GPIO_GPIT1R 0x10 302#define IXP425_GPIO_GPIT2R 0x14 303#define IXP425_GPIO_GPCLKR 0x18 304# define GPCLKR_MUX14 (1U << 8) 305# define GPCLKR_CLK0TC_SHIFT 4 306# define GPCLKR_CLK0DC_SHIFT 0 307 308/* GPIO Output */ 309#define GPOUT_ON 0x1 310#define GPOUT_OFF 0x0 311 312/* GPIO direction */ 313#define GPOER_INPUT 0x1 314#define GPOER_OUTPUT 0x0 315 316/* GPIO Type bits */ 317#define GPIO_TYPE_ACT_HIGH 0x0 318#define GPIO_TYPE_ACT_LOW 0x1 319#define GPIO_TYPE_EDG_RISING 0x2 320#define GPIO_TYPE_EDG_FALLING 0x3 321#define GPIO_TYPE_TRANSITIONAL 0x4 322#define GPIO_TYPE_MASK 0x7 323#define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3)) 324#define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R) 325 326#define IXP4XX_GPIO_PINS 16 327 328/* 329 * Expansion Bus Configuration Space. 330 */ 331#define IXP425_EXP_HWBASE 0xc4000000UL 332#define IXP425_EXP_VBASE 0xf0010000UL 333#define IXP425_EXP_SIZE 0x1000 334 335/* offset */ 336#define EXP_TIMING_CS0_OFFSET 0x0000 337#define EXP_TIMING_CS1_OFFSET 0x0004 338#define EXP_TIMING_CS2_OFFSET 0x0008 339#define EXP_TIMING_CS3_OFFSET 0x000c 340#define EXP_TIMING_CS4_OFFSET 0x0010 341#define EXP_TIMING_CS5_OFFSET 0x0014 342#define EXP_TIMING_CS6_OFFSET 0x0018 343#define EXP_TIMING_CS7_OFFSET 0x001c 344#define EXP_CNFG0_OFFSET 0x0020 345#define EXP_CNFG1_OFFSET 0x0024 346#define EXP_FCTRL_OFFSET 0x0028 347 348#define IXP425_EXP_RECOVERY_SHIFT 16 349#define IXP425_EXP_HOLD_SHIFT 20 350#define IXP425_EXP_STROBE_SHIFT 22 351#define IXP425_EXP_SETUP_SHIFT 26 352#define IXP425_EXP_ADDR_SHIFT 28 353#define IXP425_EXP_CS_EN (1U << 31) 354 355#define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) 356#define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) 357#define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) 358#define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 359#define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) 360 361/* EXP_CSn bits */ 362#define EXP_BYTE_EN 0x00000001 /* bus uses only 8-bit data */ 363#define EXP_WR_EN 0x00000002 /* ena writes to CS region */ 364/* bit 2 is reserved */ 365#define EXP_SPLT_EN 0x00000008 /* ena AHB split transfers */ 366#define EXP_MUX_EN 0x00000010 /* multiplexed address/data */ 367#define EXP_HRDY_POL 0x00000020 /* HPI|HRDY polarity */ 368#define EXP_BYTE_RD16 0x00000040 /* byte rd access to word dev */ 369#define EXP_CNFG 0x00003c00 /* device config size */ 370#define EXP_SZ_512 (0 << 10) 371#define EXP_SZ_1K (1 << 10) 372#define EXP_SZ_2K (2 << 10) 373#define EXP_SZ_4K (3 << 10) 374#define EXP_SZ_8K (4 << 10) 375#define EXP_SZ_16K (5 << 10) 376#define EXP_SZ_32K (6 << 10) 377#define EXP_SZ_64K (7 << 10) 378#define EXP_SZ_128K (8 << 10) 379#define EXP_SZ_256K (9 << 10) 380#define EXP_SZ_512K (10 << 10) 381#define EXP_SZ_1M (11 << 10) 382#define EXP_SZ_2M (12 << 10) 383#define EXP_SZ_4M (13 << 10) 384#define EXP_SZ_8M (14 << 10) 385#define EXP_SZ_16M (15 << 10) 386#define EXP_CYC_TYPE 0x0000c000 /* bus cycle "type" */ 387#define EXP_CYC_INTEL (0 << 14) 388#define EXP_CYC_MOTO (1 << 14) 389#define EXP_CYC_HPI (2 << 14) 390#define EXP_T5 0x000f0000 /* recovery timing */ 391#define EXP_T4 0x00300000 /* hold timing */ 392#define EXP_T3 0x03c00000 /* strobe timing */ 393#define EXP_T2 0x0c000000 /* setup/chip select timing */ 394#define EXP_T1 0x30000000 /* address timing */ 395/* bit 30 is reserved */ 396#define EXP_CS_EN 0x80000000 /* chip select enabled */ 397 398/* EXP_CNFG0 bits */ 399#define EXP_CNFG0_8BIT (1 << 0) 400#define EXP_CNFG0_PCI_HOST (1 << 1) 401#define EXP_CNFG0_PCI_ARB (1 << 2) 402#define EXP_CNFG0_PCI_66MHZ (1 << 4) 403#define EXP_CNFG0_MEM_MAP (1U << 31) 404 405/* EXP_CNFG1 bits */ 406#define EXP_CNFG1_SW_INT0 (1 << 0) 407#define EXP_CNFG1_SW_INT1 (1 << 1) 408 409#define EXP_FCTRL_RCOMP (1<<0) 410#define EXP_FCTRL_USB_DEVICE (1<<1) 411#define EXP_FCTRL_HASH (1<<2) 412#define EXP_FCTRL_AES (1<<3) 413#define EXP_FCTRL_DES (1<<4) 414#define EXP_FCTRL_HDLC (1<<5) 415#define EXP_FCTRL_AAL (1<<6) 416#define EXP_FCTRL_HSS (1<<7) 417#define EXP_FCTRL_UTOPIA (1<<8) 418#define EXP_FCTRL_ETH0 (1<<9) 419#define EXP_FCTRL_ETH1 (1<<10) 420#define EXP_FCTRL_NPEA (1<<11) /* reset */ 421#define EXP_FCTRL_NPEB (1<<12) /* reset */ 422#define EXP_FCTRL_NPEC (1<<13) /* reset */ 423#define EXP_FCTRL_PCI (1<<14) 424#define EXP_FCTRL_ECC_TIMESYNC (1<<15) 425#define EXP_FCTRL_UTOPIA_PHY (3<<16) /* PHY limit */ 426#define EXP_FCTRL_USB_HOST (1<<18) 427#define EXP_FCTRL_NPEA_ETH (1<<19) 428#define EXP_FCTRL_NPEB_ETH (1<<20) 429#define EXP_FCTRL_RSA (1<<21) 430#define EXP_FCTRL_MAXFREQ (3<<22) /* XScale frequency */ 431#define EXP_FCTRL_RESVD (0xff<<24) 432 433#define EXP_FCTRL_IXP46X_ONLY \ 434 (EXP_FCTRL_ECC_TIMESYNC | EXP_FCTRL_USB_HOST | EXP_FCTRL_NPEA_ETH | \ 435 EXP_FCTRL_NPEB_ETH | EXP_FCTRL_RSA | EXP_FCTRL_MAXFREQ) 436 437#define EXP_FCTRL_BITS \ 438 "\20\1RCOMP\2USB\3HASH\4AES\5DES\6HDLC\7AAL\10HSS\11UTOPIA\12ETH0" \ 439 "\13ETH1\17PCI\20ECC\23USB_HOST\24NPEA_ETH\25NPEB_ETH\26RSA" 440 441/* 442 * PCI 443 */ 444#define IXP425_PCI_HWBASE 0xc0000000 445#define IXP425_PCI_VBASE 0xf0017000UL 446#define IXP425_PCI_SIZE 0x1000 447 448#define IXP425_AHB_OFFSET 0x00000000UL /* AHB bus */ 449 450/* 451 * Mapping registers of IXP425 PCI Configuration 452 */ 453/* PCI_ID_REG 0x00 */ 454/* PCI_COMMAND_STATUS_REG 0x04 */ 455/* PCI_CLASS_REG 0x08 */ 456/* PCI_BHLC_REG 0x0c */ 457#define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */ 458#define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */ 459#define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */ 460#define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */ 461#define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */ 462#define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */ 463/* PCI_SUBSYS_ID_REG 0x2c */ 464/* PCI_INTERRUPT_REG 0x3c */ 465#define PCI_RTOTTO 0x40 466 467/* PCI Controller CSR Base Address */ 468#define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE 469 470/* PCI Memory Space */ 471#define IXP425_PCI_MEM_HWBASE 0x48000000UL 472#define IXP425_PCI_MEM_VBASE 0xf8000000UL 473#define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */ 474 475/* PCI I/O Space */ 476#define IXP425_PCI_IO_HWBASE 0x00000000UL 477#define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 478 479/* PCI Controller Configuration Offset */ 480#define PCI_NP_AD 0x00 481#define PCI_NP_CBE 0x04 482# define NP_CBE_SHIFT 4 483#define PCI_NP_WDATA 0x08 484#define PCI_NP_RDATA 0x0c 485#define PCI_CRP_AD_CBE 0x10 486#define PCI_CRP_AD_WDATA 0x14 487#define PCI_CRP_AD_RDATA 0x18 488#define PCI_CSR 0x1c 489# define CSR_PRST (1U << 16) 490# define CSR_IC (1U << 15) 491# define CSR_ABE (1U << 4) 492# define CSR_PDS (1U << 3) 493# define CSR_ADS (1U << 2) 494# define CSR_HOST (1U << 0) 495#define PCI_ISR 0x20 496# define ISR_AHBE (1U << 3) 497# define ISR_PPE (1U << 2) 498# define ISR_PFE (1U << 1) 499# define ISR_PSE (1U << 0) 500#define PCI_INTEN 0x24 501#define PCI_DMACTRL 0x28 502#define PCI_AHBMEMBASE 0x2c 503#define PCI_AHBIOBASE 0x30 504#define PCI_PCIMEMBASE 0x34 505#define PCI_AHBDOORBELL 0x38 506#define PCI_PCIDOORBELL 0x3c 507#define PCI_ATPDMA0_AHBADDR 0x40 508#define PCI_ATPDMA0_PCIADDR 0x44 509#define PCI_ATPDMA0_LENGTH 0x48 510#define PCI_ATPDMA1_AHBADDR 0x4c 511#define PCI_ATPDMA1_PCIADDR 0x50 512#define PCI_ATPDMA1_LENGTH 0x54 513#define PCI_PTADMA0_AHBADDR 0x58 514#define PCI_PTADMA0_PCIADDR 0x5c 515#define PCI_PTADMA0_LENGTH 0x60 516#define PCI_PTADMA1_AHBADDR 0x64 517#define PCI_PTADMA1_PCIADDR 0x68 518#define PCI_PTADMA1_LENGTH 0x6c 519 520/* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */ 521#define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/ 522#define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/ 523#define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */ 524#define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */ 525#define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */ 526#define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */ 527#define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */ 528#define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */ 529 530/* PCI byte enables */ 531#define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0) 532#define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0) 533#define BE_32BIT(a) 0x00 534 535/* PCI byte selects */ 536#define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8))) 537#define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8))) 538#define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8)) 539#define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8)) 540 541/* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */ 542#define COMMAND_CRP_READ 0x00 543#define COMMAND_CRP_WRITE (1U << 16) 544 545/* 546 * SDRAM Configuration Register 547 */ 548#define IXP425_MCU_HWBASE 0xcc000000UL 549#define IXP425_MCU_VBASE 0xf0200000UL 550#define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */ 551#define MCU_SDR_CONFIG 0x00 552#define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7) 553#define MCU_SDR_CONFIG_64MBIT (1u << 5) 554#define MCU_SDR_REFRESH 0x04 555#define MCU_SDR_IR 0x08 556 557/* 558 * IXP435 DDR MCU Registers 559 */ 560#define IXP435_MCU_HWBASE 0xcc00e500UL 561#define MCU_DDR_SDIR 0x00 /* DDR SDAM Initialization Reg*/ 562#define MCU_DDR_SDCR0 0x04 /* DDR SDRAM Control Reg 0 */ 563#define MCU_DDR_SDCR1 0x08 /* DDR SDRAM Control Reg 1 */ 564#define MCU_DDR_SDBR 0x0c /* SDRAM Base Register */ 565#define MCU_DDR_SBR0 0x10 /* SDRAM Boundary Register 0 */ 566#define MCU_DDR_SBR1 0x14 /* SDRAM Boundary Register 1 */ 567#define MCU_DDR_ECCR 0x1c /* ECC Control Register */ 568#define MCU_DDR_ELOG0 0x20 /* ECC Log Register 0 */ 569#define MCU_DDR_ELOG1 0x24 /* ECC Log Register 1 */ 570#define MCU_DDR_ECAR0 0x28 /* ECC Address Register 0 */ 571#define MCU_DDR_ECAR1 0x2c /* ECC Address Register 1 */ 572#define MCU_DDR_ECTST 0x30 /* ECC Test Register */ 573#define MCU_DDR_MCISR 0x34 /* MC Interrupt Status Reg */ 574#define MCU_DDR_MPTCR 0x3c /* MC Port Transaction Cnt Reg*/ 575#define MCU_DDR_RFR 0x48 /* Refresh Frequency Register */ 576#define MCU_DDR_SDPR(n) (0x50+(n)*4) /* SDRAM Page Register 0-7 */ 577/* NB: RCVDLY at 0x1050 and LEGOVERIDE at 0x1074 */ 578 579/* 580 * Performance Monitoring Unit (CP14) 581 * 582 * CP14.0.1 Performance Monitor Control Register(PMNC) 583 * CP14.1.1 Clock Counter(CCNT) 584 * CP14.4.1 Interrupt Enable Register(INTEN) 585 * CP14.5.1 Overflow Flag Register(FLAG) 586 * CP14.8.1 Event Selection Register(EVTSEL) 587 * CP14.0.2 Performance Counter Register 0(PMN0) 588 * CP14.1.2 Performance Counter Register 0(PMN1) 589 * CP14.2.2 Performance Counter Register 0(PMN2) 590 * CP14.3.2 Performance Counter Register 0(PMN3) 591 */ 592 593#define PMNC_E 0x00000001 /* enable all counters */ 594#define PMNC_P 0x00000002 /* reset all PMNs to 0 */ 595#define PMNC_C 0x00000004 /* clock counter reset */ 596#define PMNC_D 0x00000008 /* clock counter / 64 */ 597 598#define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ 599#define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ 600#define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ 601#define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ 602#define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ 603 604#define FLAG_CC_IF 0x00000001 /* clock counter overflow */ 605#define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ 606#define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ 607#define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ 608#define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ 609 610#define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ 611#define PMNC_EVCNT0_SHIFT 0 612#define PMNC_EVCNT1_SHIFT 8 613#define PMNC_EVCNT2_SHIFT 16 614#define PMNC_EVCNT3_SHIFT 24 615 616/* 617 * Queue Manager 618 */ 619#define IXP425_QMGR_HWBASE 0x60000000UL 620#define IXP425_QMGR_VBASE 0xf0018000UL 621#define IXP425_QMGR_SIZE 0x4000 622 623/* 624 * Network Processing Engines (NPE's) and associated Ethernet MAC's. 625 */ 626#define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET) 627#define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET) 628#define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */ 629 630#define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET) 631#define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET) 632#define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */ 633 634#define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET) 635#define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET) 636#define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */ 637 638#define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET) 639#define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET) 640#define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */ 641 642#define IXP425_MAC_C_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_C_OFFSET) 643#define IXP425_MAC_C_VBASE (IXP425_IO_VBASE + IXP425_MAC_C_OFFSET) 644#define IXP425_MAC_C_SIZE 0x1000 /* Actually only 256 bytes */ 645 646#define IXP435_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP435_MAC_A_OFFSET) 647#define IXP435_MAC_A_VBASE (IXP425_IO_VBASE + IXP435_MAC_A_OFFSET) 648#define IXP435_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */ 649 650/* 651 * Expansion Bus Data Space. 652 */ 653#define IXP425_EXP_BUS_HWBASE 0x50000000UL 654#define IXP425_EXP_BUS_SIZE 0x01000000 /* max, typically smaller */ 655 656#define IXP425_EXP_BUS_CSx_HWBASE(i) \ 657 (IXP425_EXP_BUS_HWBASE + (i)*IXP425_EXP_BUS_SIZE) 658#define IXP425_EXP_BUS_CSx_SIZE 0x1000 659#define IXP425_EXP_BUS_CSx_VBASE(i) \ 660 (0xF0011000UL + (((i)-1)*IXP425_EXP_BUS_CSx_SIZE)) 661 662/* NB: CS0 is special; it maps flash */ 663#define IXP425_EXP_BUS_CS0_HWBASE IXP425_EXP_BUS_CSx_HWBASE(0) 664#define IXP425_EXP_BUS_CS0_VBASE 0xFD000000UL 665#ifndef IXP4XX_FLASH_SIZE 666#define IXP425_EXP_BUS_CS0_SIZE 0x01000000 /* NB: 16M */ 667#else 668#define IXP425_EXP_BUS_CS0_SIZE IXP4XX_FLASH_SIZE 669#endif 670#define IXP425_EXP_BUS_CS1_HWBASE IXP425_EXP_BUS_CSx_HWBASE(1) 671#define IXP425_EXP_BUS_CS1_VBASE IXP425_EXP_BUS_CSx_VBASE(1) 672#define IXP425_EXP_BUS_CS1_SIZE IXP425_EXP_BUS_CSx_SIZE 673#define IXP425_EXP_BUS_CS2_HWBASE IXP425_EXP_BUS_CSx_HWBASE(2) 674#define IXP425_EXP_BUS_CS2_VBASE IXP425_EXP_BUS_CSx_VBASE(2) 675#define IXP425_EXP_BUS_CS2_SIZE IXP425_EXP_BUS_CSx_SIZE 676#define IXP425_EXP_BUS_CS3_HWBASE IXP425_EXP_BUS_CSx_HWBASE(3) 677#define IXP425_EXP_BUS_CS3_VBASE IXP425_EXP_BUS_CSx_VBASE(3) 678#define IXP425_EXP_BUS_CS3_SIZE IXP425_EXP_BUS_CSx_SIZE 679#define IXP425_EXP_BUS_CS4_HWBASE IXP425_EXP_BUS_CSx_HWBASE(4) 680#define IXP425_EXP_BUS_CS4_VBASE IXP425_EXP_BUS_CSx_VBASE(4) 681#define IXP425_EXP_BUS_CS4_SIZE IXP425_EXP_BUS_CSx_SIZE 682 683/* NB: not mapped (yet) */ 684#define IXP425_EXP_BUS_CS5_HWBASE IXP425_EXP_BUS_CSx_HWBASE(5) 685#define IXP425_EXP_BUS_CS6_HWBASE IXP425_EXP_BUS_CSx_HWBASE(6) 686#define IXP425_EXP_BUS_CS7_HWBASE IXP425_EXP_BUS_CSx_HWBASE(7) 687 688/* 689 * IXP435/Gateworks Cambria 690 */ 691#define IXP435_USB1_HWBASE 0xCD000000UL /* USB host controller 1 */ 692#define IXP435_USB1_VBASE 0xF001C000UL 693#define IXP435_USB1_SIZE 0x1000 /* NB: only uses 0x300 */ 694 695#define IXP435_USB2_HWBASE 0xCE000000UL /* USB host controller 2 */ 696#define IXP435_USB2_VBASE 0xF001D000UL 697#define IXP435_USB2_SIZE 0x1000 /* NB: only uses 0x300 */ 698 699#define CAMBRIA_GPS_HWBASE 0x53FC0000UL /* optional GPS Serial Port */ 700#define CAMBRIA_GPS_VBASE 0xF001E000UL 701#define CAMBRIA_GPS_SIZE 0x1000 702#define CAMBRIA_RS485_HWBASE 0x53F80000UL /* optional RS485 Serial Port */ 703#define CAMBRIA_RS485_VBASE 0xF001F000UL 704#define CAMBRIA_RS485_SIZE 0x1000 705 706/* NB: these are mapped on the fly, so no fixed virtual addresses */ 707#define CAMBRIA_OCTAL_LED_HWBASE 0x53F40000UL /* Octal Status LED Latch */ 708#define CAMBRIA_OCTAL_LED_SIZE 0x1000 709#define CAMBRIA_CFSEL1_HWBASE 0x53E40000UL /* Compact Flash Socket Sel 0 */ 710#define CAMBRIA_CFSEL1_SIZE 0x40000 711#define CAMBRIA_CFSEL0_HWBASE 0x53E00000UL /* Compact Flash Socket Sel 1 */ 712#define CAMBRIA_CFSEL0_SIZE 0x40000 713 714#endif /* _IXP425REG_H_ */ 715