qp.c revision 261455
1/* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34#include <linux/log2.h> 35#include <linux/slab.h> 36#include <linux/netdevice.h> 37#include <linux/bitmap.h> 38#include <linux/bitops.h> 39 40#include <rdma/ib_cache.h> 41#include <rdma/ib_pack.h> 42#include <rdma/ib_addr.h> 43#include <rdma/ib_mad.h> 44 45#include <linux/mlx4/qp.h> 46#include <linux/mlx4/driver.h> 47#include <linux/io.h> 48 49#ifndef __linux__ 50#define asm __asm 51#endif 52 53#include "mlx4_ib.h" 54#include "user.h" 55 56enum { 57 MLX4_IB_ACK_REQ_FREQ = 8, 58}; 59 60enum { 61 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 62 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 63 MLX4_IB_LINK_TYPE_IB = 0, 64 MLX4_IB_LINK_TYPE_ETH = 1 65}; 66 67enum { 68 /* 69 * Largest possible UD header: send with GRH and immediate 70 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 71 * tag. (LRH would only use 8 bytes, so Ethernet is the 72 * biggest case) 73 */ 74 MLX4_IB_UD_HEADER_SIZE = 82, 75 MLX4_IB_LSO_HEADER_SPARE = 128, 76}; 77 78enum { 79 MLX4_IB_IBOE_ETHERTYPE = 0x8915 80}; 81 82struct mlx4_ib_sqp { 83 struct mlx4_ib_qp qp; 84 int pkey_index; 85 u32 qkey; 86 u32 send_psn; 87 struct ib_ud_header ud_header; 88 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 89}; 90 91enum { 92 MLX4_IB_MIN_SQ_STRIDE = 6, 93 MLX4_IB_CACHE_LINE_SIZE = 64, 94}; 95 96enum { 97 MLX4_RAW_QP_MTU = 7, 98 MLX4_RAW_QP_MSGMAX = 31, 99}; 100 101static const __be32 mlx4_ib_opcode[] = { 102 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 103 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 104 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 105 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 106 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 107 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 108 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 109 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 110 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 111 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 112 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 113 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 114 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 115}; 116 117#ifndef wc_wmb 118 #if defined(__i386__) 119 #define wc_wmb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory") 120 #elif defined(__x86_64__) 121 #define wc_wmb() asm volatile("sfence" ::: "memory") 122 #elif defined(__ia64__) 123 #define wc_wmb() asm volatile("fwb" ::: "memory") 124 #else 125 #define wc_wmb() wmb() 126 #endif 127#endif 128 129static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 130{ 131 return container_of(mqp, struct mlx4_ib_sqp, qp); 132} 133 134static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 135{ 136 if (!mlx4_is_master(dev->dev)) 137 return 0; 138 139 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 140 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 141 8 * MLX4_MFUNC_MAX; 142} 143 144static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 145{ 146 int proxy_sqp = 0; 147 int real_sqp = 0; 148 int i; 149 /* PPF or Native -- real SQP */ 150 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 151 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 152 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 153 if (real_sqp) 154 return 1; 155 /* VF or PF -- proxy SQP */ 156 if (mlx4_is_mfunc(dev->dev)) { 157 for (i = 0; i < dev->dev->caps.num_ports; i++) { 158 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] || 159 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) { 160 proxy_sqp = 1; 161 break; 162 } 163 } 164 } 165 return proxy_sqp; 166} 167 168/* used for INIT/CLOSE port logic */ 169static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 170{ 171 int proxy_qp0 = 0; 172 int real_qp0 = 0; 173 int i; 174 /* PPF or Native -- real QP0 */ 175 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 176 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 177 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 178 if (real_qp0) 179 return 1; 180 /* VF or PF -- proxy QP0 */ 181 if (mlx4_is_mfunc(dev->dev)) { 182 for (i = 0; i < dev->dev->caps.num_ports; i++) { 183 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) { 184 proxy_qp0 = 1; 185 break; 186 } 187 } 188 } 189 return proxy_qp0; 190} 191 192static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 193{ 194 return mlx4_buf_offset(&qp->buf, offset); 195} 196 197static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 198{ 199 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 200} 201 202static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 203{ 204 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 205} 206 207/* 208 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 209 * first four bytes of every 64 byte chunk with 210 * 0x7FFFFFF | (invalid_ownership_value << 31). 211 * 212 * When the max work request size is less than or equal to the WQE 213 * basic block size, as an optimization, we can stamp all WQEs with 214 * 0xffffffff, and skip the very first chunk of each WQE. 215 */ 216static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 217{ 218 __be32 *wqe; 219 int i; 220 int s; 221 int ind; 222 void *buf; 223 __be32 stamp; 224 struct mlx4_wqe_ctrl_seg *ctrl; 225 226 if (qp->sq_max_wqes_per_wr > 1) { 227 s = roundup(size, 1U << qp->sq.wqe_shift); 228 for (i = 0; i < s; i += 64) { 229 ind = (i >> qp->sq.wqe_shift) + n; 230 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 231 cpu_to_be32(0xffffffff); 232 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 233 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 234 *wqe = stamp; 235 } 236 } else { 237 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 238 s = (ctrl->fence_size & 0x3f) << 4; 239 for (i = 64; i < s; i += 64) { 240 wqe = buf + i; 241 *wqe = cpu_to_be32(0xffffffff); 242 } 243 } 244} 245 246static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 247{ 248 struct mlx4_wqe_ctrl_seg *ctrl; 249 struct mlx4_wqe_inline_seg *inl; 250 void *wqe; 251 int s; 252 253 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 254 s = sizeof(struct mlx4_wqe_ctrl_seg); 255 256 if (qp->ibqp.qp_type == IB_QPT_UD) { 257 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 258 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 259 memset(dgram, 0, sizeof *dgram); 260 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 261 s += sizeof(struct mlx4_wqe_datagram_seg); 262 } 263 264 /* Pad the remainder of the WQE with an inline data segment. */ 265 if (size > s) { 266 inl = wqe + s; 267 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); 268 } 269 ctrl->srcrb_flags = 0; 270 ctrl->fence_size = size / 16; 271 /* 272 * Make sure descriptor is fully written before setting ownership bit 273 * (because HW can start executing as soon as we do). 274 */ 275 wmb(); 276 277 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 278 (n & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0); 279 280 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 281} 282 283/* Post NOP WQE to prevent wrap-around in the middle of WR */ 284static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 285{ 286 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 287 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 288 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 289 ind += s; 290 } 291 return ind; 292} 293 294static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 295{ 296 struct ib_event event; 297 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 298 299 if (type == MLX4_EVENT_TYPE_PATH_MIG) 300 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 301 302 if (ibqp->event_handler) { 303 event.device = ibqp->device; 304 event.element.qp = ibqp; 305 switch (type) { 306 case MLX4_EVENT_TYPE_PATH_MIG: 307 event.event = IB_EVENT_PATH_MIG; 308 break; 309 case MLX4_EVENT_TYPE_COMM_EST: 310 event.event = IB_EVENT_COMM_EST; 311 break; 312 case MLX4_EVENT_TYPE_SQ_DRAINED: 313 event.event = IB_EVENT_SQ_DRAINED; 314 break; 315 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 316 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 317 break; 318 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 319 event.event = IB_EVENT_QP_FATAL; 320 break; 321 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 322 event.event = IB_EVENT_PATH_MIG_ERR; 323 break; 324 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 325 event.event = IB_EVENT_QP_REQ_ERR; 326 break; 327 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 328 event.event = IB_EVENT_QP_ACCESS_ERR; 329 break; 330 default: 331 pr_warn("Unexpected event type %d " 332 "on QP %06x\n", type, qp->qpn); 333 return; 334 } 335 336 ibqp->event_handler(&event, ibqp->qp_context); 337 } 338} 339 340static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 341{ 342 /* 343 * UD WQEs must have a datagram segment. 344 * RC and UC WQEs might have a remote address segment. 345 * MLX WQEs need two extra inline data segments (for the UD 346 * header and space for the ICRC). 347 */ 348 switch (type) { 349 case MLX4_IB_QPT_UD: 350 return sizeof (struct mlx4_wqe_ctrl_seg) + 351 sizeof (struct mlx4_wqe_datagram_seg) + 352 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 353 case MLX4_IB_QPT_PROXY_SMI_OWNER: 354 case MLX4_IB_QPT_PROXY_SMI: 355 case MLX4_IB_QPT_PROXY_GSI: 356 return sizeof (struct mlx4_wqe_ctrl_seg) + 357 sizeof (struct mlx4_wqe_datagram_seg) + 64; 358 case MLX4_IB_QPT_TUN_SMI_OWNER: 359 case MLX4_IB_QPT_TUN_GSI: 360 return sizeof (struct mlx4_wqe_ctrl_seg) + 361 sizeof (struct mlx4_wqe_datagram_seg); 362 363 case MLX4_IB_QPT_UC: 364 return sizeof (struct mlx4_wqe_ctrl_seg) + 365 sizeof (struct mlx4_wqe_raddr_seg); 366 case MLX4_IB_QPT_RC: 367 return sizeof (struct mlx4_wqe_ctrl_seg) + 368 sizeof (struct mlx4_wqe_masked_atomic_seg) + 369 sizeof (struct mlx4_wqe_raddr_seg); 370 case MLX4_IB_QPT_SMI: 371 case MLX4_IB_QPT_GSI: 372 return sizeof (struct mlx4_wqe_ctrl_seg) + 373 ALIGN(MLX4_IB_UD_HEADER_SIZE + 374 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 375 MLX4_INLINE_ALIGN) * 376 sizeof (struct mlx4_wqe_inline_seg), 377 sizeof (struct mlx4_wqe_data_seg)) + 378 ALIGN(4 + 379 sizeof (struct mlx4_wqe_inline_seg), 380 sizeof (struct mlx4_wqe_data_seg)); 381 default: 382 return sizeof (struct mlx4_wqe_ctrl_seg); 383 } 384} 385 386static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 387 int is_user, int has_rq, struct mlx4_ib_qp *qp) 388{ 389 /* Sanity check RQ size before proceeding */ 390 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 391 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 392 return -EINVAL; 393 394 if (!has_rq) { 395 if (cap->max_recv_wr) 396 return -EINVAL; 397 398 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 399 } else { 400 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 401 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) 402 return -EINVAL; 403 404 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 405 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 406 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg)); 407 } 408 409 /* leave userspace return values as they were, so as not to break ABI */ 410 if (is_user) { 411 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 412 cap->max_recv_sge = qp->rq.max_gs; 413 } else { 414 cap->max_recv_wr = qp->rq.max_post = 415 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 416 cap->max_recv_sge = min(qp->rq.max_gs, 417 min(dev->dev->caps.max_sq_sg, 418 dev->dev->caps.max_rq_sg)); 419 } 420 421 return 0; 422} 423 424static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 425 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 426{ 427 int s; 428 429 /* Sanity check SQ size before proceeding */ 430 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 431 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 432 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 433 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 434 return -EINVAL; 435 436 /* 437 * For MLX transport we need 2 extra S/G entries: 438 * one for the header and one for the checksum at the end 439 */ 440 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 441 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 442 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 443 return -EINVAL; 444 445 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 446 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 447 send_wqe_overhead(type, qp->flags); 448 449 if (s > dev->dev->caps.max_sq_desc_sz) 450 return -EINVAL; 451 452 /* 453 * Hermon supports shrinking WQEs, such that a single work 454 * request can include multiple units of 1 << wqe_shift. This 455 * way, work requests can differ in size, and do not have to 456 * be a power of 2 in size, saving memory and speeding up send 457 * WR posting. Unfortunately, if we do this then the 458 * wqe_index field in CQEs can't be used to look up the WR ID 459 * anymore, so we do this only if selective signaling is off. 460 * 461 * Further, on 32-bit platforms, we can't use vmap() to make 462 * the QP buffer virtually contiguous. Thus we have to use 463 * constant-sized WRs to make sure a WR is always fully within 464 * a single page-sized chunk. 465 * 466 * Finally, we use NOP work requests to pad the end of the 467 * work queue, to avoid wrap-around in the middle of WR. We 468 * set NEC bit to avoid getting completions with error for 469 * these NOP WRs, but since NEC is only supported starting 470 * with firmware 2.2.232, we use constant-sized WRs for older 471 * firmware. 472 * 473 * And, since MLX QPs only support SEND, we use constant-sized 474 * WRs in this case. 475 * 476 * We look for the smallest value of wqe_shift such that the 477 * resulting number of wqes does not exceed device 478 * capabilities. 479 * 480 * We set WQE size to at least 64 bytes, this way stamping 481 * invalidates each WQE. 482 */ 483 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 484 qp->sq_signal_bits && BITS_PER_LONG == 64 && 485 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI && 486 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI | 487 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) 488 qp->sq.wqe_shift = ilog2(64); 489 else 490 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 491 492 for (;;) { 493 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 494 495 /* 496 * We need to leave 2 KB + 1 WR of headroom in the SQ to 497 * allow HW to prefetch. 498 */ 499 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 500 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 501 qp->sq_max_wqes_per_wr + 502 qp->sq_spare_wqes); 503 504 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 505 break; 506 507 if (qp->sq_max_wqes_per_wr <= 1) 508 return -EINVAL; 509 510 ++qp->sq.wqe_shift; 511 } 512 513 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 514 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 515 send_wqe_overhead(type, qp->flags)) / 516 sizeof (struct mlx4_wqe_data_seg); 517 518 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 519 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 520 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 521 qp->rq.offset = 0; 522 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 523 } else { 524 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 525 qp->sq.offset = 0; 526 } 527 528 cap->max_send_wr = qp->sq.max_post = 529 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 530 cap->max_send_sge = min(qp->sq.max_gs, 531 min(dev->dev->caps.max_sq_sg, 532 dev->dev->caps.max_rq_sg)); 533 qp->max_inline_data = cap->max_inline_data; 534 535 return 0; 536} 537 538static int set_user_sq_size(struct mlx4_ib_dev *dev, 539 struct mlx4_ib_qp *qp, 540 struct mlx4_ib_create_qp *ucmd) 541{ 542 /* Sanity check SQ size before proceeding */ 543 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 544 ucmd->log_sq_stride > 545 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 546 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 547 return -EINVAL; 548 549 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 550 qp->sq.wqe_shift = ucmd->log_sq_stride; 551 552 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 553 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 554 555 return 0; 556} 557 558static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 559{ 560 int i; 561 562 qp->sqp_proxy_rcv = 563 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt, 564 GFP_KERNEL); 565 if (!qp->sqp_proxy_rcv) 566 return -ENOMEM; 567 for (i = 0; i < qp->rq.wqe_cnt; i++) { 568 qp->sqp_proxy_rcv[i].addr = 569 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 570 GFP_KERNEL); 571 if (!qp->sqp_proxy_rcv[i].addr) 572 goto err; 573 qp->sqp_proxy_rcv[i].map = 574 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 575 sizeof (struct mlx4_ib_proxy_sqp_hdr), 576 DMA_FROM_DEVICE); 577 } 578 return 0; 579 580err: 581 while (i > 0) { 582 --i; 583 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 584 sizeof (struct mlx4_ib_proxy_sqp_hdr), 585 DMA_FROM_DEVICE); 586 kfree(qp->sqp_proxy_rcv[i].addr); 587 } 588 kfree(qp->sqp_proxy_rcv); 589 qp->sqp_proxy_rcv = NULL; 590 return -ENOMEM; 591} 592 593static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 594{ 595 int i; 596 597 for (i = 0; i < qp->rq.wqe_cnt; i++) { 598 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 599 sizeof (struct mlx4_ib_proxy_sqp_hdr), 600 DMA_FROM_DEVICE); 601 kfree(qp->sqp_proxy_rcv[i].addr); 602 } 603 kfree(qp->sqp_proxy_rcv); 604} 605 606static int qp_has_rq(struct ib_qp_init_attr *attr) 607{ 608 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 609 return 0; 610 611 return !attr->srq; 612} 613 614#ifdef __linux__ 615static int init_qpg_parent(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *pqp, 616 struct ib_qp_init_attr *attr, int *qpn) 617{ 618 struct mlx4_ib_qpg_data *qpg_data; 619 int tss_num, rss_num; 620 int tss_align_num, rss_align_num; 621 int tss_base, rss_base = 0; 622 int err; 623 624 /* Parent is part of the TSS range (in SW TSS ARP is sent via parent) */ 625 tss_num = 1 + attr->parent_attrib.tss_child_count; 626 tss_align_num = roundup_pow_of_two(tss_num); 627 rss_num = attr->parent_attrib.rss_child_count; 628 rss_align_num = roundup_pow_of_two(rss_num); 629 630 if (rss_num > 1) { 631 /* RSS is requested */ 632 if (!(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS)) 633 return -ENOSYS; 634 if (rss_align_num > dev->dev->caps.max_rss_tbl_sz) 635 return -EINVAL; 636 /* We must work with power of two */ 637 attr->parent_attrib.rss_child_count = rss_align_num; 638 } 639 640 qpg_data = kzalloc(sizeof *qpg_data, GFP_KERNEL); 641 if (!qpg_data) 642 return -ENOMEM; 643 644 if(pqp->flags & MLX4_IB_QP_NETIF) 645 err = mlx4_ib_steer_qp_alloc(dev, tss_align_num, &tss_base); 646 else 647 err = mlx4_qp_reserve_range(dev->dev, tss_align_num, 648 tss_align_num, &tss_base, 1); 649 if (err) 650 goto err1; 651 652 if (tss_num > 1) { 653 u32 alloc = BITS_TO_LONGS(tss_align_num) * sizeof(long); 654 qpg_data->tss_bitmap = kzalloc(alloc, GFP_KERNEL); 655 if (qpg_data->tss_bitmap == NULL) { 656 err = -ENOMEM; 657 goto err2; 658 } 659 bitmap_fill(qpg_data->tss_bitmap, tss_num); 660 /* Note parent takes first index */ 661 clear_bit(0, qpg_data->tss_bitmap); 662 } 663 664 if (rss_num > 1) { 665 u32 alloc = BITS_TO_LONGS(rss_align_num) * sizeof(long); 666 err = mlx4_qp_reserve_range(dev->dev, rss_align_num, 667 1, &rss_base, 0); 668 if (err) 669 goto err3; 670 qpg_data->rss_bitmap = kzalloc(alloc, GFP_KERNEL); 671 if (qpg_data->rss_bitmap == NULL) { 672 err = -ENOMEM; 673 goto err4; 674 } 675 bitmap_fill(qpg_data->rss_bitmap, rss_align_num); 676 } 677 678 qpg_data->tss_child_count = attr->parent_attrib.tss_child_count; 679 qpg_data->rss_child_count = attr->parent_attrib.rss_child_count; 680 qpg_data->qpg_parent = pqp; 681 qpg_data->qpg_tss_mask_sz = ilog2(tss_align_num); 682 qpg_data->tss_qpn_base = tss_base; 683 qpg_data->rss_qpn_base = rss_base; 684 685 pqp->qpg_data = qpg_data; 686 *qpn = tss_base; 687 688 return 0; 689 690err4: 691 mlx4_qp_release_range(dev->dev, rss_base, rss_align_num); 692 693err3: 694 if (tss_num > 1) 695 kfree(qpg_data->tss_bitmap); 696 697err2: 698 if(pqp->flags & MLX4_IB_QP_NETIF) 699 mlx4_ib_steer_qp_free(dev, tss_base, tss_align_num); 700 else 701 mlx4_qp_release_range(dev->dev, tss_base, tss_align_num); 702 703err1: 704 kfree(qpg_data); 705 return err; 706} 707 708static void free_qpg_parent(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *pqp) 709{ 710 struct mlx4_ib_qpg_data *qpg_data = pqp->qpg_data; 711 int align_num; 712 713 if (qpg_data->tss_child_count > 1) 714 kfree(qpg_data->tss_bitmap); 715 716 align_num = roundup_pow_of_two(1 + qpg_data->tss_child_count); 717 if(pqp->flags & MLX4_IB_QP_NETIF) 718 mlx4_ib_steer_qp_free(dev, qpg_data->tss_qpn_base, align_num); 719 else 720 mlx4_qp_release_range(dev->dev, qpg_data->tss_qpn_base, align_num); 721 722 if (qpg_data->rss_child_count > 1) { 723 kfree(qpg_data->rss_bitmap); 724 align_num = roundup_pow_of_two(qpg_data->rss_child_count); 725 mlx4_qp_release_range(dev->dev, qpg_data->rss_qpn_base, 726 align_num); 727 } 728 729 kfree(qpg_data); 730} 731 732static int alloc_qpg_qpn(struct ib_qp_init_attr *init_attr, 733 struct mlx4_ib_qp *pqp, int *qpn) 734{ 735 struct mlx4_ib_qp *mqp = to_mqp(init_attr->qpg_parent); 736 struct mlx4_ib_qpg_data *qpg_data = mqp->qpg_data; 737 u32 idx, old; 738 739 switch (init_attr->qpg_type) { 740 case IB_QPG_CHILD_TX: 741 if (qpg_data->tss_child_count == 0) 742 return -EINVAL; 743 do { 744 /* Parent took index 0 */ 745 idx = find_first_bit(qpg_data->tss_bitmap, 746 qpg_data->tss_child_count + 1); 747 if (idx >= qpg_data->tss_child_count + 1) 748 return -ENOMEM; 749 old = test_and_clear_bit(idx, qpg_data->tss_bitmap); 750 } while (old == 0); 751 idx += qpg_data->tss_qpn_base; 752 break; 753 case IB_QPG_CHILD_RX: 754 if (qpg_data->rss_child_count == 0) 755 return -EINVAL; 756 do { 757 idx = find_first_bit(qpg_data->rss_bitmap, 758 qpg_data->rss_child_count); 759 if (idx >= qpg_data->rss_child_count) 760 return -ENOMEM; 761 old = test_and_clear_bit(idx, qpg_data->rss_bitmap); 762 } while (old == 0); 763 idx += qpg_data->rss_qpn_base; 764 break; 765 default: 766 return -EINVAL; 767 } 768 769 pqp->qpg_data = qpg_data; 770 *qpn = idx; 771 772 return 0; 773} 774 775static void free_qpg_qpn(struct mlx4_ib_qp *mqp, int qpn) 776{ 777 struct mlx4_ib_qpg_data *qpg_data = mqp->qpg_data; 778 779 switch (mqp->qpg_type) { 780 case IB_QPG_CHILD_TX: 781 /* Do range check */ 782 qpn -= qpg_data->tss_qpn_base; 783 set_bit(qpn, qpg_data->tss_bitmap); 784 break; 785 case IB_QPG_CHILD_RX: 786 qpn -= qpg_data->rss_qpn_base; 787 set_bit(qpn, qpg_data->rss_bitmap); 788 break; 789 default: 790 /* error */ 791 pr_warn("wrong qpg type (%d)\n", mqp->qpg_type); 792 break; 793 } 794} 795#endif 796 797static int alloc_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 798 struct ib_qp_init_attr *attr, int *qpn) 799{ 800 int err = 0; 801 802 switch (attr->qpg_type) { 803 case IB_QPG_NONE: 804 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE 805 * BlueFlame setup flow wrongly causes VLAN insertion. */ 806 if (attr->qp_type == IB_QPT_RAW_PACKET) { 807 err = mlx4_qp_reserve_range(dev->dev, 1, 1, qpn, 1); 808 } else { 809 if(qp->flags & MLX4_IB_QP_NETIF) 810 err = mlx4_ib_steer_qp_alloc(dev, 1, qpn); 811 else 812 err = mlx4_qp_reserve_range(dev->dev, 1, 1, qpn, 0); 813 } 814 break; 815 case IB_QPG_PARENT: 816#ifdef __linux__ 817 err = init_qpg_parent(dev, qp, attr, qpn); 818#endif 819 break; 820 case IB_QPG_CHILD_TX: 821 case IB_QPG_CHILD_RX: 822#ifdef __linux__ 823 err = alloc_qpg_qpn(attr, qp, qpn); 824#endif 825 break; 826 default: 827 qp->qpg_type = IB_QPG_NONE; 828 err = -EINVAL; 829 break; 830 } 831 if (err) 832 return err; 833 qp->qpg_type = attr->qpg_type; 834 return 0; 835} 836 837static void free_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 838 enum ib_qpg_type qpg_type, int qpn) 839{ 840 switch (qpg_type) { 841 case IB_QPG_NONE: 842 if (qp->flags & MLX4_IB_QP_NETIF) 843 mlx4_ib_steer_qp_free(dev, qpn, 1); 844 else 845 mlx4_qp_release_range(dev->dev, qpn, 1); 846 break; 847 case IB_QPG_PARENT: 848#ifdef __linux__ 849 free_qpg_parent(dev, qp); 850#endif 851 break; 852 case IB_QPG_CHILD_TX: 853 case IB_QPG_CHILD_RX: 854#ifdef __linux__ 855 free_qpg_qpn(qp, qpn); 856#endif 857 break; 858 default: 859 break; 860 } 861} 862 863/* Revert allocation on create_qp_common */ 864static void unalloc_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 865 struct ib_qp_init_attr *attr, int qpn) 866{ 867 free_qpn_common(dev, qp, attr->qpg_type, qpn); 868} 869 870static void release_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 871{ 872 free_qpn_common(dev, qp, qp->qpg_type, qp->mqp.qpn); 873} 874 875static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 876 struct ib_qp_init_attr *init_attr, 877 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp) 878{ 879 int qpn; 880 int err; 881 struct mlx4_ib_sqp *sqp; 882 struct mlx4_ib_qp *qp; 883 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 884 885#ifndef __linux__ 886 init_attr->qpg_type = IB_QPG_NONE; 887#endif 888 889 /* When tunneling special qps, we use a plain UD qp */ 890 if (sqpn) { 891 if (mlx4_is_mfunc(dev->dev) && 892 (!mlx4_is_master(dev->dev) || 893 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 894 if (init_attr->qp_type == IB_QPT_GSI) 895 qp_type = MLX4_IB_QPT_PROXY_GSI; 896 else if (mlx4_is_master(dev->dev)) 897 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 898 else 899 qp_type = MLX4_IB_QPT_PROXY_SMI; 900 } 901 qpn = sqpn; 902 /* add extra sg entry for tunneling */ 903 init_attr->cap.max_recv_sge++; 904 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 905 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 906 container_of(init_attr, 907 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 908 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 909 tnl_init->proxy_qp_type != IB_QPT_GSI) || 910 !mlx4_is_master(dev->dev)) 911 return -EINVAL; 912 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 913 qp_type = MLX4_IB_QPT_TUN_GSI; 914 else if (tnl_init->slave == mlx4_master_func_num(dev->dev)) 915 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 916 else 917 qp_type = MLX4_IB_QPT_TUN_SMI; 918 /* we are definitely in the PPF here, since we are creating 919 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 920 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 921 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 922 sqpn = qpn; 923 } 924 925 if (!*caller_qp) { 926 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 927 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 928 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 929 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL); 930 if (!sqp) 931 return -ENOMEM; 932 qp = &sqp->qp; 933 qp->pri.vid = qp->alt.vid = 0xFFFF; 934 } else { 935 qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL); 936 if (!qp) 937 return -ENOMEM; 938 qp->pri.vid = qp->alt.vid = 0xFFFF; 939 } 940 } else 941 qp = *caller_qp; 942 943 qp->mlx4_ib_qp_type = qp_type; 944 945 mutex_init(&qp->mutex); 946 spin_lock_init(&qp->sq.lock); 947 spin_lock_init(&qp->rq.lock); 948 INIT_LIST_HEAD(&qp->gid_list); 949 INIT_LIST_HEAD(&qp->steering_rules); 950 INIT_LIST_HEAD(&qp->rules_list); 951 952 qp->state = IB_QPS_RESET; 953 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 954 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 955 956 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp); 957 if (err) 958 goto err; 959 960 if (pd->uobject) { 961 struct mlx4_ib_create_qp ucmd; 962 int shift; 963 int n; 964 965 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 966 err = -EFAULT; 967 goto err; 968 } 969 970 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 971 972 err = set_user_sq_size(dev, qp, &ucmd); 973 if (err) 974 goto err; 975 976 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 977 qp->buf_size, 0, 0); 978 if (IS_ERR(qp->umem)) { 979 err = PTR_ERR(qp->umem); 980 goto err; 981 } 982 983 n = ib_umem_page_count(qp->umem); 984 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 985 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 986 987 if (err) 988 goto err_buf; 989 990 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 991 if (err) 992 goto err_mtt; 993 994 if (qp_has_rq(init_attr)) { 995 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 996 ucmd.db_addr, &qp->db); 997 if (err) 998 goto err_mtt; 999 } 1000 } else { 1001 qp->sq_no_prefetch = 0; 1002 1003 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1004 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1005 1006 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1007 qp->flags |= MLX4_IB_QP_LSO; 1008 1009 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP && 1010 dev->dev->caps.steering_mode == 1011 MLX4_STEERING_MODE_DEVICE_MANAGED && 1012 !mlx4_is_mfunc(dev->dev)) 1013 qp->flags |= MLX4_IB_QP_NETIF; 1014 1015 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1016 if (err) 1017 goto err; 1018 1019 if (qp_has_rq(init_attr)) { 1020 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1021 if (err) 1022 goto err; 1023 1024 *qp->db.db = 0; 1025 } 1026 1027 if (qp->max_inline_data) { 1028 err = mlx4_bf_alloc(dev->dev, &qp->bf, 0); 1029 if (err) { 1030 pr_debug("failed to allocate blue flame" 1031 " register (%d)", err); 1032 qp->bf.uar = &dev->priv_uar; 1033 } 1034 } else 1035 qp->bf.uar = &dev->priv_uar; 1036 1037 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) { 1038 err = -ENOMEM; 1039 goto err_db; 1040 } 1041 1042 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1043 &qp->mtt); 1044 if (err) 1045 goto err_buf; 1046 1047 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1048 if (err) 1049 goto err_mtt; 1050 1051 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL); 1052 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL); 1053 1054 if (!qp->sq.wrid || !qp->rq.wrid) { 1055 err = -ENOMEM; 1056 goto err_wrid; 1057 } 1058 } 1059 1060 if (sqpn) { 1061 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1062 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1063 if (alloc_proxy_bufs(pd->device, qp)) { 1064 err = -ENOMEM; 1065 goto err_wrid; 1066 } 1067 } 1068 } else { 1069 err = alloc_qpn_common(dev, qp, init_attr, &qpn); 1070 if (err) 1071 goto err_proxy; 1072 } 1073 1074 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1075 if (err) 1076 goto err_qpn; 1077 1078 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1079 qp->mqp.qpn |= (1 << 23); 1080 1081 /* 1082 * Hardware wants QPN written in big-endian order (after 1083 * shifting) for send doorbell. Precompute this value to save 1084 * a little bit when posting sends. 1085 */ 1086 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1087 1088 qp->mqp.event = mlx4_ib_qp_event; 1089 if (!*caller_qp) 1090 *caller_qp = qp; 1091 return 0; 1092 1093err_qpn: 1094 unalloc_qpn_common(dev, qp, init_attr, qpn); 1095 1096err_proxy: 1097 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1098 free_proxy_bufs(pd->device, qp); 1099err_wrid: 1100 if (pd->uobject) { 1101 if (qp_has_rq(init_attr)) 1102 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 1103 } else { 1104 kfree(qp->sq.wrid); 1105 kfree(qp->rq.wrid); 1106 } 1107 1108err_mtt: 1109 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1110 1111err_buf: 1112 if (pd->uobject) 1113 ib_umem_release(qp->umem); 1114 else 1115 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1116 1117err_db: 1118 if (!pd->uobject && qp_has_rq(init_attr)) 1119 mlx4_db_free(dev->dev, &qp->db); 1120 1121 if (qp->max_inline_data) 1122 mlx4_bf_free(dev->dev, &qp->bf); 1123 1124err: 1125 if (!*caller_qp) 1126 kfree(qp); 1127 return err; 1128} 1129 1130static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1131{ 1132 switch (state) { 1133 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1134 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1135 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1136 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1137 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1138 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1139 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1140 default: return -1; 1141 } 1142} 1143 1144static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1145 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1146{ 1147 if (send_cq == recv_cq) { 1148 spin_lock_irq(&send_cq->lock); 1149 __acquire(&recv_cq->lock); 1150 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1151 spin_lock_irq(&send_cq->lock); 1152 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1153 } else { 1154 spin_lock_irq(&recv_cq->lock); 1155 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1156 } 1157} 1158 1159static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1160 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1161{ 1162 if (send_cq == recv_cq) { 1163 __release(&recv_cq->lock); 1164 spin_unlock_irq(&send_cq->lock); 1165 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1166 spin_unlock(&recv_cq->lock); 1167 spin_unlock_irq(&send_cq->lock); 1168 } else { 1169 spin_unlock(&send_cq->lock); 1170 spin_unlock_irq(&recv_cq->lock); 1171 } 1172} 1173 1174static void del_gid_entries(struct mlx4_ib_qp *qp) 1175{ 1176 struct mlx4_ib_gid_entry *ge, *tmp; 1177 1178 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1179 list_del(&ge->list); 1180 kfree(ge); 1181 } 1182} 1183 1184static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1185{ 1186 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1187 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1188 else 1189 return to_mpd(qp->ibqp.pd); 1190} 1191 1192static void get_cqs(struct mlx4_ib_qp *qp, 1193 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1194{ 1195 switch (qp->ibqp.qp_type) { 1196 case IB_QPT_XRC_TGT: 1197 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1198 *recv_cq = *send_cq; 1199 break; 1200 case IB_QPT_XRC_INI: 1201 *send_cq = to_mcq(qp->ibqp.send_cq); 1202 *recv_cq = *send_cq; 1203 break; 1204 default: 1205 *send_cq = to_mcq(qp->ibqp.send_cq); 1206 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1207 break; 1208 } 1209} 1210 1211static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1212 int is_user) 1213{ 1214 struct mlx4_ib_cq *send_cq, *recv_cq; 1215 1216 if (qp->state != IB_QPS_RESET) { 1217 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1218 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1219 pr_warn("modify QP %06x to RESET failed.\n", 1220 qp->mqp.qpn); 1221 if (qp->pri.smac) { 1222 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1223 qp->pri.smac = 0; 1224 } 1225 if (qp->alt.smac) { 1226 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1227 qp->alt.smac = 0; 1228 } 1229 if (qp->pri.vid < 0x1000) { 1230 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1231 qp->pri.vid = 0xFFFF; 1232 qp->pri.candidate_vid = 0xFFFF; 1233 qp->pri.update_vid = 0; 1234 } 1235 if (qp->alt.vid < 0x1000) { 1236 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1237 qp->alt.vid = 0xFFFF; 1238 qp->alt.candidate_vid = 0xFFFF; 1239 qp->alt.update_vid = 0; 1240 } 1241 } 1242 1243 get_cqs(qp, &send_cq, &recv_cq); 1244 1245 mlx4_ib_lock_cqs(send_cq, recv_cq); 1246 1247 if (!is_user) { 1248 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1249 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1250 if (send_cq != recv_cq) 1251 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1252 } 1253 1254 mlx4_qp_remove(dev->dev, &qp->mqp); 1255 1256 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1257 1258 mlx4_qp_free(dev->dev, &qp->mqp); 1259 1260 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) 1261 release_qpn_common(dev, qp); 1262 1263 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1264 1265 if (is_user) { 1266 if (qp->rq.wqe_cnt) 1267 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context), 1268 &qp->db); 1269 ib_umem_release(qp->umem); 1270 } else { 1271 kfree(qp->sq.wrid); 1272 kfree(qp->rq.wrid); 1273 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1274 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1275 free_proxy_bufs(&dev->ib_dev, qp); 1276 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1277 if (qp->max_inline_data) 1278 mlx4_bf_free(dev->dev, &qp->bf); 1279 1280 if (qp->rq.wqe_cnt) 1281 mlx4_db_free(dev->dev, &qp->db); 1282 } 1283 1284 del_gid_entries(qp); 1285} 1286 1287static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1288{ 1289 /* Native or PPF */ 1290 if (!mlx4_is_mfunc(dev->dev) || 1291 (mlx4_is_master(dev->dev) && 1292 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1293 return dev->dev->phys_caps.base_sqpn + 1294 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1295 attr->port_num - 1; 1296 } 1297 /* PF or VF -- creating proxies */ 1298 if (attr->qp_type == IB_QPT_SMI) 1299 return dev->dev->caps.qp0_proxy[attr->port_num - 1]; 1300 else 1301 return dev->dev->caps.qp1_proxy[attr->port_num - 1]; 1302} 1303 1304#ifdef __linux__ 1305static int check_qpg_attr(struct mlx4_ib_dev *dev, 1306 struct ib_qp_init_attr *attr) 1307{ 1308 if (attr->qpg_type == IB_QPG_NONE) 1309 return 0; 1310 1311 if (attr->qp_type != IB_QPT_UD) 1312 return -EINVAL; 1313 1314 if (attr->qpg_type == IB_QPG_PARENT) { 1315 if (attr->parent_attrib.tss_child_count == 1) 1316 return -EINVAL; /* Doesn't make sense */ 1317 if (attr->parent_attrib.rss_child_count == 1) 1318 return -EINVAL; /* Doesn't make sense */ 1319 if ((attr->parent_attrib.tss_child_count == 0) && 1320 (attr->parent_attrib.rss_child_count == 0)) 1321 /* Should be called with IP_QPG_NONE */ 1322 return -EINVAL; 1323 if (attr->parent_attrib.rss_child_count > 1) { 1324 int rss_align_num; 1325 if (!(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS)) 1326 return -ENOSYS; 1327 rss_align_num = roundup_pow_of_two( 1328 attr->parent_attrib.rss_child_count); 1329 if (rss_align_num > dev->dev->caps.max_rss_tbl_sz) 1330 return -EINVAL; 1331 } 1332 } else { 1333 struct mlx4_ib_qpg_data *qpg_data; 1334 if (attr->qpg_parent == NULL) 1335 return -EINVAL; 1336 if (IS_ERR(attr->qpg_parent)) 1337 return -EINVAL; 1338 qpg_data = to_mqp(attr->qpg_parent)->qpg_data; 1339 if (qpg_data == NULL) 1340 return -EINVAL; 1341 if (attr->qpg_type == IB_QPG_CHILD_TX && 1342 !qpg_data->tss_child_count) 1343 return -EINVAL; 1344 if (attr->qpg_type == IB_QPG_CHILD_RX && 1345 !qpg_data->rss_child_count) 1346 return -EINVAL; 1347 } 1348 return 0; 1349} 1350#endif 1351 1352#define RESERVED_FLAGS_MASK ((((unsigned int)IB_QP_CREATE_RESERVED_END - 1) | IB_QP_CREATE_RESERVED_END) \ 1353 & ~(IB_QP_CREATE_RESERVED_START - 1)) 1354 1355static enum mlx4_ib_qp_flags to_mlx4_ib_qp_flags(enum ib_qp_create_flags ib_qp_flags) 1356{ 1357 enum mlx4_ib_qp_flags mlx4_ib_qp_flags = 0; 1358 1359 if (ib_qp_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1360 mlx4_ib_qp_flags |= MLX4_IB_QP_LSO; 1361 1362 if (ib_qp_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1363 mlx4_ib_qp_flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1364 1365 if (ib_qp_flags & IB_QP_CREATE_NETIF_QP) 1366 mlx4_ib_qp_flags |= MLX4_IB_QP_NETIF; 1367 1368 /* reserved flags */ 1369 mlx4_ib_qp_flags |= (ib_qp_flags & RESERVED_FLAGS_MASK); 1370 1371 return mlx4_ib_qp_flags; 1372} 1373 1374struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1375 struct ib_qp_init_attr *init_attr, 1376 struct ib_udata *udata) 1377{ 1378 struct mlx4_ib_qp *qp = NULL; 1379 int err; 1380 u16 xrcdn = 0; 1381 enum mlx4_ib_qp_flags mlx4_qp_flags = to_mlx4_ib_qp_flags(init_attr->create_flags); 1382 struct ib_device *device; 1383 1384 /* see ib_core::ib_create_qp same handling */ 1385 device = pd ? pd->device : init_attr->xrcd->device; 1386 /* 1387 * We only support LSO, vendor flag1, and multicast loopback blocking, 1388 * and only for kernel UD QPs. 1389 */ 1390 if (mlx4_qp_flags & ~(MLX4_IB_QP_LSO | 1391 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1392 MLX4_IB_SRIOV_TUNNEL_QP | MLX4_IB_SRIOV_SQP | 1393 MLX4_IB_QP_NETIF)) 1394 return ERR_PTR(-EINVAL); 1395 1396 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1397 if (init_attr->qp_type != IB_QPT_UD) 1398 return ERR_PTR(-EINVAL); 1399 } 1400 1401 if (init_attr->create_flags && 1402 (udata || 1403 ((mlx4_qp_flags & ~MLX4_IB_SRIOV_SQP) && 1404 init_attr->qp_type != IB_QPT_UD) || 1405 ((mlx4_qp_flags & MLX4_IB_SRIOV_SQP) && 1406 init_attr->qp_type > IB_QPT_GSI))) 1407 return ERR_PTR(-EINVAL); 1408 1409#ifdef __linux__ 1410 err = check_qpg_attr(to_mdev(device), init_attr); 1411 if (err) 1412 return ERR_PTR(err); 1413#endif 1414 1415 switch (init_attr->qp_type) { 1416 case IB_QPT_XRC_TGT: 1417 pd = to_mxrcd(init_attr->xrcd)->pd; 1418 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1419 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1420 /* fall through */ 1421 case IB_QPT_XRC_INI: 1422 if (!(to_mdev(device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1423 return ERR_PTR(-ENOSYS); 1424 init_attr->recv_cq = init_attr->send_cq; 1425 /* fall through */ 1426 case IB_QPT_RC: 1427 case IB_QPT_UC: 1428 case IB_QPT_RAW_PACKET: 1429 qp = kzalloc(sizeof *qp, GFP_KERNEL); 1430 if (!qp) 1431 return ERR_PTR(-ENOMEM); 1432 qp->pri.vid = qp->alt.vid = 0xFFFF; 1433 /* fall through */ 1434 case IB_QPT_UD: 1435 { 1436 err = create_qp_common(to_mdev(device), pd, init_attr, udata, 0, &qp); 1437 if (err) { 1438 kfree(qp); 1439 return ERR_PTR(err); 1440 } 1441 1442 qp->ibqp.qp_num = qp->mqp.qpn; 1443 qp->xrcdn = xrcdn; 1444 1445 break; 1446 } 1447 case IB_QPT_SMI: 1448 case IB_QPT_GSI: 1449 { 1450 /* Userspace is not allowed to create special QPs: */ 1451 if (udata) 1452 return ERR_PTR(-EINVAL); 1453 1454 err = create_qp_common(to_mdev(device), pd, init_attr, udata, 1455 get_sqp_num(to_mdev(device), init_attr), 1456 &qp); 1457 if (err) 1458 return ERR_PTR(err); 1459 1460 qp->port = init_attr->port_num; 1461 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1; 1462 1463 break; 1464 } 1465 default: 1466 /* Don't support raw QPs */ 1467 return ERR_PTR(-EINVAL); 1468 } 1469 1470 return &qp->ibqp; 1471} 1472 1473int mlx4_ib_destroy_qp(struct ib_qp *qp) 1474{ 1475 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1476 struct mlx4_ib_qp *mqp = to_mqp(qp); 1477 struct mlx4_ib_pd *pd; 1478 1479 if (is_qp0(dev, mqp)) 1480 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1481 1482 pd = get_pd(mqp); 1483 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject); 1484 1485 if (is_sqp(dev, mqp)) 1486 kfree(to_msqp(mqp)); 1487 else 1488 kfree(mqp); 1489 1490 return 0; 1491} 1492 1493static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1494{ 1495 switch (type) { 1496 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1497 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1498 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1499 case MLX4_IB_QPT_XRC_INI: 1500 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1501 case MLX4_IB_QPT_SMI: 1502 case MLX4_IB_QPT_GSI: 1503 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1504 1505 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1506 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1507 MLX4_QP_ST_MLX : -1); 1508 case MLX4_IB_QPT_PROXY_SMI: 1509 case MLX4_IB_QPT_TUN_SMI: 1510 case MLX4_IB_QPT_PROXY_GSI: 1511 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1512 MLX4_QP_ST_UD : -1); 1513 default: return -1; 1514 } 1515} 1516 1517static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1518 int attr_mask) 1519{ 1520 u8 dest_rd_atomic; 1521 u32 access_flags; 1522 u32 hw_access_flags = 0; 1523 1524 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1525 dest_rd_atomic = attr->max_dest_rd_atomic; 1526 else 1527 dest_rd_atomic = qp->resp_depth; 1528 1529 if (attr_mask & IB_QP_ACCESS_FLAGS) 1530 access_flags = attr->qp_access_flags; 1531 else 1532 access_flags = qp->atomic_rd_en; 1533 1534 if (!dest_rd_atomic) 1535 access_flags &= IB_ACCESS_REMOTE_WRITE; 1536 1537 if (access_flags & IB_ACCESS_REMOTE_READ) 1538 hw_access_flags |= MLX4_QP_BIT_RRE; 1539 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1540 hw_access_flags |= MLX4_QP_BIT_RAE; 1541 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1542 hw_access_flags |= MLX4_QP_BIT_RWE; 1543 1544 return cpu_to_be32(hw_access_flags); 1545} 1546 1547static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1548 int attr_mask) 1549{ 1550 if (attr_mask & IB_QP_PKEY_INDEX) 1551 sqp->pkey_index = attr->pkey_index; 1552 if (attr_mask & IB_QP_QKEY) 1553 sqp->qkey = attr->qkey; 1554 if (attr_mask & IB_QP_SQ_PSN) 1555 sqp->send_psn = attr->sq_psn; 1556} 1557 1558static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1559{ 1560 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1561} 1562 1563static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah, 1564 struct mlx4_ib_qp *qp, struct mlx4_qp_path *path, 1565 u8 port, int is_primary) 1566{ 1567 struct net_device *ndev; 1568 int err; 1569 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) == 1570 IB_LINK_LAYER_ETHERNET; 1571 u8 mac[6]; 1572 int is_mcast; 1573 u16 vlan_tag; 1574 int vidx; 1575 int smac_index; 1576 u64 u64_mac; 1577 u8 *smac; 1578 struct mlx4_roce_smac_vlan_info *smac_info; 1579 1580 path->grh_mylmc = ah->src_path_bits & 0x7f; 1581 path->rlid = cpu_to_be16(ah->dlid); 1582 if (ah->static_rate) { 1583 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET; 1584 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1585 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1586 --path->static_rate; 1587 } else 1588 path->static_rate = 0; 1589 1590 if (ah->ah_flags & IB_AH_GRH) { 1591 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) { 1592 pr_err("sgid_index (%u) too large. max is %d\n", 1593 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1594 return -1; 1595 } 1596 1597 path->grh_mylmc |= 1 << 7; 1598 path->mgid_index = ah->grh.sgid_index; 1599 path->hop_limit = ah->grh.hop_limit; 1600 path->tclass_flowlabel = 1601 cpu_to_be32((ah->grh.traffic_class << 20) | 1602 (ah->grh.flow_label)); 1603 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1604 } 1605 1606 if (is_eth) { 1607 if (!(ah->ah_flags & IB_AH_GRH)) 1608 return -1; 1609 1610 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1611 ((port - 1) << 6) | ((ah->sl & 7) << 3); 1612 1613 if (is_primary) 1614 smac_info = &qp->pri; 1615 else 1616 smac_info = &qp->alt; 1617 1618 vlan_tag = rdma_get_vlan_id(&dev->iboe.gid_table[port - 1][ah->grh.sgid_index]); 1619 if (vlan_tag < 0x1000) { 1620 if (smac_info->vid < 0x1000) { 1621 /* both valid vlan ids */ 1622 if (smac_info->vid != vlan_tag) { 1623 /* different VIDs. unreg old and reg new */ 1624 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1625 if (err) 1626 return err; 1627 smac_info->candidate_vid = vlan_tag; 1628 smac_info->candidate_vlan_index = vidx; 1629 smac_info->candidate_vlan_port = port; 1630 smac_info->update_vid = 1; 1631 path->vlan_index = vidx; 1632 path->fl = 1 << 6; 1633 } else { 1634 path->vlan_index = smac_info->vlan_index; 1635 path->fl = 1 << 6; 1636 } 1637 } else { 1638 /* no current vlan tag in qp */ 1639 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1640 if (err) 1641 return err; 1642 smac_info->candidate_vid = vlan_tag; 1643 smac_info->candidate_vlan_index = vidx; 1644 smac_info->candidate_vlan_port = port; 1645 smac_info->update_vid = 1; 1646 path->vlan_index = vidx; 1647 path->fl = 1 << 6; 1648 } 1649 } else { 1650 /* have current vlan tag. unregister it at modify-qp success */ 1651 if (smac_info->vid < 0x1000) { 1652 smac_info->candidate_vid = 0xFFFF; 1653 smac_info->update_vid = 1; 1654 } 1655 } 1656 1657 err = mlx4_ib_resolve_grh(dev, ah, mac, &is_mcast, port); 1658 if (err) 1659 return err; 1660 1661 /* get smac_index for RoCE use. 1662 * If no smac was yet assigned, register one. 1663 * If one was already assigned, but the new mac differs, 1664 * unregister the old one and register the new one. 1665 */ 1666 spin_lock(&dev->iboe.lock); 1667 ndev = dev->iboe.netdevs[port - 1]; 1668 if (ndev) { 1669#ifdef __linux__ 1670 smac = ndev->dev_addr; /* fixme: cache this value */ 1671#else 1672 smac = IF_LLADDR(ndev); /* fixme: cache this value */ 1673#endif 1674 1675 u64_mac = mlx4_mac_to_u64(smac); 1676 } else 1677 u64_mac = dev->dev->caps.def_mac[port]; 1678 spin_unlock(&dev->iboe.lock); 1679 1680 if (!smac_info->smac || smac_info->smac != u64_mac) { 1681 /* register candidate now, unreg if needed, after success */ 1682 smac_index = mlx4_register_mac(dev->dev, port, u64_mac); 1683 if (smac_index >= 0) { 1684 smac_info->candidate_smac_index = smac_index; 1685 smac_info->candidate_smac = u64_mac; 1686 smac_info->candidate_smac_port = port; 1687 } else 1688 return -EINVAL; 1689 } else 1690 smac_index = smac_info->smac_index; 1691 1692 memcpy(path->dmac, mac, 6); 1693 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1694 /* put MAC table smac index for IBoE */ 1695 path->grh_mylmc = (u8) (smac_index) | 0x80 ; 1696 1697 } else 1698 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1699 ((port - 1) << 6) | ((ah->sl & 0xf) << 2); 1700 1701 return 0; 1702} 1703 1704static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1705{ 1706 struct mlx4_ib_gid_entry *ge, *tmp; 1707 1708 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1709 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1710 ge->added = 1; 1711 ge->port = qp->port; 1712 } 1713 } 1714} 1715 1716static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1717 struct mlx4_qp_context *context) 1718{ 1719 struct net_device *ndev; 1720 u64 u64_mac; 1721 u8 *smac; 1722 int smac_index; 1723 1724 ndev = dev->iboe.netdevs[qp->port - 1]; 1725 if (ndev) { 1726#ifdef __linux__ 1727 smac = ndev->dev_addr; /* fixme: cache this value */ 1728#else 1729 smac = IF_LLADDR(ndev); /* fixme: cache this value */ 1730#endif 1731 u64_mac = mlx4_mac_to_u64(smac); 1732 } else 1733 u64_mac = dev->dev->caps.def_mac[qp->port]; 1734 1735 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1736 if (!qp->pri.smac) { 1737 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1738 if (smac_index >= 0) { 1739 qp->pri.candidate_smac_index = smac_index; 1740 qp->pri.candidate_smac = u64_mac; 1741 qp->pri.candidate_smac_port = qp->port; 1742 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1743 } else 1744 return -ENOENT; 1745 } 1746 return 0; 1747} 1748static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, 1749 const struct ib_qp_attr *attr, int attr_mask, 1750 enum ib_qp_state cur_state, enum ib_qp_state new_state) 1751{ 1752 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1753 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1754 struct mlx4_ib_pd *pd; 1755 struct mlx4_ib_cq *send_cq, *recv_cq; 1756 struct mlx4_qp_context *context; 1757 enum mlx4_qp_optpar optpar = 0; 1758 int sqd_event; 1759 int steer_qp = 0; 1760 int err = -EINVAL; 1761 int is_eth = -1; 1762 1763 context = kzalloc(sizeof *context, GFP_KERNEL); 1764 if (!context) 1765 return -ENOMEM; 1766 1767 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 1768 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 1769 1770 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 1771 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1772 else { 1773 optpar |= MLX4_QP_OPTPAR_PM_STATE; 1774 switch (attr->path_mig_state) { 1775 case IB_MIG_MIGRATED: 1776 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1777 break; 1778 case IB_MIG_REARM: 1779 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 1780 break; 1781 case IB_MIG_ARMED: 1782 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 1783 break; 1784 } 1785 } 1786 1787 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) 1788 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 1789 else if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1790 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 1791 else if (ibqp->qp_type == IB_QPT_UD) { 1792 if (qp->flags & MLX4_IB_QP_LSO) 1793 context->mtu_msgmax = (IB_MTU_4096 << 5) | 1794 ilog2(dev->dev->caps.max_gso_sz); 1795 else 1796 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1797 } else if (attr_mask & IB_QP_PATH_MTU) { 1798 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 1799 pr_err("path MTU (%u) is invalid\n", 1800 attr->path_mtu); 1801 goto out; 1802 } 1803 context->mtu_msgmax = (attr->path_mtu << 5) | 1804 ilog2(dev->dev->caps.max_msg_sz); 1805 } 1806 1807 if (qp->rq.wqe_cnt) 1808 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 1809 context->rq_size_stride |= qp->rq.wqe_shift - 4; 1810 1811 if (qp->sq.wqe_cnt) 1812 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 1813 context->sq_size_stride |= qp->sq.wqe_shift - 4; 1814 1815 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1816 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 1817 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 1818 context->param3 |= cpu_to_be32(1 << 30); 1819 } 1820 1821 if (qp->ibqp.uobject) 1822 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index); 1823 else 1824 context->usr_page = cpu_to_be32(qp->bf.uar->index); 1825 1826 if (attr_mask & IB_QP_DEST_QPN) 1827 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 1828 1829 if (attr_mask & IB_QP_PORT) { 1830 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 1831 !(attr_mask & IB_QP_AV)) { 1832 mlx4_set_sched(&context->pri_path, attr->port_num); 1833 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 1834 } 1835 } 1836 1837 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 1838 if (dev->counters[qp->port - 1] != -1) { 1839 context->pri_path.counter_index = 1840 dev->counters[qp->port - 1]; 1841 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 1842 } else 1843 context->pri_path.counter_index = 0xff; 1844 1845 if (qp->flags & MLX4_IB_QP_NETIF && 1846 (qp->qpg_type == IB_QPG_NONE || qp->qpg_type == IB_QPG_PARENT)) { 1847 mlx4_ib_steer_qp_reg(dev, qp, 1); 1848 steer_qp = 1; 1849 } 1850 } 1851 1852 if (attr_mask & IB_QP_PKEY_INDEX) { 1853 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1854 context->pri_path.disable_pkey_check = 0x40; 1855 context->pri_path.pkey_index = attr->pkey_index; 1856 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 1857 } 1858 1859 if (attr_mask & IB_QP_AV) { 1860 if (mlx4_set_path(dev, &attr->ah_attr, qp, &context->pri_path, 1861 attr_mask & IB_QP_PORT ? 1862 attr->port_num : qp->port, 1)) 1863 goto out; 1864 1865 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 1866 MLX4_QP_OPTPAR_SCHED_QUEUE); 1867 } 1868 1869 if (attr_mask & IB_QP_TIMEOUT) { 1870 context->pri_path.ackto |= attr->timeout << 3; 1871 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 1872 } 1873 1874 if (attr_mask & IB_QP_ALT_PATH) { 1875 if (attr->alt_port_num == 0 || 1876 attr->alt_port_num > dev->dev->caps.num_ports) 1877 goto out; 1878 1879 if (attr->alt_pkey_index >= 1880 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 1881 goto out; 1882 1883 if (mlx4_set_path(dev, &attr->alt_ah_attr, qp, &context->alt_path, 1884 attr->alt_port_num, 0)) 1885 goto out; 1886 1887 context->alt_path.pkey_index = attr->alt_pkey_index; 1888 context->alt_path.ackto = attr->alt_timeout << 3; 1889 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 1890 } 1891 1892 pd = get_pd(qp); 1893 get_cqs(qp, &send_cq, &recv_cq); 1894 context->pd = cpu_to_be32(pd->pdn); 1895 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 1896 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 1897 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 1898 1899 /* Set "fast registration enabled" for all kernel QPs */ 1900 if (!qp->ibqp.uobject) 1901 context->params1 |= cpu_to_be32(1 << 11); 1902 1903 if (attr_mask & IB_QP_RNR_RETRY) { 1904 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1905 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 1906 } 1907 1908 if (attr_mask & IB_QP_RETRY_CNT) { 1909 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1910 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 1911 } 1912 1913 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1914 if (attr->max_rd_atomic) 1915 context->params1 |= 1916 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1917 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 1918 } 1919 1920 if (attr_mask & IB_QP_SQ_PSN) 1921 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1922 1923 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1924 if (attr->max_dest_rd_atomic) 1925 context->params2 |= 1926 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1927 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 1928 } 1929 1930 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 1931 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 1932 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 1933 } 1934 1935 if (attr_mask & IB_M_EXT_CLASS_1) 1936 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_MASTER); 1937 1938 /* for now we enable also sqe on send */ 1939 if (attr_mask & IB_M_EXT_CLASS_2) { 1940 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_SYNC_SQ); 1941 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_MASTER); 1942 } 1943 1944 if (attr_mask & IB_M_EXT_CLASS_3) 1945 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_SYNC_RQ); 1946 1947 if (ibqp->srq) 1948 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 1949 1950 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 1951 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1952 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 1953 } 1954 if (attr_mask & IB_QP_RQ_PSN) 1955 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1956 1957 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 1958 if (attr_mask & IB_QP_QKEY) { 1959 if (qp->mlx4_ib_qp_type & 1960 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 1961 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 1962 else { 1963 if (mlx4_is_mfunc(dev->dev) && 1964 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 1965 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 1966 MLX4_RESERVED_QKEY_BASE) { 1967 pr_err("Cannot use reserved QKEY" 1968 " 0x%x (range 0xffff0000..0xffffffff" 1969 " is reserved)\n", attr->qkey); 1970 err = -EINVAL; 1971 goto out; 1972 } 1973 context->qkey = cpu_to_be32(attr->qkey); 1974 } 1975 optpar |= MLX4_QP_OPTPAR_Q_KEY; 1976 } 1977 1978 if (ibqp->srq) 1979 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn); 1980 1981 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1982 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1983 1984 if (cur_state == IB_QPS_INIT && 1985 new_state == IB_QPS_RTR && 1986 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI || 1987 ibqp->qp_type == IB_QPT_UD || 1988 ibqp->qp_type == IB_QPT_RAW_PACKET)) { 1989 context->pri_path.sched_queue = (qp->port - 1) << 6; 1990 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 1991 qp->mlx4_ib_qp_type & 1992 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 1993 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 1994 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 1995 context->pri_path.fl = 0x80; 1996 } else { 1997 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1998 context->pri_path.fl = 0x80; 1999 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2000 } 2001 is_eth = rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2002 IB_LINK_LAYER_ETHERNET; 2003 if (is_eth) { 2004 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2005 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2006 context->pri_path.feup = 1 << 7; /* don't fsm */ 2007 /* handle smac_index */ 2008 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2009 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2010 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2011 err = handle_eth_ud_smac_index(dev, qp, context); 2012 if (err) 2013 return -EINVAL; 2014 } 2015 } 2016 } 2017 2018 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2019 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2020 sqd_event = 1; 2021 else 2022 sqd_event = 0; 2023 2024 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2025 context->rlkey |= (1 << 4); 2026 2027 if ((attr_mask & IB_QP_GROUP_RSS) && 2028 (qp->qpg_data->rss_child_count > 1)) { 2029 struct mlx4_ib_qpg_data *qpg_data = qp->qpg_data; 2030 void *rss_context_base = &context->pri_path; 2031 struct mlx4_rss_context *rss_context = 2032 (struct mlx4_rss_context *) (rss_context_base 2033 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH); 2034 2035 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2036 2037 /* This should be tbl_sz_base_qpn */ 2038 rss_context->base_qpn = cpu_to_be32(qpg_data->rss_qpn_base | 2039 (ilog2(qpg_data->rss_child_count) << 24)); 2040 rss_context->default_qpn = cpu_to_be32(qpg_data->rss_qpn_base); 2041 /* This should be flags_hash_fn */ 2042 rss_context->flags = MLX4_RSS_TCP_IPV6 | 2043 MLX4_RSS_TCP_IPV4; 2044 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS) { 2045 rss_context->base_qpn_udp = rss_context->default_qpn; 2046 rss_context->flags |= MLX4_RSS_IPV6 | 2047 MLX4_RSS_IPV4 | 2048 MLX4_RSS_UDP_IPV6 | 2049 MLX4_RSS_UDP_IPV4; 2050 } 2051 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) { 2052 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 2053 0x1983A2FC, 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 2054 0xA74499AD, 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; 2055 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2056 memcpy(rss_context->rss_key, rsskey, 2057 sizeof(rss_context->rss_key)); 2058 } else { 2059 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 2060 memset(rss_context->rss_key, 0, 2061 sizeof(rss_context->rss_key)); 2062 } 2063 } 2064 /* 2065 * Before passing a kernel QP to the HW, make sure that the 2066 * ownership bits of the send queue are set and the SQ 2067 * headroom is stamped so that the hardware doesn't start 2068 * processing stale work requests. 2069 */ 2070 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2071 struct mlx4_wqe_ctrl_seg *ctrl; 2072 int i; 2073 2074 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2075 ctrl = get_send_wqe(qp, i); 2076 ctrl->owner_opcode = cpu_to_be32(1U << 31); 2077 if (qp->sq_max_wqes_per_wr == 1) 2078 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4); 2079 2080 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 2081 } 2082 } 2083 2084 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2085 to_mlx4_state(new_state), context, optpar, 2086 sqd_event, &qp->mqp); 2087 if (err) 2088 goto out; 2089 2090 qp->state = new_state; 2091 2092 if (attr_mask & IB_QP_ACCESS_FLAGS) 2093 qp->atomic_rd_en = attr->qp_access_flags; 2094 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2095 qp->resp_depth = attr->max_dest_rd_atomic; 2096 if (attr_mask & IB_QP_PORT) { 2097 qp->port = attr->port_num; 2098 update_mcg_macs(dev, qp); 2099 } 2100 if (attr_mask & IB_QP_ALT_PATH) 2101 qp->alt_port = attr->alt_port_num; 2102 2103 if (is_sqp(dev, qp)) 2104 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2105 2106 /* Set 'ignore_cq_overrun' bits for collectives offload */ 2107 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2108 if (attr_mask & (IB_M_EXT_CLASS_2 | IB_M_EXT_CLASS_3)) { 2109 err = mlx4_ib_ignore_overrun_cq(ibqp->send_cq); 2110 if (err) { 2111 pr_err("Failed to set ignore CQ " 2112 "overrun for QP 0x%x's send CQ\n", 2113 ibqp->qp_num); 2114 goto out; 2115 } 2116 2117 if (ibqp->recv_cq != ibqp->send_cq) { 2118 err = mlx4_ib_ignore_overrun_cq(ibqp->recv_cq); 2119 if (err) { 2120 pr_err("Failed to set ignore " 2121 "CQ overrun for QP 0x%x's recv " 2122 "CQ\n", ibqp->qp_num); 2123 goto out; 2124 } 2125 } 2126 } 2127 } 2128 2129 /* 2130 * If we moved QP0 to RTR, bring the IB link up; if we moved 2131 * QP0 to RESET or ERROR, bring the link back down. 2132 */ 2133 if (is_qp0(dev, qp)) { 2134 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2135 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2136 pr_warn("INIT_PORT failed for port %d\n", 2137 qp->port); 2138 2139 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2140 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2141 mlx4_CLOSE_PORT(dev->dev, qp->port); 2142 } 2143 2144 /* 2145 * If we moved a kernel QP to RESET, clean up all old CQ 2146 * entries and reinitialize the QP. 2147 */ 2148 if (new_state == IB_QPS_RESET) { 2149 if (!ibqp->uobject) { 2150 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2151 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2152 if (send_cq != recv_cq) 2153 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2154 2155 qp->rq.head = 0; 2156 qp->rq.tail = 0; 2157 qp->sq.head = 0; 2158 qp->sq.tail = 0; 2159 qp->sq_next_wqe = 0; 2160 if (qp->rq.wqe_cnt) 2161 *qp->db.db = 0; 2162 2163 if (qp->flags & MLX4_IB_QP_NETIF && 2164 (qp->qpg_type == IB_QPG_NONE || 2165 qp->qpg_type == IB_QPG_PARENT)) 2166 mlx4_ib_steer_qp_reg(dev, qp, 0); 2167 } 2168 if (qp->pri.smac) { 2169 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2170 qp->pri.smac = 0; 2171 } 2172 if (qp->alt.smac) { 2173 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2174 qp->alt.smac = 0; 2175 } 2176 if (qp->pri.vid < 0x1000) { 2177 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2178 qp->pri.vid = 0xFFFF; 2179 qp->pri.candidate_vid = 0xFFFF; 2180 qp->pri.update_vid = 0; 2181 } 2182 2183 if (qp->alt.vid < 0x1000) { 2184 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2185 qp->alt.vid = 0xFFFF; 2186 qp->alt.candidate_vid = 0xFFFF; 2187 qp->alt.update_vid = 0; 2188 } 2189 } 2190 2191out: 2192 if (err && steer_qp) 2193 mlx4_ib_steer_qp_reg(dev, qp, 0); 2194 kfree(context); 2195 if (qp->pri.candidate_smac) { 2196 if (err) 2197 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2198 else { 2199 if (qp->pri.smac) { 2200 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2201 } 2202 qp->pri.smac = qp->pri.candidate_smac; 2203 qp->pri.smac_index = qp->pri.candidate_smac_index; 2204 qp->pri.smac_port = qp->pri.candidate_smac_port; 2205 2206 } 2207 qp->pri.candidate_smac = 0; 2208 qp->pri.candidate_smac_index = 0; 2209 qp->pri.candidate_smac_port = 0; 2210 } 2211 if (qp->alt.candidate_smac) { 2212 if (err) 2213 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->pri.candidate_smac); 2214 else { 2215 if (qp->pri.smac) { 2216 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2217 } 2218 qp->alt.smac = qp->alt.candidate_smac; 2219 qp->alt.smac_index = qp->alt.candidate_smac_index; 2220 qp->alt.smac_port = qp->alt.candidate_smac_port; 2221 2222 } 2223 qp->pri.candidate_smac = 0; 2224 qp->pri.candidate_smac_index = 0; 2225 qp->pri.candidate_smac_port = 0; 2226 } 2227 2228 if (qp->pri.update_vid) { 2229 if (err) { 2230 if (qp->pri.candidate_vid < 0x1000) 2231 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2232 qp->pri.candidate_vid); 2233 } else { 2234 if (qp->pri.vid < 0x1000) 2235 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2236 qp->pri.vid); 2237 qp->pri.vid = qp->pri.candidate_vid; 2238 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2239 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2240 } 2241 qp->pri.candidate_vid = 0xFFFF; 2242 qp->pri.update_vid = 0; 2243 } 2244 2245 if (qp->alt.update_vid) { 2246 if (err) { 2247 if (qp->alt.candidate_vid < 0x1000) 2248 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2249 qp->alt.candidate_vid); 2250 } else { 2251 if (qp->alt.vid < 0x1000) 2252 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2253 qp->alt.vid); 2254 qp->alt.vid = qp->alt.candidate_vid; 2255 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2256 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2257 } 2258 qp->alt.candidate_vid = 0xFFFF; 2259 qp->alt.update_vid = 0; 2260 } 2261 2262 return err; 2263} 2264 2265int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2266 int attr_mask, struct ib_udata *udata) 2267{ 2268 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2269 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2270 enum ib_qp_state cur_state, new_state; 2271 int err = -EINVAL; 2272 2273 mutex_lock(&qp->mutex); 2274 2275 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2276 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2277 2278 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2279 attr_mask & ~IB_M_QP_MOD_VEND_MASK)) { 2280 pr_debug("qpn 0x%x: invalid attribute mask specified " 2281 "for transition %d to %d. qp_type %d," 2282 " attr_mask 0x%x\n", 2283 ibqp->qp_num, cur_state, new_state, 2284 ibqp->qp_type, attr_mask); 2285 goto out; 2286 } 2287 2288 if ((attr_mask & IB_M_QP_MOD_VEND_MASK) && !dev->dev->caps.sync_qp) { 2289 pr_err("extended verbs are not supported by %s\n", 2290 dev->ib_dev.name); 2291 goto out; 2292 } 2293 2294 if ((attr_mask & IB_QP_PORT) && 2295 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2296 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2297 "for transition %d to %d. qp_type %d\n", 2298 ibqp->qp_num, attr->port_num, cur_state, 2299 new_state, ibqp->qp_type); 2300 goto out; 2301 } 2302 2303 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2304 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2305 IB_LINK_LAYER_ETHERNET)) 2306 goto out; 2307 2308 if (attr_mask & IB_QP_PKEY_INDEX) { 2309 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2310 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2311 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2312 "for transition %d to %d. qp_type %d\n", 2313 ibqp->qp_num, attr->pkey_index, cur_state, 2314 new_state, ibqp->qp_type); 2315 goto out; 2316 } 2317 } 2318 2319 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2320 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2321 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2322 "Transition %d to %d. qp_type %d\n", 2323 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2324 new_state, ibqp->qp_type); 2325 goto out; 2326 } 2327 2328 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2329 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2330 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2331 "Transition %d to %d. qp_type %d\n", 2332 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2333 new_state, ibqp->qp_type); 2334 goto out; 2335 } 2336 2337 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2338 err = 0; 2339 goto out; 2340 } 2341 2342 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2343 2344out: 2345 mutex_unlock(&qp->mutex); 2346 return err; 2347} 2348 2349static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2350 struct ib_send_wr *wr, 2351 void *wqe, unsigned *mlx_seg_len) 2352{ 2353 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2354 struct ib_device *ib_dev = &mdev->ib_dev; 2355 struct mlx4_wqe_mlx_seg *mlx = wqe; 2356 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2357 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2358 u16 pkey; 2359 u32 qkey; 2360 int send_size; 2361 int header_size; 2362 int spc; 2363 int i; 2364 2365 if (wr->opcode != IB_WR_SEND) 2366 return -EINVAL; 2367 2368 send_size = 0; 2369 2370 for (i = 0; i < wr->num_sge; ++i) 2371 send_size += wr->sg_list[i].length; 2372 2373 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2374 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2375 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2376 send_size += sizeof (struct mlx4_ib_tunnel_header); 2377 2378 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header); 2379 2380 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2381 sqp->ud_header.lrh.service_level = 2382 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2383 sqp->ud_header.lrh.destination_lid = 2384 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2385 sqp->ud_header.lrh.source_lid = 2386 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2387 } 2388 2389 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2390 2391 /* force loopback */ 2392 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2393 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2394 2395 sqp->ud_header.lrh.virtual_lane = 0; 2396 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 2397 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2398 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2399 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2400 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2401 else 2402 sqp->ud_header.bth.destination_qpn = 2403 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]); 2404 2405 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2406 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2407 return -EINVAL; 2408 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2409 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2410 2411 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2412 sqp->ud_header.immediate_present = 0; 2413 2414 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2415 2416 /* 2417 * Inline data segments may not cross a 64 byte boundary. If 2418 * our UD header is bigger than the space available up to the 2419 * next 64 byte boundary in the WQE, use two inline data 2420 * segments to hold the UD header. 2421 */ 2422 spc = MLX4_INLINE_ALIGN - 2423 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2424 if (header_size <= spc) { 2425 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2426 memcpy(inl + 1, sqp->header_buf, header_size); 2427 i = 1; 2428 } else { 2429 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2430 memcpy(inl + 1, sqp->header_buf, spc); 2431 2432 inl = (void *) (inl + 1) + spc; 2433 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2434 /* 2435 * Need a barrier here to make sure all the data is 2436 * visible before the byte_count field is set. 2437 * Otherwise the HCA prefetcher could grab the 64-byte 2438 * chunk with this inline segment and get a valid (!= 2439 * 0xffffffff) byte count but stale data, and end up 2440 * generating a packet with bad headers. 2441 * 2442 * The first inline segment's byte_count field doesn't 2443 * need a barrier, because it comes after a 2444 * control/MLX segment and therefore is at an offset 2445 * of 16 mod 64. 2446 */ 2447 wmb(); 2448 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2449 i = 2; 2450 } 2451 2452 *mlx_seg_len = 2453 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2454 return 0; 2455} 2456 2457static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr, 2458 void *wqe, unsigned *mlx_seg_len) 2459{ 2460 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2461 struct mlx4_wqe_mlx_seg *mlx = wqe; 2462 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2463 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2464 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2465 union ib_gid sgid; 2466 u16 pkey; 2467 int send_size; 2468 int header_size; 2469 int spc; 2470 int i; 2471 int is_eth; 2472 int is_vlan = 0; 2473 int is_grh; 2474 u16 vlan = 0; 2475 int err = 0; 2476 2477 send_size = 0; 2478 for (i = 0; i < wr->num_sge; ++i) 2479 send_size += wr->sg_list[i].length; 2480 2481 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2482 is_grh = mlx4_ib_ah_grh_present(ah); 2483 if (is_eth) { 2484 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2485 /* When multi-function is enabled, the ib_core gid 2486 * indexes don't necessarily match the hw ones, so 2487 * we must use our own cache */ 2488 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2489 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2490 ah->av.ib.gid_index, &sgid.raw[0]); 2491 if (err) 2492 return err; 2493 } else { 2494 err = ib_get_cached_gid(ib_dev, 2495 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2496 ah->av.ib.gid_index, &sgid); 2497 if (err) 2498 return err; 2499 } 2500 2501 vlan = rdma_get_vlan_id(&sgid); 2502 is_vlan = vlan < 0x1000; 2503 } 2504 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header); 2505 2506 if (!is_eth) { 2507 sqp->ud_header.lrh.service_level = 2508 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2509 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 2510 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2511 } 2512 2513 if (is_grh) { 2514 sqp->ud_header.grh.traffic_class = 2515 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 2516 sqp->ud_header.grh.flow_label = 2517 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 2518 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 2519 if (is_eth) 2520 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 2521 else { 2522 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2523 /* When multi-function is enabled, the ib_core gid 2524 * indexes don't necessarily match the hw ones, so 2525 * we must use our own cache */ 2526 sqp->ud_header.grh.source_gid.global.subnet_prefix = 2527 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2528 subnet_prefix; 2529 sqp->ud_header.grh.source_gid.global.interface_id = 2530 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2531 guid_cache[ah->av.ib.gid_index]; 2532 } else 2533 ib_get_cached_gid(ib_dev, 2534 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2535 ah->av.ib.gid_index, 2536 &sqp->ud_header.grh.source_gid); 2537 } 2538 memcpy(sqp->ud_header.grh.destination_gid.raw, 2539 ah->av.ib.dgid, 16); 2540 } 2541 2542 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2543 2544 if (!is_eth) { 2545 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 2546 (sqp->ud_header.lrh.destination_lid == 2547 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 2548 (sqp->ud_header.lrh.service_level << 8)); 2549 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 2550 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 2551 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2552 } 2553 2554 switch (wr->opcode) { 2555 case IB_WR_SEND: 2556 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2557 sqp->ud_header.immediate_present = 0; 2558 break; 2559 case IB_WR_SEND_WITH_IMM: 2560 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2561 sqp->ud_header.immediate_present = 1; 2562 sqp->ud_header.immediate_data = wr->ex.imm_data; 2563 break; 2564 default: 2565 return -EINVAL; 2566 } 2567 2568 if (is_eth) { 2569 u8 smac[6]; 2570 struct in6_addr in6; 2571 2572 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 2573 2574 mlx->sched_prio = cpu_to_be16(pcp); 2575 2576 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 2577 /* FIXME: cache smac value? */ 2578 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 2579 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 2580 memcpy(&in6, sgid.raw, sizeof(in6)); 2581 rdma_get_ll_mac(&in6, smac); 2582 memcpy(sqp->ud_header.eth.smac_h, smac, 6); 2583 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 2584 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 2585 if (!is_vlan) { 2586 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE); 2587 } else { 2588 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE); 2589 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 2590 } 2591 } else { 2592 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; 2593 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 2594 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 2595 } 2596 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 2597 if (!sqp->qp.ibqp.qp_num) 2598 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 2599 else 2600 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey); 2601 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2602 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2603 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2604 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? 2605 sqp->qkey : wr->wr.ud.remote_qkey); 2606 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 2607 2608 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2609 2610 if (0) { 2611 pr_err("built UD header of size %d:\n", header_size); 2612 for (i = 0; i < header_size / 4; ++i) { 2613 if (i % 8 == 0) 2614 pr_err(" [%02x] ", i * 4); 2615 pr_cont(" %08x", 2616 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 2617 if ((i + 1) % 8 == 0) 2618 pr_cont("\n"); 2619 } 2620 pr_err("\n"); 2621 } 2622 2623 /* 2624 * Inline data segments may not cross a 64 byte boundary. If 2625 * our UD header is bigger than the space available up to the 2626 * next 64 byte boundary in the WQE, use two inline data 2627 * segments to hold the UD header. 2628 */ 2629 spc = MLX4_INLINE_ALIGN - 2630 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2631 if (header_size <= spc) { 2632 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2633 memcpy(inl + 1, sqp->header_buf, header_size); 2634 i = 1; 2635 } else { 2636 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2637 memcpy(inl + 1, sqp->header_buf, spc); 2638 2639 inl = (void *) (inl + 1) + spc; 2640 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2641 /* 2642 * Need a barrier here to make sure all the data is 2643 * visible before the byte_count field is set. 2644 * Otherwise the HCA prefetcher could grab the 64-byte 2645 * chunk with this inline segment and get a valid (!= 2646 * 0xffffffff) byte count but stale data, and end up 2647 * generating a packet with bad headers. 2648 * 2649 * The first inline segment's byte_count field doesn't 2650 * need a barrier, because it comes after a 2651 * control/MLX segment and therefore is at an offset 2652 * of 16 mod 64. 2653 */ 2654 wmb(); 2655 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2656 i = 2; 2657 } 2658 2659 *mlx_seg_len = 2660 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2661 return 0; 2662} 2663 2664static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2665{ 2666 unsigned cur; 2667 struct mlx4_ib_cq *cq; 2668 2669 cur = wq->head - wq->tail; 2670 if (likely(cur + nreq < wq->max_post)) 2671 return 0; 2672 2673 cq = to_mcq(ib_cq); 2674 spin_lock(&cq->lock); 2675 cur = wq->head - wq->tail; 2676 spin_unlock(&cq->lock); 2677 2678 return cur + nreq >= wq->max_post; 2679} 2680 2681static __be32 convert_access(int acc) 2682{ 2683 return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC) : 0) | 2684 (acc & IB_ACCESS_REMOTE_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) | 2685 (acc & IB_ACCESS_REMOTE_READ ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ) : 0) | 2686 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 2687 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 2688} 2689 2690static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr) 2691{ 2692 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list); 2693 int i; 2694 2695 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i) 2696 mfrpl->mapped_page_list[i] = 2697 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] | 2698 MLX4_MTT_FLAG_PRESENT); 2699 2700 fseg->flags = convert_access(wr->wr.fast_reg.access_flags); 2701 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey); 2702 fseg->buf_list = cpu_to_be64(mfrpl->map); 2703 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start); 2704 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length); 2705 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 2706 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift); 2707 fseg->reserved[0] = 0; 2708 fseg->reserved[1] = 0; 2709} 2710 2711static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 2712{ 2713 iseg->flags = 0; 2714 iseg->mem_key = cpu_to_be32(rkey); 2715 iseg->guest_id = 0; 2716 iseg->pa = 0; 2717} 2718 2719static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 2720 u64 remote_addr, u32 rkey) 2721{ 2722 rseg->raddr = cpu_to_be64(remote_addr); 2723 rseg->rkey = cpu_to_be32(rkey); 2724 rseg->reserved = 0; 2725} 2726 2727static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr) 2728{ 2729 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 2730 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 2731 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 2732 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 2733 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 2734 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask); 2735 } else { 2736 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 2737 aseg->compare = 0; 2738 } 2739 2740} 2741 2742static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 2743 struct ib_send_wr *wr) 2744{ 2745 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 2746 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask); 2747 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 2748 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask); 2749} 2750 2751static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 2752 struct ib_send_wr *wr) 2753{ 2754 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av)); 2755 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2756 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 2757 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan; 2758 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6); 2759} 2760 2761static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 2762 struct mlx4_wqe_datagram_seg *dseg, 2763 struct ib_send_wr *wr, enum ib_qp_type qpt) 2764{ 2765 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av; 2766 struct mlx4_av sqp_av = {0}; 2767 int port = *((u8 *) &av->ib.port_pd) & 0x3; 2768 2769 /* force loopback */ 2770 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 2771 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 2772 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 2773 cpu_to_be32(0xf0000000); 2774 2775 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 2776 /* This function used only for sending on QP1 proxies */ 2777 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]); 2778 /* Use QKEY from the QP context, which is set by master */ 2779 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2780} 2781 2782static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len) 2783{ 2784 struct mlx4_wqe_inline_seg *inl = wqe; 2785 struct mlx4_ib_tunnel_header hdr; 2786 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2787 int spc; 2788 int i; 2789 2790 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 2791 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2792 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index); 2793 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 2794 2795 spc = MLX4_INLINE_ALIGN - 2796 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2797 if (sizeof (hdr) <= spc) { 2798 memcpy(inl + 1, &hdr, sizeof (hdr)); 2799 wmb(); 2800 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 2801 i = 1; 2802 } else { 2803 memcpy(inl + 1, &hdr, spc); 2804 wmb(); 2805 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2806 2807 inl = (void *) (inl + 1) + spc; 2808 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 2809 wmb(); 2810 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 2811 i = 2; 2812 } 2813 2814 *mlx_seg_len = 2815 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 2816} 2817 2818static void set_mlx_icrc_seg(void *dseg) 2819{ 2820 u32 *t = dseg; 2821 struct mlx4_wqe_inline_seg *iseg = dseg; 2822 2823 t[1] = 0; 2824 2825 /* 2826 * Need a barrier here before writing the byte_count field to 2827 * make sure that all the data is visible before the 2828 * byte_count field is set. Otherwise, if the segment begins 2829 * a new cacheline, the HCA prefetcher could grab the 64-byte 2830 * chunk and get a valid (!= * 0xffffffff) byte count but 2831 * stale data, and end up sending the wrong data. 2832 */ 2833 wmb(); 2834 2835 iseg->byte_count = cpu_to_be32((1U << 31) | 4); 2836} 2837 2838static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2839{ 2840 dseg->lkey = cpu_to_be32(sg->lkey); 2841 dseg->addr = cpu_to_be64(sg->addr); 2842 2843 /* 2844 * Need a barrier here before writing the byte_count field to 2845 * make sure that all the data is visible before the 2846 * byte_count field is set. Otherwise, if the segment begins 2847 * a new cacheline, the HCA prefetcher could grab the 64-byte 2848 * chunk and get a valid (!= * 0xffffffff) byte count but 2849 * stale data, and end up sending the wrong data. 2850 */ 2851 wmb(); 2852 2853 dseg->byte_count = cpu_to_be32(sg->length); 2854} 2855 2856static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2857{ 2858 dseg->byte_count = cpu_to_be32(sg->length); 2859 dseg->lkey = cpu_to_be32(sg->lkey); 2860 dseg->addr = cpu_to_be64(sg->addr); 2861} 2862 2863static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr, 2864 struct mlx4_ib_qp *qp, unsigned *lso_seg_len, 2865 __be32 *lso_hdr_sz, __be32 *blh) 2866{ 2867 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16); 2868 2869 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 2870 *blh = cpu_to_be32(1 << 6); 2871 2872 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 2873 wr->num_sge > qp->sq.max_gs - (halign >> 4))) 2874 return -EINVAL; 2875 2876 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen); 2877 2878 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 | 2879 wr->wr.ud.hlen); 2880 *lso_seg_len = halign; 2881 return 0; 2882} 2883 2884static __be32 send_ieth(struct ib_send_wr *wr) 2885{ 2886 switch (wr->opcode) { 2887 case IB_WR_SEND_WITH_IMM: 2888 case IB_WR_RDMA_WRITE_WITH_IMM: 2889 return wr->ex.imm_data; 2890 2891 case IB_WR_SEND_WITH_INV: 2892 return cpu_to_be32(wr->ex.invalidate_rkey); 2893 2894 default: 2895 return 0; 2896 } 2897} 2898 2899static void add_zero_len_inline(void *wqe) 2900{ 2901 struct mlx4_wqe_inline_seg *inl = wqe; 2902 memset(wqe, 0, 16); 2903 inl->byte_count = cpu_to_be32(1U << 31); 2904} 2905 2906static int lay_inline_data(struct mlx4_ib_qp *qp, struct ib_send_wr *wr, 2907 void *wqe, int *sz) 2908{ 2909 struct mlx4_wqe_inline_seg *seg; 2910 void *addr; 2911 int len, seg_len; 2912 int num_seg; 2913 int off, to_copy; 2914 int i; 2915 int inl = 0; 2916 2917 seg = wqe; 2918 wqe += sizeof *seg; 2919 off = ((unsigned long)wqe) & (unsigned long)(MLX4_INLINE_ALIGN - 1); 2920 num_seg = 0; 2921 seg_len = 0; 2922 2923 for (i = 0; i < wr->num_sge; ++i) { 2924 addr = (void *) (unsigned long)(wr->sg_list[i].addr); 2925 len = wr->sg_list[i].length; 2926 inl += len; 2927 2928 if (inl > qp->max_inline_data) { 2929 inl = 0; 2930 return -1; 2931 } 2932 2933 while (len >= MLX4_INLINE_ALIGN - off) { 2934 to_copy = MLX4_INLINE_ALIGN - off; 2935 memcpy(wqe, addr, to_copy); 2936 len -= to_copy; 2937 wqe += to_copy; 2938 addr += to_copy; 2939 seg_len += to_copy; 2940 wmb(); /* see comment below */ 2941 seg->byte_count = htonl(MLX4_INLINE_SEG | seg_len); 2942 seg_len = 0; 2943 seg = wqe; 2944 wqe += sizeof *seg; 2945 off = sizeof *seg; 2946 ++num_seg; 2947 } 2948 2949 memcpy(wqe, addr, len); 2950 wqe += len; 2951 seg_len += len; 2952 off += len; 2953 } 2954 2955 if (seg_len) { 2956 ++num_seg; 2957 /* 2958 * Need a barrier here to make sure 2959 * all the data is visible before the 2960 * byte_count field is set. Otherwise 2961 * the HCA prefetcher could grab the 2962 * 64-byte chunk with this inline 2963 * segment and get a valid (!= 2964 * 0xffffffff) byte count but stale 2965 * data, and end up sending the wrong 2966 * data. 2967 */ 2968 wmb(); 2969 seg->byte_count = htonl(MLX4_INLINE_SEG | seg_len); 2970 } 2971 2972 *sz = (inl + num_seg * sizeof *seg + 15) / 16; 2973 2974 return 0; 2975} 2976 2977/* 2978 * Avoid using memcpy() to copy to BlueFlame page, since memcpy() 2979 * implementations may use move-string-buffer assembler instructions, 2980 * which do not guarantee order of copying. 2981 */ 2982static void mlx4_bf_copy(unsigned long *dst, unsigned long *src, 2983 unsigned bytecnt) 2984{ 2985 __iowrite64_copy(dst, src, bytecnt / 8); 2986} 2987 2988int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 2989 struct ib_send_wr **bad_wr) 2990{ 2991 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2992 void *wqe; 2993 struct mlx4_wqe_ctrl_seg *uninitialized_var(ctrl); 2994 struct mlx4_wqe_data_seg *dseg; 2995 unsigned long flags; 2996 int nreq; 2997 int err = 0; 2998 unsigned ind; 2999 int uninitialized_var(stamp); 3000 int uninitialized_var(size); 3001 unsigned uninitialized_var(seglen); 3002 __be32 dummy; 3003 __be32 *lso_wqe; 3004 __be32 uninitialized_var(lso_hdr_sz); 3005 __be32 blh; 3006 int i; 3007 int inl = 0; 3008 spin_lock_irqsave(&qp->sq.lock, flags); 3009 3010 ind = qp->sq_next_wqe; 3011 3012 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3013 lso_wqe = &dummy; 3014 blh = 0; 3015 3016 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3017 err = -ENOMEM; 3018 *bad_wr = wr; 3019 goto out; 3020 } 3021 3022 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3023 err = -EINVAL; 3024 *bad_wr = wr; 3025 goto out; 3026 } 3027 3028 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3029 *((u32 *) (&ctrl->vlan_tag)) = 0; 3030 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3031 3032 ctrl->srcrb_flags = 3033 (wr->send_flags & IB_SEND_SIGNALED ? 3034 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3035 (wr->send_flags & IB_SEND_SOLICITED ? 3036 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3037 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3038 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3039 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3040 qp->sq_signal_bits; 3041 3042 ctrl->imm = send_ieth(wr); 3043 3044 wqe += sizeof *ctrl; 3045 size = sizeof *ctrl / 16; 3046 3047 switch (qp->mlx4_ib_qp_type) { 3048 case MLX4_IB_QPT_RC: 3049 case MLX4_IB_QPT_UC: 3050 switch (wr->opcode) { 3051 case IB_WR_ATOMIC_CMP_AND_SWP: 3052 case IB_WR_ATOMIC_FETCH_AND_ADD: 3053 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3054 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 3055 wr->wr.atomic.rkey); 3056 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3057 3058 set_atomic_seg(wqe, wr); 3059 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3060 3061 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3062 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3063 3064 break; 3065 3066 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3067 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 3068 wr->wr.atomic.rkey); 3069 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3070 3071 set_masked_atomic_seg(wqe, wr); 3072 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3073 3074 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3075 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3076 3077 break; 3078 3079 case IB_WR_RDMA_READ: 3080 case IB_WR_RDMA_WRITE: 3081 case IB_WR_RDMA_WRITE_WITH_IMM: 3082 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 3083 wr->wr.rdma.rkey); 3084 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3085 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3086 break; 3087 3088 case IB_WR_LOCAL_INV: 3089 ctrl->srcrb_flags |= 3090 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3091 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3092 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3093 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3094 break; 3095 3096 case IB_WR_FAST_REG_MR: 3097 ctrl->srcrb_flags |= 3098 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3099 set_fmr_seg(wqe, wr); 3100 wqe += sizeof (struct mlx4_wqe_fmr_seg); 3101 size += sizeof (struct mlx4_wqe_fmr_seg) / 16; 3102 break; 3103 3104 default: 3105 /* No extra segments required for sends */ 3106 break; 3107 } 3108 break; 3109 3110 case MLX4_IB_QPT_TUN_SMI_OWNER: 3111 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen); 3112 if (unlikely(err)) { 3113 *bad_wr = wr; 3114 goto out; 3115 } 3116 wqe += seglen; 3117 size += seglen / 16; 3118 break; 3119 case MLX4_IB_QPT_TUN_SMI: 3120 case MLX4_IB_QPT_TUN_GSI: 3121 /* this is a UD qp used in MAD responses to slaves. */ 3122 set_datagram_seg(wqe, wr); 3123 /* set the forced-loopback bit in the data seg av */ 3124 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3125 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3126 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3127 break; 3128 case MLX4_IB_QPT_UD: 3129 set_datagram_seg(wqe, wr); 3130 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3131 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3132 3133 if (wr->opcode == IB_WR_LSO) { 3134 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh); 3135 if (unlikely(err)) { 3136 *bad_wr = wr; 3137 goto out; 3138 } 3139 lso_wqe = (__be32 *) wqe; 3140 wqe += seglen; 3141 size += seglen / 16; 3142 } 3143 break; 3144 3145 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3146 if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) { 3147 err = -ENOSYS; 3148 *bad_wr = wr; 3149 goto out; 3150 } 3151 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen); 3152 if (unlikely(err)) { 3153 *bad_wr = wr; 3154 goto out; 3155 } 3156 wqe += seglen; 3157 size += seglen / 16; 3158 /* to start tunnel header on a cache-line boundary */ 3159 add_zero_len_inline(wqe); 3160 wqe += 16; 3161 size++; 3162 build_tunnel_header(wr, wqe, &seglen); 3163 wqe += seglen; 3164 size += seglen / 16; 3165 break; 3166 case MLX4_IB_QPT_PROXY_SMI: 3167 /* don't allow QP0 sends on guests */ 3168 err = -ENOSYS; 3169 *bad_wr = wr; 3170 goto out; 3171 case MLX4_IB_QPT_PROXY_GSI: 3172 /* If we are tunneling special qps, this is a UD qp. 3173 * In this case we first add a UD segment targeting 3174 * the tunnel qp, and then add a header with address 3175 * information */ 3176 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type); 3177 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3178 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3179 build_tunnel_header(wr, wqe, &seglen); 3180 wqe += seglen; 3181 size += seglen / 16; 3182 break; 3183 3184 case MLX4_IB_QPT_SMI: 3185 case MLX4_IB_QPT_GSI: 3186 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen); 3187 if (unlikely(err)) { 3188 *bad_wr = wr; 3189 goto out; 3190 } 3191 wqe += seglen; 3192 size += seglen / 16; 3193 break; 3194 3195 default: 3196 break; 3197 } 3198 3199 /* 3200 * Write data segments in reverse order, so as to 3201 * overwrite cacheline stamp last within each 3202 * cacheline. This avoids issues with WQE 3203 * prefetching. 3204 */ 3205 dseg = wqe; 3206 dseg += wr->num_sge - 1; 3207 3208 /* Add one more inline data segment for ICRC for MLX sends */ 3209 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3210 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3211 qp->mlx4_ib_qp_type & 3212 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3213 set_mlx_icrc_seg(dseg + 1); 3214 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3215 } 3216 3217 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) { 3218 int sz; 3219 err = lay_inline_data(qp, wr, wqe, &sz); 3220 if (!err) { 3221 inl = 1; 3222 size += sz; 3223 } 3224 } else { 3225 size += wr->num_sge * 3226 (sizeof(struct mlx4_wqe_data_seg) / 16); 3227 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3228 set_data_seg(dseg, wr->sg_list + i); 3229 } 3230 3231 /* 3232 * Possibly overwrite stamping in cacheline with LSO 3233 * segment only after making sure all data segments 3234 * are written. 3235 */ 3236 wmb(); 3237 *lso_wqe = lso_hdr_sz; 3238 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? 3239 MLX4_WQE_CTRL_FENCE : 0) | size; 3240 3241 /* 3242 * Make sure descriptor is fully written before 3243 * setting ownership bit (because HW can start 3244 * executing as soon as we do). 3245 */ 3246 wmb(); 3247 3248 if (wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3249 *bad_wr = wr; 3250 err = -EINVAL; 3251 goto out; 3252 } 3253 3254 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3255 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0) | blh; 3256 3257 stamp = ind + qp->sq_spare_wqes; 3258 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 3259 3260 /* 3261 * We can improve latency by not stamping the last 3262 * send queue WQE until after ringing the doorbell, so 3263 * only stamp here if there are still more WQEs to post. 3264 * 3265 * Same optimization applies to padding with NOP wqe 3266 * in case of WQE shrinking (used to prevent wrap-around 3267 * in the middle of WR). 3268 */ 3269 if (wr->next) { 3270 stamp_send_wqe(qp, stamp, size * 16); 3271 ind = pad_wraparound(qp, ind); 3272 } 3273 } 3274 3275out: 3276 if (nreq == 1 && inl && size > 1 && size < qp->bf.buf_size / 16) { 3277 ctrl->owner_opcode |= htonl((qp->sq_next_wqe & 0xffff) << 8); 3278 /* We set above doorbell_qpn bits to 0 as part of vlan 3279 * tag initialization, so |= should be correct. 3280 */ 3281 *(u32 *) (&ctrl->vlan_tag) |= qp->doorbell_qpn; 3282 /* 3283 * Make sure that descriptor is written to memory 3284 * before writing to BlueFlame page. 3285 */ 3286 wmb(); 3287 3288 ++qp->sq.head; 3289 3290 mlx4_bf_copy(qp->bf.reg + qp->bf.offset, (unsigned long *) ctrl, 3291 ALIGN(size * 16, 64)); 3292 wc_wmb(); 3293 3294 qp->bf.offset ^= qp->bf.buf_size; 3295 3296 } else if (nreq) { 3297 qp->sq.head += nreq; 3298 3299 /* 3300 * Make sure that descriptors are written before 3301 * doorbell record. 3302 */ 3303 wmb(); 3304 3305 writel(qp->doorbell_qpn, qp->bf.uar->map + MLX4_SEND_DOORBELL); 3306 3307 /* 3308 * Make sure doorbells don't leak out of SQ spinlock 3309 * and reach the HCA out of order. 3310 */ 3311 mmiowb(); 3312 3313 } 3314 3315 if (likely(nreq)) { 3316 stamp_send_wqe(qp, stamp, size * 16); 3317 ind = pad_wraparound(qp, ind); 3318 qp->sq_next_wqe = ind; 3319 } 3320 3321 spin_unlock_irqrestore(&qp->sq.lock, flags); 3322 3323 return err; 3324} 3325 3326int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 3327 struct ib_recv_wr **bad_wr) 3328{ 3329 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3330 struct mlx4_wqe_data_seg *scat; 3331 unsigned long flags; 3332 int err = 0; 3333 int nreq; 3334 int ind; 3335 int max_gs; 3336 int i; 3337 3338 max_gs = qp->rq.max_gs; 3339 spin_lock_irqsave(&qp->rq.lock, flags); 3340 3341 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3342 3343 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3344 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3345 err = -ENOMEM; 3346 *bad_wr = wr; 3347 goto out; 3348 } 3349 3350 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3351 err = -EINVAL; 3352 *bad_wr = wr; 3353 goto out; 3354 } 3355 3356 scat = get_recv_wqe(qp, ind); 3357 3358 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3359 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3360 ib_dma_sync_single_for_device(ibqp->device, 3361 qp->sqp_proxy_rcv[ind].map, 3362 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3363 DMA_FROM_DEVICE); 3364 scat->byte_count = 3365 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3366 /* use dma lkey from upper layer entry */ 3367 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3368 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3369 scat++; 3370 max_gs--; 3371 } 3372 3373 for (i = 0; i < wr->num_sge; ++i) 3374 __set_data_seg(scat + i, wr->sg_list + i); 3375 3376 if (i < max_gs) { 3377 scat[i].byte_count = 0; 3378 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3379 scat[i].addr = 0; 3380 } 3381 3382 qp->rq.wrid[ind] = wr->wr_id; 3383 3384 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3385 } 3386 3387out: 3388 if (likely(nreq)) { 3389 qp->rq.head += nreq; 3390 3391 /* 3392 * Make sure that descriptors are written before 3393 * doorbell record. 3394 */ 3395 wmb(); 3396 3397 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3398 } 3399 3400 spin_unlock_irqrestore(&qp->rq.lock, flags); 3401 3402 return err; 3403} 3404 3405static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3406{ 3407 switch (mlx4_state) { 3408 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3409 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3410 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3411 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3412 case MLX4_QP_STATE_SQ_DRAINING: 3413 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3414 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3415 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3416 default: return -1; 3417 } 3418} 3419 3420static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3421{ 3422 switch (mlx4_mig_state) { 3423 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3424 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3425 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3426 default: return -1; 3427 } 3428} 3429 3430static int to_ib_qp_access_flags(int mlx4_flags) 3431{ 3432 int ib_flags = 0; 3433 3434 if (mlx4_flags & MLX4_QP_BIT_RRE) 3435 ib_flags |= IB_ACCESS_REMOTE_READ; 3436 if (mlx4_flags & MLX4_QP_BIT_RWE) 3437 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3438 if (mlx4_flags & MLX4_QP_BIT_RAE) 3439 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3440 3441 return ib_flags; 3442} 3443 3444static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 3445 struct mlx4_qp_path *path) 3446{ 3447 struct mlx4_dev *dev = ibdev->dev; 3448 int is_eth; 3449 3450 memset(ib_ah_attr, 0, sizeof *ib_ah_attr); 3451 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1; 3452 3453 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports) 3454 return; 3455 3456 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) == 3457 IB_LINK_LAYER_ETHERNET; 3458 if (is_eth) 3459 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) | 3460 ((path->sched_queue & 4) << 1); 3461 else 3462 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf; 3463 3464 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3465 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f; 3466 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3467 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0; 3468 if (ib_ah_attr->ah_flags) { 3469 ib_ah_attr->grh.sgid_index = path->mgid_index; 3470 ib_ah_attr->grh.hop_limit = path->hop_limit; 3471 ib_ah_attr->grh.traffic_class = 3472 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3473 ib_ah_attr->grh.flow_label = 3474 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3475 memcpy(ib_ah_attr->grh.dgid.raw, 3476 path->rgid, sizeof ib_ah_attr->grh.dgid.raw); 3477 } 3478} 3479 3480int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3481 struct ib_qp_init_attr *qp_init_attr) 3482{ 3483 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3484 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3485 struct mlx4_qp_context context; 3486 int mlx4_state; 3487 int err = 0; 3488 3489 mutex_lock(&qp->mutex); 3490 3491 if (qp->state == IB_QPS_RESET) { 3492 qp_attr->qp_state = IB_QPS_RESET; 3493 goto done; 3494 } 3495 3496 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3497 if (err) { 3498 err = -EINVAL; 3499 goto out; 3500 } 3501 3502 mlx4_state = be32_to_cpu(context.flags) >> 28; 3503 3504 qp->state = to_ib_qp_state(mlx4_state); 3505 qp_attr->qp_state = qp->state; 3506 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3507 qp_attr->path_mig_state = 3508 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3509 qp_attr->qkey = be32_to_cpu(context.qkey); 3510 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3511 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3512 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3513 qp_attr->qp_access_flags = 3514 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3515 3516 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3517 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3518 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3519 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3520 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 3521 } 3522 3523 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3524 if (qp_attr->qp_state == IB_QPS_INIT) 3525 qp_attr->port_num = qp->port; 3526 else 3527 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3528 3529 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3530 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3531 3532 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3533 3534 qp_attr->max_dest_rd_atomic = 3535 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 3536 qp_attr->min_rnr_timer = 3537 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 3538 qp_attr->timeout = context.pri_path.ackto >> 3; 3539 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 3540 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 3541 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 3542 3543done: 3544 qp_attr->cur_qp_state = qp_attr->qp_state; 3545 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3546 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3547 3548 if (!ibqp->uobject) { 3549 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3550 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3551 } else { 3552 qp_attr->cap.max_send_wr = 0; 3553 qp_attr->cap.max_send_sge = 0; 3554 } 3555 3556 /* 3557 * We don't support inline sends for kernel QPs (yet), and we 3558 * don't know what userspace's value should be. 3559 */ 3560 qp_attr->cap.max_inline_data = 0; 3561 3562 qp_init_attr->cap = qp_attr->cap; 3563 3564 qp_init_attr->create_flags = 0; 3565 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3566 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3567 3568 if (qp->flags & MLX4_IB_QP_LSO) 3569 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 3570 3571 if (qp->flags & MLX4_IB_QP_NETIF) 3572 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 3573 3574 qp_init_attr->sq_sig_type = 3575 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 3576 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3577 3578 qp_init_attr->qpg_type = ibqp->qpg_type; 3579 if (ibqp->qpg_type == IB_QPG_PARENT) 3580 qp_init_attr->cap.qpg_tss_mask_sz = qp->qpg_data->qpg_tss_mask_sz; 3581 else 3582 qp_init_attr->cap.qpg_tss_mask_sz = 0; 3583 3584out: 3585 mutex_unlock(&qp->mutex); 3586 return err; 3587} 3588 3589