imx_gptreg.h revision 261455
155682Smarkm/*- 2233294Sstas * Copyright (c) 2012, 2013 The FreeBSD Foundation 3233294Sstas * All rights reserved. 4233294Sstas * 555682Smarkm * This software was developed by Oleksandr Rybalko under sponsorship 6233294Sstas * from the FreeBSD Foundation. 7233294Sstas * 8233294Sstas * Redistribution and use in source and binary forms, with or without 955682Smarkm * modification, are permitted provided that the following conditions 10233294Sstas * are met: 11233294Sstas * 1. Redistributions of source code must retain the above copyright 1255682Smarkm * notice, this list of conditions and the following disclaimer. 13233294Sstas * 2. Redistributions in binary form must reproduce the above copyright 14233294Sstas * notice, this list of conditions and the following disclaimer in the 15233294Sstas * documentation and/or other materials provided with the distribution. 1655682Smarkm * 17233294Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18233294Sstas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19233294Sstas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2055682Smarkm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21233294Sstas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22233294Sstas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23233294Sstas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24233294Sstas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25233294Sstas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26233294Sstas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27233294Sstas * SUCH DAMAGE. 28233294Sstas * 29233294Sstas * $FreeBSD: stable/10/sys/arm/freescale/imx/imx_gptreg.h 261455 2014-02-04 03:36:42Z eadler $ 30233294Sstas */ 31233294Sstas 3255682Smarkm/* Registers definition for Freescale i.MX515 Generic Periodic Timer */ 3355682Smarkm 3455682Smarkm#define IMX_GPT_CR 0x0000 /* Control Register R/W */ 3555682Smarkm#define GPT_CR_FO3 (1U << 31) 36233294Sstas#define GPT_CR_FO2 (1 << 30) 3755682Smarkm#define GPT_CR_FO1 (1 << 29) 3872445Sassar#define GPT_CR_OM3_SHIFT 26 3972445Sassar#define GPT_CR_OM3_MASK 0x1c000000 4072445Sassar#define GPT_CR_OM2_SHIFT 23 4172445Sassar#define GPT_CR_OM2_MASK 0x03800000 4272445Sassar#define GPT_CR_OM1_SHIFT 20 4372445Sassar#define GPT_CR_OM1_MASK 0x00700000 4472445Sassar#define GPT_CR_OMX_NONE 0 4572445Sassar#define GPT_CR_OMX_TOGGLE 1 4672445Sassar#define GPT_CR_OMX_CLEAR 2 4772445Sassar#define GPT_CR_OMX_SET 3 4872445Sassar#define GPT_CR_OMX_PULSE 4 /* Run CLKSRC on output pin */ 49233294Sstas#define GPT_CR_IM2_SHIFT 18 50233294Sstas#define GPT_CR_IM2_MASK 0x000c0000 5172445Sassar#define GPT_CR_IM1_SHIFT 16 5272445Sassar#define GPT_CR_IM1_MASK 0x00030000 5372445Sassar#define GPT_CR_IMX_NONE 0 5472445Sassar#define GPT_CR_IMX_REDGE 1 5572445Sassar#define GPT_CR_IMX_FEDGE 2 56233294Sstas#define GPT_CR_IMX_BOTH 3 57233294Sstas#define GPT_CR_SWR (1 << 15) 5872445Sassar#define GPT_CR_24MEN (1 << 10) 5972445Sassar#define GPT_CR_FRR (1 << 9) 6072445Sassar#define GPT_CR_CLKSRC_NONE (0 << 6) 6172445Sassar#define GPT_CR_CLKSRC_IPG (1 << 6) 6278527Sassar#define GPT_CR_CLKSRC_IPG_HIGH (2 << 6) 6372445Sassar#define GPT_CR_CLKSRC_EXT (3 << 6) 6472445Sassar#define GPT_CR_CLKSRC_32K (4 << 6) 6572445Sassar#define GPT_CR_CLKSRC_24M (5 << 6) 6672445Sassar#define GPT_CR_STOPEN (1 << 5) 6772445Sassar#define GPT_CR_DOZEEN (1 << 4) 6872445Sassar#define GPT_CR_WAITEN (1 << 3) 6978527Sassar#define GPT_CR_DBGEN (1 << 2) 7072445Sassar#define GPT_CR_ENMOD (1 << 1) 7172445Sassar#define GPT_CR_EN (1 << 0) 7272445Sassar 7372445Sassar#define IMX_GPT_PR 0x0004 /* Prescaler Register R/W */ 7472445Sassar#define GPT_PR_VALUE_SHIFT 0 7578527Sassar#define GPT_PR_VALUE_MASK 0x00000fff 7672445Sassar#define GPT_PR_VALUE_SHIFT_24M 12 7772445Sassar#define GPT_PR_VALUE_MASK_24M 0x0000f000 7878527Sassar 7978527Sassar/* Same map for SR and IR */ 8078527Sassar#define IMX_GPT_SR 0x0008 /* Status Register R/W */ 8172445Sassar#define IMX_GPT_IR 0x000c /* Interrupt Register R/W */ 8272445Sassar#define GPT_IR_ROV (1 << 5) 8372445Sassar#define GPT_IR_IF2 (1 << 4) 8472445Sassar#define GPT_IR_IF1 (1 << 3) 85178825Sdfr#define GPT_IR_OF3 (1 << 2) 86178825Sdfr#define GPT_IR_OF2 (1 << 1) 87178825Sdfr#define GPT_IR_OF1 (1 << 0) 88178825Sdfr#define GPT_IR_ALL \ 89178825Sdfr (GPT_IR_ROV | \ 90178825Sdfr GPT_IR_IF2 | \ 91178825Sdfr GPT_IR_IF1 | \ 92178825Sdfr GPT_IR_OF3 | \ 93178825Sdfr GPT_IR_OF2 | \ 94178825Sdfr GPT_IR_OF1) 95233294Sstas 96233294Sstas#define IMX_GPT_OCR1 0x0010 /* Output Compare Register 1 R/W */ 97233294Sstas#define IMX_GPT_OCR2 0x0014 /* Output Compare Register 2 R/W */ 9872445Sassar#define IMX_GPT_OCR3 0x0018 /* Output Compare Register 3 R/W */ 9972445Sassar#define IMX_GPT_ICR1 0x001c /* Input capture Register 1 RO */ 10072445Sassar#define IMX_GPT_ICR2 0x0020 /* Input capture Register 2 RO */ 10172445Sassar#define IMX_GPT_CNT 0x0024 /* Counter Register RO */ 10272445Sassar