at91_machdep.c revision 266160
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * machdep.c 38 * 39 * Machine dependant functions for kernel setup 40 * 41 * This file needs a lot of work. 42 * 43 * Created : 17/09/94 44 */ 45 46#include <sys/cdefs.h> 47__FBSDID("$FreeBSD: stable/10/sys/arm/at91/at91_machdep.c 266160 2014-05-15 17:30:16Z ian $"); 48 49#define _ARM32_BUS_DMA_PRIVATE 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/sysproto.h> 53#include <sys/signalvar.h> 54#include <sys/imgact.h> 55#include <sys/kernel.h> 56#include <sys/ktr.h> 57#include <sys/linker.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/mutex.h> 61#include <sys/pcpu.h> 62#include <sys/proc.h> 63#include <sys/ptrace.h> 64#include <sys/cons.h> 65#include <sys/bio.h> 66#include <sys/bus.h> 67#include <sys/buf.h> 68#include <sys/exec.h> 69#include <sys/kdb.h> 70#include <sys/msgbuf.h> 71#include <machine/reg.h> 72#include <machine/cpu.h> 73#include <machine/board.h> 74 75#include <vm/vm.h> 76#include <vm/pmap.h> 77#include <vm/vm_object.h> 78#include <vm/vm_page.h> 79#include <vm/vm_map.h> 80#include <machine/devmap.h> 81#include <machine/vmparam.h> 82#include <machine/pcb.h> 83#include <machine/undefined.h> 84#include <machine/machdep.h> 85#include <machine/metadata.h> 86#include <machine/armreg.h> 87#include <machine/bus.h> 88#include <sys/reboot.h> 89 90#include <arm/at91/at91board.h> 91#include <arm/at91/at91var.h> 92#include <arm/at91/at91soc.h> 93#include <arm/at91/at91_usartreg.h> 94#include <arm/at91/at91rm92reg.h> 95#include <arm/at91/at91sam9g20reg.h> 96#include <arm/at91/at91sam9g45reg.h> 97 98#ifndef MAXCPU 99#define MAXCPU 1 100#endif 101 102/* Page table for mapping proc0 zero page */ 103#define KERNEL_PT_SYS 0 104#define KERNEL_PT_KERN 1 105#define KERNEL_PT_KERN_NUM 22 106/* L2 table for mapping after kernel */ 107#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM 108#define KERNEL_PT_AFKERNEL_NUM 5 109 110/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 111#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 112 113extern u_int data_abort_handler_address; 114extern u_int prefetch_abort_handler_address; 115extern u_int undefined_handler_address; 116 117struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 118 119/* Static device mappings. */ 120const struct arm_devmap_entry at91_devmap[] = { 121 /* 122 * Map the critical on-board devices. The interrupt vector at 123 * 0xffff0000 makes it impossible to map them PA == VA, so we map all 124 * 0xfffxxxxx addresses to 0xdffxxxxx. This covers all critical devices 125 * on all members of the AT91SAM9 and AT91RM9200 families. 126 */ 127 { 128 0xdff00000, 129 0xfff00000, 130 0x00100000, 131 VM_PROT_READ|VM_PROT_WRITE, 132 PTE_NOCACHE, 133 }, 134 /* There's a notion that we should do the rest of these lazily. */ 135 /* 136 * We can't just map the OHCI registers VA == PA, because 137 * AT91xx_xxx_BASE belongs to the userland address space. 138 * We could just choose a different virtual address, but a better 139 * solution would probably be to just use pmap_mapdev() to allocate 140 * KVA, as we don't need the OHCI controller before the vm 141 * initialization is done. However, the AT91 resource allocation 142 * system doesn't know how to use pmap_mapdev() yet. 143 * Care must be taken to ensure PA and VM address do not overlap 144 * between entries. 145 */ 146 { 147 /* 148 * Add the ohci controller, and anything else that might be 149 * on this chip select for a VA/PA mapping. 150 */ 151 /* Internal Memory 1MB */ 152 AT91RM92_OHCI_VA_BASE, 153 AT91RM92_OHCI_BASE, 154 0x00100000, 155 VM_PROT_READ|VM_PROT_WRITE, 156 PTE_NOCACHE, 157 }, 158 { 159 /* CompactFlash controller. Portion of EBI CS4 1MB */ 160 AT91RM92_CF_VA_BASE, 161 AT91RM92_CF_BASE, 162 0x00100000, 163 VM_PROT_READ|VM_PROT_WRITE, 164 PTE_NOCACHE, 165 }, 166 /* 167 * The next two should be good for the 9260, 9261 and 9G20 since 168 * addresses mapping is the same. 169 */ 170 { 171 /* Internal Memory 1MB */ 172 AT91SAM9G20_OHCI_VA_BASE, 173 AT91SAM9G20_OHCI_BASE, 174 0x00100000, 175 VM_PROT_READ|VM_PROT_WRITE, 176 PTE_NOCACHE, 177 }, 178 { 179 /* EBI CS3 256MB */ 180 AT91SAM9G20_NAND_VA_BASE, 181 AT91SAM9G20_NAND_BASE, 182 AT91SAM9G20_NAND_SIZE, 183 VM_PROT_READ|VM_PROT_WRITE, 184 PTE_NOCACHE, 185 }, 186 /* 187 * The next should be good for the 9G45. 188 */ 189 { 190 /* Internal Memory 1MB */ 191 AT91SAM9G45_OHCI_VA_BASE, 192 AT91SAM9G45_OHCI_BASE, 193 0x00100000, 194 VM_PROT_READ|VM_PROT_WRITE, 195 PTE_NOCACHE, 196 }, 197 { 0, 0, 0, 0, 0, } 198}; 199 200/* Physical and virtual addresses for some global pages */ 201 202vm_paddr_t phys_avail[10]; 203vm_paddr_t dump_avail[4]; 204 205struct pv_addr systempage; 206struct pv_addr msgbufpv; 207struct pv_addr irqstack; 208struct pv_addr undstack; 209struct pv_addr abtstack; 210struct pv_addr kernelstack; 211 212#ifdef LINUX_BOOT_ABI 213extern int membanks; 214extern int memstart[]; 215extern int memsize[]; 216#endif 217 218long 219at91_ramsize(void) 220{ 221 uint32_t cr, mdr, mr, *SDRAMC; 222 int banks, rows, cols, bw; 223#ifdef LINUX_BOOT_ABI 224 /* 225 * If we found any ATAGs that were for memory, return the first bank. 226 */ 227 if (membanks > 0) 228 return (memsize[0]); 229#endif 230 231 if (at91_is_rm92()) { 232 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE); 233 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4]; 234 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4]; 235 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1; 236 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11; 237 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8; 238 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2; 239 } else if (at91_cpu_is(AT91_T_SAM9G45)) { 240 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE); 241 cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4]; 242 mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4]; 243 banks = 0; 244 rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11; 245 cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8; 246 bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2; 247 248 /* Fix the calculation for DDR memory */ 249 mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK; 250 if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 || 251 mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) { 252 /* The cols value is 1 higher for DDR */ 253 cols += 1; 254 /* DDR has 4 internal banks. */ 255 banks = 2; 256 } 257 } else { 258 /* 259 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25 260 * as addresses and registers are the same. 261 */ 262 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE); 263 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4]; 264 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4]; 265 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1; 266 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11; 267 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8; 268 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2; 269 } 270 271 return (1 << (cols + rows + banks + bw)); 272} 273 274static const char *soc_type_name[] = { 275 [AT91_T_CAP9] = "at91cap9", 276 [AT91_T_RM9200] = "at91rm9200", 277 [AT91_T_SAM9260] = "at91sam9260", 278 [AT91_T_SAM9261] = "at91sam9261", 279 [AT91_T_SAM9263] = "at91sam9263", 280 [AT91_T_SAM9G10] = "at91sam9g10", 281 [AT91_T_SAM9G20] = "at91sam9g20", 282 [AT91_T_SAM9G45] = "at91sam9g45", 283 [AT91_T_SAM9N12] = "at91sam9n12", 284 [AT91_T_SAM9RL] = "at91sam9rl", 285 [AT91_T_SAM9X5] = "at91sam9x5", 286 [AT91_T_NONE] = "UNKNOWN" 287}; 288 289static const char *soc_subtype_name[] = { 290 [AT91_ST_NONE] = "UNKNOWN", 291 [AT91_ST_RM9200_BGA] = "at91rm9200_bga", 292 [AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp", 293 [AT91_ST_SAM9XE] = "at91sam9xe", 294 [AT91_ST_SAM9G45] = "at91sam9g45", 295 [AT91_ST_SAM9M10] = "at91sam9m10", 296 [AT91_ST_SAM9G46] = "at91sam9g46", 297 [AT91_ST_SAM9M11] = "at91sam9m11", 298 [AT91_ST_SAM9G15] = "at91sam9g15", 299 [AT91_ST_SAM9G25] = "at91sam9g25", 300 [AT91_ST_SAM9G35] = "at91sam9g35", 301 [AT91_ST_SAM9X25] = "at91sam9x25", 302 [AT91_ST_SAM9X35] = "at91sam9x35", 303}; 304 305struct at91_soc_info soc_info; 306 307/* 308 * Read the SoC ID from the CIDR register and try to match it against the 309 * values we know. If we find a good one, we return true. If not, we 310 * return false. When we find a good one, we also find the subtype 311 * and CPU family. 312 */ 313static int 314at91_try_id(uint32_t dbgu_base) 315{ 316 uint32_t socid; 317 318 soc_info.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base + 319 DBGU_C1R); 320 socid = soc_info.cidr & ~AT91_CPU_VERSION_MASK; 321 322 soc_info.type = AT91_T_NONE; 323 soc_info.subtype = AT91_ST_NONE; 324 soc_info.family = (soc_info.cidr & AT91_CPU_FAMILY_MASK) >> 20; 325 soc_info.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base + 326 DBGU_C2R); 327 328 switch (socid) { 329 case AT91_CPU_CAP9: 330 soc_info.type = AT91_T_CAP9; 331 break; 332 case AT91_CPU_RM9200: 333 soc_info.type = AT91_T_RM9200; 334 break; 335 case AT91_CPU_SAM9XE128: 336 case AT91_CPU_SAM9XE256: 337 case AT91_CPU_SAM9XE512: 338 case AT91_CPU_SAM9260: 339 soc_info.type = AT91_T_SAM9260; 340 if (soc_info.family == AT91_FAMILY_SAM9XE) 341 soc_info.subtype = AT91_ST_SAM9XE; 342 break; 343 case AT91_CPU_SAM9261: 344 soc_info.type = AT91_T_SAM9261; 345 break; 346 case AT91_CPU_SAM9263: 347 soc_info.type = AT91_T_SAM9263; 348 break; 349 case AT91_CPU_SAM9G10: 350 soc_info.type = AT91_T_SAM9G10; 351 break; 352 case AT91_CPU_SAM9G20: 353 soc_info.type = AT91_T_SAM9G20; 354 break; 355 case AT91_CPU_SAM9G45: 356 soc_info.type = AT91_T_SAM9G45; 357 break; 358 case AT91_CPU_SAM9N12: 359 soc_info.type = AT91_T_SAM9N12; 360 break; 361 case AT91_CPU_SAM9RL64: 362 soc_info.type = AT91_T_SAM9RL; 363 break; 364 case AT91_CPU_SAM9X5: 365 soc_info.type = AT91_T_SAM9X5; 366 break; 367 default: 368 return (0); 369 } 370 371 switch (soc_info.type) { 372 case AT91_T_SAM9G45: 373 switch (soc_info.exid) { 374 case AT91_EXID_SAM9G45: 375 soc_info.subtype = AT91_ST_SAM9G45; 376 break; 377 case AT91_EXID_SAM9G46: 378 soc_info.subtype = AT91_ST_SAM9G46; 379 break; 380 case AT91_EXID_SAM9M10: 381 soc_info.subtype = AT91_ST_SAM9M10; 382 break; 383 case AT91_EXID_SAM9M11: 384 soc_info.subtype = AT91_ST_SAM9M11; 385 break; 386 } 387 break; 388 case AT91_T_SAM9X5: 389 switch (soc_info.exid) { 390 case AT91_EXID_SAM9G15: 391 soc_info.subtype = AT91_ST_SAM9G15; 392 break; 393 case AT91_EXID_SAM9G25: 394 soc_info.subtype = AT91_ST_SAM9G25; 395 break; 396 case AT91_EXID_SAM9G35: 397 soc_info.subtype = AT91_ST_SAM9G35; 398 break; 399 case AT91_EXID_SAM9X25: 400 soc_info.subtype = AT91_ST_SAM9X25; 401 break; 402 case AT91_EXID_SAM9X35: 403 soc_info.subtype = AT91_ST_SAM9X35; 404 break; 405 } 406 break; 407 default: 408 break; 409 } 410 /* 411 * Disable interrupts in the DBGU unit... 412 */ 413 *(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff; 414 415 /* 416 * Save the name for later... 417 */ 418 snprintf(soc_info.name, sizeof(soc_info.name), "%s%s%s", 419 soc_type_name[soc_info.type], 420 soc_info.subtype == AT91_ST_NONE ? "" : " subtype ", 421 soc_info.subtype == AT91_ST_NONE ? "" : 422 soc_subtype_name[soc_info.subtype]); 423 424 /* 425 * try to get the matching CPU support. 426 */ 427 soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype); 428 soc_info.dbgu_base = AT91_BASE + dbgu_base; 429 430 return (1); 431} 432 433static void 434at91_soc_id(void) 435{ 436 437 if (!at91_try_id(AT91_DBGU0)) 438 at91_try_id(AT91_DBGU1); 439} 440 441#ifdef ARM_MANY_BOARD 442/* likely belongs in arm/arm/machdep.c, but since board_init is still at91 only... */ 443SET_DECLARE(arm_board_set, const struct arm_board); 444 445/* Not yet fully functional, but enough to build ATMEL config */ 446static long 447board_init(void) 448{ 449 return -1; 450} 451#endif 452 453void * 454initarm(struct arm_boot_params *abp) 455{ 456 struct pv_addr kernel_l1pt; 457 struct pv_addr dpcpu; 458 int i; 459 u_int l1pagetable; 460 vm_offset_t freemempos; 461 vm_offset_t afterkern; 462 uint32_t memsize; 463 vm_offset_t lastaddr; 464 465 lastaddr = parse_boot_param(abp); 466 set_cpufuncs(); 467 pcpu0_init(); 468 469 /* Do basic tuning, hz etc */ 470 init_param1(); 471 472 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; 473 /* Define a macro to simplify memory allocation */ 474#define valloc_pages(var, np) \ 475 alloc_pages((var).pv_va, (np)); \ 476 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR); 477 478#define alloc_pages(var, np) \ 479 (var) = freemempos; \ 480 freemempos += (np * PAGE_SIZE); \ 481 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 482 483 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 484 freemempos += PAGE_SIZE; 485 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 486 for (i = 0; i < NUM_KERNEL_PTS; ++i) { 487 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 488 valloc_pages(kernel_pt_table[i], 489 L2_TABLE_SIZE / PAGE_SIZE); 490 } else { 491 kernel_pt_table[i].pv_va = freemempos - 492 (i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 493 L2_TABLE_SIZE_REAL; 494 kernel_pt_table[i].pv_pa = 495 kernel_pt_table[i].pv_va - KERNVIRTADDR + 496 KERNPHYSADDR; 497 } 498 } 499 /* 500 * Allocate a page for the system page mapped to 0x00000000 501 * or 0xffff0000. This page will just contain the system vectors 502 * and can be shared by all processes. 503 */ 504 valloc_pages(systempage, 1); 505 506 /* Allocate dynamic per-cpu area. */ 507 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 508 dpcpu_init((void *)dpcpu.pv_va, 0); 509 510 /* Allocate stacks for all modes */ 511 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU); 512 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU); 513 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU); 514 valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU); 515 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 516 517 /* 518 * Now we start construction of the L1 page table 519 * We start by mapping the L2 page tables into the L1. 520 * This means that we can replace L1 mappings later on if necessary 521 */ 522 l1pagetable = kernel_l1pt.pv_va; 523 524 /* Map the L2 pages tables in the L1 page table */ 525 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, 526 &kernel_pt_table[KERNEL_PT_SYS]); 527 for (i = 0; i < KERNEL_PT_KERN_NUM; i++) 528 pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE, 529 &kernel_pt_table[KERNEL_PT_KERN + i]); 530 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 531 (((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1), 532 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 533 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1)); 534 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 535 pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE, 536 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 537 } 538 539 /* Map the vector page. */ 540 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 541 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 542 543 /* Map the DPCPU pages */ 544 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE, 545 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 546 547 /* Map the stack pages */ 548 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, 549 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 550 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, 551 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 552 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, 553 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 554 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, 555 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 556 557 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 558 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 559 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa, 560 msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 561 562 for (i = 0; i < NUM_KERNEL_PTS; ++i) { 563 pmap_map_chunk(l1pagetable, kernel_pt_table[i].pv_va, 564 kernel_pt_table[i].pv_pa, L2_TABLE_SIZE, 565 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 566 } 567 568 arm_devmap_bootstrap(l1pagetable, at91_devmap); 569 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT); 570 setttb(kernel_l1pt.pv_pa); 571 cpu_tlb_flushID(); 572 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); 573 574 at91_soc_id(); 575 576 /* 577 * Initialize all the clocks, so that the console can work. We can only 578 * do this if at91_soc_id() was able to fill in the support data. Even 579 * if we can't init the clocks, still try to do a console init so we can 580 * try to print the error message about missing soc support. There's a 581 * chance the printf will work if the bootloader set up the DBGU. 582 */ 583 if (soc_info.soc_data != NULL) { 584 soc_info.soc_data->soc_clock_init(); 585 at91_pmc_init_clock(); 586 } 587 588 cninit(); 589 590 if (soc_info.soc_data == NULL) 591 printf("Warning: No soc support for %s found.\n", soc_info.name); 592 593 memsize = board_init(); 594 physmem = memsize / PAGE_SIZE; 595 596 /* 597 * Pages were allocated during the secondary bootstrap for the 598 * stacks for different CPU modes. 599 * We must now set the r13 registers in the different CPU modes to 600 * point to these stacks. 601 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 602 * of the stack memory. 603 */ 604 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); 605 cpu_setup(""); 606 607 set_stackptrs(0); 608 609 /* 610 * We must now clean the cache again.... 611 * Cleaning may be done by reading new data to displace any 612 * dirty data in the cache. This will have happened in setttb() 613 * but since we are boot strapping the addresses used for the read 614 * may have just been remapped and thus the cache could be out 615 * of sync. A re-clean after the switch will cure this. 616 * After booting there are no gross relocations of the kernel thus 617 * this problem will not occur after initarm(). 618 */ 619 cpu_idcache_wbinv_all(); 620 621 /* Set stack for exception handlers */ 622 623 data_abort_handler_address = (u_int)data_abort_handler; 624 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 625 undefined_handler_address = (u_int)undefinedinstruction_bounce; 626 undefined_init(); 627 628 init_proc0(kernelstack.pv_va); 629 630 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 631 632 pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1); 633 arm_dump_avail_init(abp->abp_physaddr, memsize, 634 sizeof(dump_avail)/sizeof(dump_avail[0])); 635 /* Always use the 256MB of KVA we have available between the kernel and devices */ 636 vm_max_kernel_address = KERNVIRTADDR + (256 << 20); 637 pmap_bootstrap(freemempos, &kernel_l1pt); 638 msgbufp = (void*)msgbufpv.pv_va; 639 msgbufinit(msgbufp, msgbufsize); 640 mutex_init(); 641 642 i = 0; 643#if PHYSADDR != KERNPHYSADDR 644 phys_avail[i++] = PHYSADDR; 645 phys_avail[i++] = KERNPHYSADDR; 646#endif 647 phys_avail[i++] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR; 648 phys_avail[i++] = PHYSADDR + memsize; 649 phys_avail[i++] = 0; 650 phys_avail[i++] = 0; 651 init_param2(physmem); 652 kdb_init(); 653 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 654 sizeof(struct pcb))); 655} 656 657/* 658 * These functions are handled elsewhere, so make them nops here. 659 */ 660void 661cpu_startprofclock(void) 662{ 663 664} 665 666void 667cpu_stopprofclock(void) 668{ 669 670} 671 672void 673cpu_initclocks(void) 674{ 675 676} 677 678void 679DELAY(int n) 680{ 681 682 if (soc_info.soc_data) 683 soc_info.soc_data->soc_delay(n); 684} 685 686void 687cpu_reset(void) 688{ 689 690 if (soc_info.soc_data) 691 soc_info.soc_data->soc_reset(); 692 while (1) 693 continue; 694} 695