uart_dev_lpc.c revision 266084
1161648Smjacob/*- 2161648Smjacob * Copyright (c) 2003 Marcel Moolenaar 3161648Smjacob * All rights reserved. 4161648Smjacob * 5161648Smjacob * Redistribution and use in source and binary forms, with or without 6161648Smjacob * modification, are permitted provided that the following conditions 7161648Smjacob * are met: 8161648Smjacob * 9161648Smjacob * 1. Redistributions of source code must retain the above copyright 10161648Smjacob * notice, this list of conditions and the following disclaimer. 11161648Smjacob * 2. Redistributions in binary form must reproduce the above copyright 12161648Smjacob * notice, this list of conditions and the following disclaimer in the 13161648Smjacob * documentation and/or other materials provided with the distribution. 14161648Smjacob * 15161648Smjacob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16161648Smjacob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17161648Smjacob * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18161648Smjacob * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19161648Smjacob * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20161648Smjacob * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21161648Smjacob * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22161648Smjacob * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23161648Smjacob * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24161648Smjacob * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25161648Smjacob */ 26161648Smjacob 27161648Smjacob#include <sys/cdefs.h> 28161648Smjacob__FBSDID("$FreeBSD: stable/10/sys/dev/uart/uart_dev_lpc.c 266084 2014-05-14 19:18:58Z ian $"); 29161648Smjacob 30161648Smjacob#include <sys/param.h> 31161648Smjacob#include <sys/systm.h> 32161648Smjacob#include <sys/bus.h> 33161648Smjacob#include <sys/conf.h> 34161648Smjacob#include <machine/bus.h> 35161648Smjacob#include <machine/fdt.h> 36161648Smjacob 37#include <dev/uart/uart.h> 38#include <dev/uart/uart_cpu.h> 39#include <dev/uart/uart_bus.h> 40 41#include <dev/ic/ns16550.h> 42#include <arm/lpc/lpcreg.h> 43 44#include "uart_if.h" 45 46#define DEFAULT_RCLK (13 * 1000 * 1000) 47 48static bus_space_handle_t bsh_clkpwr; 49 50#define lpc_ns8250_get_clkreg(_bas, _reg) \ 51 bus_space_read_4(fdtbus_bs_tag, bsh_clkpwr, (_reg)) 52#define lpc_ns8250_set_clkreg(_bas, _reg, _val) \ 53 bus_space_write_4(fdtbus_bs_tag, bsh_clkpwr, (_reg), (_val)) 54 55/* 56 * Clear pending interrupts. THRE is cleared by reading IIR. Data 57 * that may have been received gets lost here. 58 */ 59static void 60lpc_ns8250_clrint(struct uart_bas *bas) 61{ 62 uint8_t iir, lsr; 63 64 iir = uart_getreg(bas, REG_IIR); 65 while ((iir & IIR_NOPEND) == 0) { 66 iir &= IIR_IMASK; 67 if (iir == IIR_RLS) { 68 lsr = uart_getreg(bas, REG_LSR); 69 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 70 (void)uart_getreg(bas, REG_DATA); 71 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 72 (void)uart_getreg(bas, REG_DATA); 73 else if (iir == IIR_MLSC) 74 (void)uart_getreg(bas, REG_MSR); 75 uart_barrier(bas); 76 iir = uart_getreg(bas, REG_IIR); 77 } 78} 79 80static int 81lpc_ns8250_delay(struct uart_bas *bas) 82{ 83 uint32_t uclk; 84 int x, y; 85 86 uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK); 87 88 x = (uclk >> 8) & 0xff; 89 y = uclk & 0xff; 90 91 return (16000000 / (bas->rclk * x / y)); 92} 93 94static void 95lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y) 96{ 97 98 switch (baudrate) { 99 case 2400: 100 *x = 1; 101 *y = 255; 102 return; 103 case 4800: 104 *x = 1; 105 *y = 169; 106 return; 107 case 9600: 108 *x = 3; 109 *y = 254; 110 return; 111 case 19200: 112 *x = 3; 113 *y = 127; 114 return; 115 case 38400: 116 *x = 6; 117 *y = 127; 118 return; 119 case 57600: 120 *x = 9; 121 *y = 127; 122 return; 123 default: 124 case 115200: 125 *x = 19; 126 *y = 134; 127 return; 128 case 230400: 129 *x = 19; 130 *y = 67; 131 return; 132 case 460800: 133 *x = 38; 134 *y = 67; 135 return; 136 } 137} 138 139static int 140lpc_ns8250_drain(struct uart_bas *bas, int what) 141{ 142 int delay, limit; 143 144 delay = lpc_ns8250_delay(bas); 145 146 if (what & UART_DRAIN_TRANSMITTER) { 147 /* 148 * Pick an arbitrary high limit to avoid getting stuck in 149 * an infinite loop when the hardware is broken. Make the 150 * limit high enough to handle large FIFOs. 151 */ 152 limit = 10*1024; 153 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 154 DELAY(delay); 155 if (limit == 0) { 156 /* printf("lpc_ns8250: transmitter appears stuck... "); */ 157 return (EIO); 158 } 159 } 160 161 if (what & UART_DRAIN_RECEIVER) { 162 /* 163 * Pick an arbitrary high limit to avoid getting stuck in 164 * an infinite loop when the hardware is broken. Make the 165 * limit high enough to handle large FIFOs and integrated 166 * UARTs. The HP rx2600 for example has 3 UARTs on the 167 * management board that tend to get a lot of data send 168 * to it when the UART is first activated. 169 */ 170 limit=10*4096; 171 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 172 (void)uart_getreg(bas, REG_DATA); 173 uart_barrier(bas); 174 DELAY(delay << 2); 175 } 176 if (limit == 0) { 177 /* printf("lpc_ns8250: receiver appears broken... "); */ 178 return (EIO); 179 } 180 } 181 182 return (0); 183} 184 185/* 186 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 187 * drained. WARNING: this function clobbers the FIFO setting! 188 */ 189static void 190lpc_ns8250_flush(struct uart_bas *bas, int what) 191{ 192 uint8_t fcr; 193 194 fcr = FCR_ENABLE; 195 if (what & UART_FLUSH_TRANSMITTER) 196 fcr |= FCR_XMT_RST; 197 if (what & UART_FLUSH_RECEIVER) 198 fcr |= FCR_RCV_RST; 199 uart_setreg(bas, REG_FCR, fcr); 200 uart_barrier(bas); 201} 202 203static int 204lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 205 int parity) 206{ 207 int xdiv, ydiv; 208 uint8_t lcr; 209 210 lcr = 0; 211 if (databits >= 8) 212 lcr |= LCR_8BITS; 213 else if (databits == 7) 214 lcr |= LCR_7BITS; 215 else if (databits == 6) 216 lcr |= LCR_6BITS; 217 else 218 lcr |= LCR_5BITS; 219 if (stopbits > 1) 220 lcr |= LCR_STOPB; 221 lcr |= parity << 3; 222 223 /* Set baudrate. */ 224 if (baudrate > 0) { 225 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 226 uart_barrier(bas); 227 uart_setreg(bas, REG_DLL, 0x00); 228 uart_setreg(bas, REG_DLH, 0x00); 229 uart_barrier(bas); 230 231 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv); 232 lpc_ns8250_set_clkreg(bas, 233 LPC_CLKPWR_UART_U5CLK, 234 LPC_CLKPWR_UART_UCLK_X(xdiv) | 235 LPC_CLKPWR_UART_UCLK_Y(ydiv)); 236 } 237 238 /* Set LCR and clear DLAB. */ 239 uart_setreg(bas, REG_LCR, lcr); 240 uart_barrier(bas); 241 return (0); 242} 243 244/* 245 * Low-level UART interface. 246 */ 247static int lpc_ns8250_probe(struct uart_bas *bas); 248static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int); 249static void lpc_ns8250_term(struct uart_bas *bas); 250static void lpc_ns8250_putc(struct uart_bas *bas, int); 251static int lpc_ns8250_rxready(struct uart_bas *bas); 252static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *); 253 254static struct uart_ops uart_lpc_ns8250_ops = { 255 .probe = lpc_ns8250_probe, 256 .init = lpc_ns8250_init, 257 .term = lpc_ns8250_term, 258 .putc = lpc_ns8250_putc, 259 .rxready = lpc_ns8250_rxready, 260 .getc = lpc_ns8250_getc, 261}; 262 263static int 264lpc_ns8250_probe(struct uart_bas *bas) 265{ 266#if 0 267 u_char val; 268 269 /* Check known 0 bits that don't depend on DLAB. */ 270 val = uart_getreg(bas, REG_IIR); 271 if (val & 0x30) 272 return (ENXIO); 273 /* 274 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 275 * chip, but otherwise doesn't seem to have a function. In 276 * other words, uart(4) works regardless. Ignore that bit so 277 * the probe succeeds. 278 */ 279 val = uart_getreg(bas, REG_MCR); 280 if (val & 0xa0) 281 return (ENXIO); 282#endif 283 return (0); 284} 285 286static void 287lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 288 int parity) 289{ 290 u_char ier; 291 u_long clkmode; 292 293 /* Enable UART clock */ 294 bus_space_map(fdtbus_bs_tag, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, 295 &bsh_clkpwr); 296 clkmode = lpc_ns8250_get_clkreg(bas, LPC_UART_CLKMODE); 297 lpc_ns8250_set_clkreg(bas, LPC_UART_CLKMODE, clkmode | 298 LPC_UART_CLKMODE_UART5(1)); 299 300#if 0 301 /* Work around H/W bug */ 302 uart_setreg(bas, REG_DATA, 0x00); 303#endif 304 if (bas->rclk == 0) 305 bas->rclk = DEFAULT_RCLK; 306 lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); 307 308 /* Disable all interrupt sources. */ 309 /* 310 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 311 * UARTs split the receive time-out interrupt bit out separately as 312 * 0x10. This gets handled by ier_mask and ier_rxbits below. 313 */ 314 ier = uart_getreg(bas, REG_IER) & 0xe0; 315 uart_setreg(bas, REG_IER, ier); 316 uart_barrier(bas); 317 318 /* Disable the FIFO (if present). */ 319 uart_setreg(bas, REG_FCR, 0); 320 uart_barrier(bas); 321 322 /* Set RTS & DTR. */ 323 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 324 uart_barrier(bas); 325 326 lpc_ns8250_clrint(bas); 327} 328 329static void 330lpc_ns8250_term(struct uart_bas *bas) 331{ 332 333 /* Clear RTS & DTR. */ 334 uart_setreg(bas, REG_MCR, MCR_IE); 335 uart_barrier(bas); 336} 337 338static void 339lpc_ns8250_putc(struct uart_bas *bas, int c) 340{ 341 int limit; 342 343 limit = 250000; 344 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 345 DELAY(4); 346 uart_setreg(bas, REG_DATA, c); 347 uart_barrier(bas); 348 limit = 250000; 349 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 350 DELAY(4); 351} 352 353static int 354lpc_ns8250_rxready(struct uart_bas *bas) 355{ 356 357 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 358} 359 360static int 361lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 362{ 363 int c; 364 365 uart_lock(hwmtx); 366 367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 368 uart_unlock(hwmtx); 369 DELAY(4); 370 uart_lock(hwmtx); 371 } 372 373 c = uart_getreg(bas, REG_DATA); 374 375 uart_unlock(hwmtx); 376 377 return (c); 378} 379 380/* 381 * High-level UART interface. 382 */ 383struct lpc_ns8250_softc { 384 struct uart_softc base; 385 uint8_t fcr; 386 uint8_t ier; 387 uint8_t mcr; 388 389 uint8_t ier_mask; 390 uint8_t ier_rxbits; 391}; 392 393static int lpc_ns8250_bus_attach(struct uart_softc *); 394static int lpc_ns8250_bus_detach(struct uart_softc *); 395static int lpc_ns8250_bus_flush(struct uart_softc *, int); 396static int lpc_ns8250_bus_getsig(struct uart_softc *); 397static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 398static int lpc_ns8250_bus_ipend(struct uart_softc *); 399static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int); 400static int lpc_ns8250_bus_probe(struct uart_softc *); 401static int lpc_ns8250_bus_receive(struct uart_softc *); 402static int lpc_ns8250_bus_setsig(struct uart_softc *, int); 403static int lpc_ns8250_bus_transmit(struct uart_softc *); 404static void lpc_ns8250_bus_grab(struct uart_softc *); 405static void lpc_ns8250_bus_ungrab(struct uart_softc *); 406 407static kobj_method_t lpc_ns8250_methods[] = { 408 KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach), 409 KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach), 410 KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush), 411 KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig), 412 KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl), 413 KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend), 414 KOBJMETHOD(uart_param, lpc_ns8250_bus_param), 415 KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe), 416 KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive), 417 KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig), 418 KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit), 419 KOBJMETHOD(uart_grab, lpc_ns8250_bus_grab), 420 KOBJMETHOD(uart_ungrab, lpc_ns8250_bus_ungrab), 421 { 0, 0 } 422}; 423 424struct uart_class uart_lpc_class = { 425 "lpc_ns8250", 426 lpc_ns8250_methods, 427 sizeof(struct lpc_ns8250_softc), 428 .uc_ops = &uart_lpc_ns8250_ops, 429 .uc_range = 8, 430 .uc_rclk = DEFAULT_RCLK 431}; 432 433#define SIGCHG(c, i, s, d) \ 434 if (c) { \ 435 i |= (i & s) ? s : s | d; \ 436 } else { \ 437 i = (i & s) ? (i & ~s) | d : i; \ 438 } 439 440static int 441lpc_ns8250_bus_attach(struct uart_softc *sc) 442{ 443 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 444 struct uart_bas *bas; 445 unsigned int ivar; 446 447 bas = &sc->sc_bas; 448 449 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR); 450 lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA; 451 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 452 &ivar)) { 453 if (UART_FLAGS_FCR_RX_LOW(ivar)) 454 lpc_ns8250->fcr |= FCR_RX_LOW; 455 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 456 lpc_ns8250->fcr |= FCR_RX_MEDL; 457 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 458 lpc_ns8250->fcr |= FCR_RX_HIGH; 459 else 460 lpc_ns8250->fcr |= FCR_RX_MEDH; 461 } else 462 lpc_ns8250->fcr |= FCR_RX_HIGH; 463 464 /* Get IER mask */ 465 ivar = 0xf0; 466 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 467 &ivar); 468 lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff); 469 470 /* Get IER RX interrupt bits */ 471 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 472 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 473 &ivar); 474 lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 475 476 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); 477 uart_barrier(bas); 478 lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 479 480 if (lpc_ns8250->mcr & MCR_DTR) 481 sc->sc_hwsig |= SER_DTR; 482 if (lpc_ns8250->mcr & MCR_RTS) 483 sc->sc_hwsig |= SER_RTS; 484 lpc_ns8250_bus_getsig(sc); 485 486 lpc_ns8250_clrint(bas); 487 lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; 488 lpc_ns8250->ier |= lpc_ns8250->ier_rxbits; 489 uart_setreg(bas, REG_IER, lpc_ns8250->ier); 490 uart_barrier(bas); 491 492 return (0); 493} 494 495static int 496lpc_ns8250_bus_detach(struct uart_softc *sc) 497{ 498 struct lpc_ns8250_softc *lpc_ns8250; 499 struct uart_bas *bas; 500 u_char ier; 501 502 lpc_ns8250 = (struct lpc_ns8250_softc *)sc; 503 bas = &sc->sc_bas; 504 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; 505 uart_setreg(bas, REG_IER, ier); 506 uart_barrier(bas); 507 lpc_ns8250_clrint(bas); 508 return (0); 509} 510 511static int 512lpc_ns8250_bus_flush(struct uart_softc *sc, int what) 513{ 514 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 515 struct uart_bas *bas; 516 int error; 517 518 bas = &sc->sc_bas; 519 uart_lock(sc->sc_hwmtx); 520 if (sc->sc_rxfifosz > 1) { 521 lpc_ns8250_flush(bas, what); 522 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); 523 uart_barrier(bas); 524 error = 0; 525 } else 526 error = lpc_ns8250_drain(bas, what); 527 uart_unlock(sc->sc_hwmtx); 528 return (error); 529} 530 531static int 532lpc_ns8250_bus_getsig(struct uart_softc *sc) 533{ 534 uint32_t new, old, sig; 535 uint8_t msr; 536 537 do { 538 old = sc->sc_hwsig; 539 sig = old; 540 uart_lock(sc->sc_hwmtx); 541 msr = uart_getreg(&sc->sc_bas, REG_MSR); 542 uart_unlock(sc->sc_hwmtx); 543 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 544 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 545 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 546 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 547 new = sig & ~SER_MASK_DELTA; 548 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 549 return (sig); 550} 551 552static int 553lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 554{ 555 struct uart_bas *bas; 556 int baudrate, divisor, error; 557 uint8_t efr, lcr; 558 559 bas = &sc->sc_bas; 560 error = 0; 561 uart_lock(sc->sc_hwmtx); 562 switch (request) { 563 case UART_IOCTL_BREAK: 564 lcr = uart_getreg(bas, REG_LCR); 565 if (data) 566 lcr |= LCR_SBREAK; 567 else 568 lcr &= ~LCR_SBREAK; 569 uart_setreg(bas, REG_LCR, lcr); 570 uart_barrier(bas); 571 break; 572 case UART_IOCTL_IFLOW: 573 lcr = uart_getreg(bas, REG_LCR); 574 uart_barrier(bas); 575 uart_setreg(bas, REG_LCR, 0xbf); 576 uart_barrier(bas); 577 efr = uart_getreg(bas, REG_EFR); 578 if (data) 579 efr |= EFR_RTS; 580 else 581 efr &= ~EFR_RTS; 582 uart_setreg(bas, REG_EFR, efr); 583 uart_barrier(bas); 584 uart_setreg(bas, REG_LCR, lcr); 585 uart_barrier(bas); 586 break; 587 case UART_IOCTL_OFLOW: 588 lcr = uart_getreg(bas, REG_LCR); 589 uart_barrier(bas); 590 uart_setreg(bas, REG_LCR, 0xbf); 591 uart_barrier(bas); 592 efr = uart_getreg(bas, REG_EFR); 593 if (data) 594 efr |= EFR_CTS; 595 else 596 efr &= ~EFR_CTS; 597 uart_setreg(bas, REG_EFR, efr); 598 uart_barrier(bas); 599 uart_setreg(bas, REG_LCR, lcr); 600 uart_barrier(bas); 601 break; 602 case UART_IOCTL_BAUD: 603 lcr = uart_getreg(bas, REG_LCR); 604 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 605 uart_barrier(bas); 606 divisor = uart_getreg(bas, REG_DLL) | 607 (uart_getreg(bas, REG_DLH) << 8); 608 uart_barrier(bas); 609 uart_setreg(bas, REG_LCR, lcr); 610 uart_barrier(bas); 611 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 612 if (baudrate > 0) 613 *(int*)data = baudrate; 614 else 615 error = ENXIO; 616 break; 617 default: 618 error = EINVAL; 619 break; 620 } 621 uart_unlock(sc->sc_hwmtx); 622 return (error); 623} 624 625static int 626lpc_ns8250_bus_ipend(struct uart_softc *sc) 627{ 628 struct uart_bas *bas; 629 struct lpc_ns8250_softc *lpc_ns8250; 630 int ipend; 631 uint8_t iir, lsr; 632 633 lpc_ns8250 = (struct lpc_ns8250_softc *)sc; 634 bas = &sc->sc_bas; 635 uart_lock(sc->sc_hwmtx); 636 iir = uart_getreg(bas, REG_IIR); 637 if (iir & IIR_NOPEND) { 638 uart_unlock(sc->sc_hwmtx); 639 return (0); 640 } 641 ipend = 0; 642 if (iir & IIR_RXRDY) { 643 lsr = uart_getreg(bas, REG_LSR); 644 if (lsr & LSR_OE) 645 ipend |= SER_INT_OVERRUN; 646 if (lsr & LSR_BI) 647 ipend |= SER_INT_BREAK; 648 if (lsr & LSR_RXRDY) 649 ipend |= SER_INT_RXREADY; 650 } else { 651 if (iir & IIR_TXRDY) { 652 ipend |= SER_INT_TXIDLE; 653 uart_setreg(bas, REG_IER, lpc_ns8250->ier); 654 } else 655 ipend |= SER_INT_SIGCHG; 656 } 657 if (ipend == 0) 658 lpc_ns8250_clrint(bas); 659 uart_unlock(sc->sc_hwmtx); 660 return (ipend); 661} 662 663static int 664lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 665 int stopbits, int parity) 666{ 667 struct uart_bas *bas; 668 int error; 669 670 bas = &sc->sc_bas; 671 uart_lock(sc->sc_hwmtx); 672 error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); 673 uart_unlock(sc->sc_hwmtx); 674 return (error); 675} 676 677static int 678lpc_ns8250_bus_probe(struct uart_softc *sc) 679{ 680 struct lpc_ns8250_softc *lpc_ns8250; 681 struct uart_bas *bas; 682 int count, delay, error, limit; 683 uint8_t lsr, mcr, ier; 684 685 lpc_ns8250 = (struct lpc_ns8250_softc *)sc; 686 bas = &sc->sc_bas; 687 688 error = lpc_ns8250_probe(bas); 689 if (error) 690 return (error); 691 692 mcr = MCR_IE; 693 if (sc->sc_sysdev == NULL) { 694 /* By using lpc_ns8250_init() we also set DTR and RTS. */ 695 lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 696 } else 697 mcr |= MCR_DTR | MCR_RTS; 698 699 error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 700 if (error) 701 return (error); 702 703 /* 704 * Set loopback mode. This avoids having garbage on the wire and 705 * also allows us send and receive data. We set DTR and RTS to 706 * avoid the possibility that automatic flow-control prevents 707 * any data from being sent. 708 */ 709 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 710 uart_barrier(bas); 711 712 /* 713 * Enable FIFOs. And check that the UART has them. If not, we're 714 * done. Since this is the first time we enable the FIFOs, we reset 715 * them. 716 */ 717 uart_setreg(bas, REG_FCR, FCR_ENABLE); 718 uart_barrier(bas); 719 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 720 /* 721 * NS16450 or INS8250. We don't bother to differentiate 722 * between them. They're too old to be interesting. 723 */ 724 uart_setreg(bas, REG_MCR, mcr); 725 uart_barrier(bas); 726 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 727 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 728 return (0); 729 } 730 731 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 732 uart_barrier(bas); 733 734 count = 0; 735 delay = lpc_ns8250_delay(bas); 736 737 /* We have FIFOs. Drain the transmitter and receiver. */ 738 error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 739 if (error) { 740 uart_setreg(bas, REG_MCR, mcr); 741 uart_setreg(bas, REG_FCR, 0); 742 uart_barrier(bas); 743 goto done; 744 } 745 746 /* 747 * We should have a sufficiently clean "pipe" to determine the 748 * size of the FIFOs. We send as much characters as is reasonable 749 * and wait for the overflow bit in the LSR register to be 750 * asserted, counting the characters as we send them. Based on 751 * that count we know the FIFO size. 752 */ 753 do { 754 uart_setreg(bas, REG_DATA, 0); 755 uart_barrier(bas); 756 count++; 757 758 limit = 30; 759 lsr = 0; 760 /* 761 * LSR bits are cleared upon read, so we must accumulate 762 * them to be able to test LSR_OE below. 763 */ 764 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 765 --limit) 766 DELAY(delay); 767 if (limit == 0) { 768 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; 769 uart_setreg(bas, REG_IER, ier); 770 uart_setreg(bas, REG_MCR, mcr); 771 uart_setreg(bas, REG_FCR, 0); 772 uart_barrier(bas); 773 count = 0; 774 goto done; 775 } 776 } while ((lsr & LSR_OE) == 0 && count < 130); 777 count--; 778 779 uart_setreg(bas, REG_MCR, mcr); 780 781 /* Reset FIFOs. */ 782 lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 783 784done: 785 sc->sc_rxfifosz = 64; 786 device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs"); 787 788 /* 789 * Force the Tx FIFO size to 16 bytes for now. We don't program the 790 * Tx trigger. Also, we assume that all data has been sent when the 791 * interrupt happens. 792 */ 793 sc->sc_txfifosz = 16; 794 795#if 0 796 /* 797 * XXX there are some issues related to hardware flow control and 798 * it's likely that uart(4) is the cause. This basicly needs more 799 * investigation, but we avoid using for hardware flow control 800 * until then. 801 */ 802 /* 16650s or higher have automatic flow control. */ 803 if (sc->sc_rxfifosz > 16) { 804 sc->sc_hwiflow = 1; 805 sc->sc_hwoflow = 1; 806 } 807#endif 808 return (0); 809} 810 811static int 812lpc_ns8250_bus_receive(struct uart_softc *sc) 813{ 814 struct uart_bas *bas; 815 int xc; 816 uint8_t lsr; 817 818 bas = &sc->sc_bas; 819 uart_lock(sc->sc_hwmtx); 820 lsr = uart_getreg(bas, REG_LSR); 821 while (lsr & LSR_RXRDY) { 822 if (uart_rx_full(sc)) { 823 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 824 break; 825 } 826 xc = uart_getreg(bas, REG_DATA); 827 if (lsr & LSR_FE) 828 xc |= UART_STAT_FRAMERR; 829 if (lsr & LSR_PE) 830 xc |= UART_STAT_PARERR; 831 uart_rx_put(sc, xc); 832 lsr = uart_getreg(bas, REG_LSR); 833 } 834 /* Discard everything left in the Rx FIFO. */ 835 while (lsr & LSR_RXRDY) { 836 (void)uart_getreg(bas, REG_DATA); 837 uart_barrier(bas); 838 lsr = uart_getreg(bas, REG_LSR); 839 } 840 uart_unlock(sc->sc_hwmtx); 841 return (0); 842} 843 844static int 845lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig) 846{ 847 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 848 struct uart_bas *bas; 849 uint32_t new, old; 850 851 bas = &sc->sc_bas; 852 do { 853 old = sc->sc_hwsig; 854 new = old; 855 if (sig & SER_DDTR) { 856 SIGCHG(sig & SER_DTR, new, SER_DTR, 857 SER_DDTR); 858 } 859 if (sig & SER_DRTS) { 860 SIGCHG(sig & SER_RTS, new, SER_RTS, 861 SER_DRTS); 862 } 863 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 864 uart_lock(sc->sc_hwmtx); 865 lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 866 if (new & SER_DTR) 867 lpc_ns8250->mcr |= MCR_DTR; 868 if (new & SER_RTS) 869 lpc_ns8250->mcr |= MCR_RTS; 870 uart_setreg(bas, REG_MCR, lpc_ns8250->mcr); 871 uart_barrier(bas); 872 uart_unlock(sc->sc_hwmtx); 873 return (0); 874} 875 876static int 877lpc_ns8250_bus_transmit(struct uart_softc *sc) 878{ 879 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 880 struct uart_bas *bas; 881 int i; 882 883 bas = &sc->sc_bas; 884 uart_lock(sc->sc_hwmtx); 885 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 886 ; 887 uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY); 888 uart_barrier(bas); 889 for (i = 0; i < sc->sc_txdatasz; i++) { 890 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 891 uart_barrier(bas); 892 } 893 sc->sc_txbusy = 1; 894 uart_unlock(sc->sc_hwmtx); 895 return (0); 896} 897 898void 899lpc_ns8250_bus_grab(struct uart_softc *sc) 900{ 901 struct uart_bas *bas = &sc->sc_bas; 902 903 /* 904 * turn off all interrupts to enter polling mode. Leave the 905 * saved mask alone. We'll restore whatever it was in ungrab. 906 * All pending interupt signals are reset when IER is set to 0. 907 */ 908 uart_lock(sc->sc_hwmtx); 909 uart_setreg(bas, REG_IER, 0); 910 uart_barrier(bas); 911 uart_unlock(sc->sc_hwmtx); 912} 913 914void 915lpc_ns8250_bus_ungrab(struct uart_softc *sc) 916{ 917 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 918 struct uart_bas *bas = &sc->sc_bas; 919 920 /* 921 * Restore previous interrupt mask 922 */ 923 uart_lock(sc->sc_hwmtx); 924 uart_setreg(bas, REG_IER, lpc_ns8250->ier); 925 uart_barrier(bas); 926 uart_unlock(sc->sc_hwmtx); 927} 928