imx53x.dtsi revision 266365
1/* 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * Copyright (c) 2013 Rui Paulo 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf under sponsorship from 7 * the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Freescale i.MX535 Device Tree Source. 31 * 32 * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/imx53x.dtsi 266365 2014-05-17 22:00:10Z ian $ 33 */ 34 35/ { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 39 aliases { 40 soc = &SOC; 41 }; 42 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu@0 { 49 device_type = "cpu"; 50 compatible = "ARM,MCIMX535"; 51 reg = <0x0>; 52 d-cache-line-size = <32>; 53 i-cache-line-size = <32>; 54 d-cache-size = <0x8000>; 55 i-cache-size = <0x8000>; 56 l2-cache-line-size = <32>; 57 l2-cache-line = <0x40000>; 58 timebase-frequency = <0>; 59 bus-frequency = <0>; 60 clock-frequency = <0>; 61 }; 62 }; 63 64 localbus@0fffc000 { 65 compatible = "simple-bus"; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 /* This reflects CPU decode windows setup. */ 70 ranges; 71 72 tzic: tz-interrupt-controller@0fffc000 { 73 compatible = "fsl,imx53-tzic", "fsl,tzic"; 74 interrupt-controller; 75 #interrupt-cells = <1>; 76 reg = <0x0fffc000 0x00004000>; 77 }; 78 /* 79 * 40000000 40000FFF 4K Debug ROM 80 * 40001000 40001FFF 4K ETB 81 * 40002000 40002FFF 4K ETM 82 * 40003000 40003FFF 4K TPIU 83 * 40004000 40004FFF 4K CTI0 84 * 40005000 40005FFF 4K CTI1 85 * 40006000 40006FFF 4K CTI2 86 * 40007000 40007FFF 4K CTI3 87 * 40008000 40008FFF 4K ARM Debug Unit 88 * 89 * 0FFFC000 0FFFCFFF 0x4000 TZIC 90 */ 91 }; 92 93 SOC: soc@50000000 { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 interrupt-parent = <&tzic>; 98 ranges; 99 100 aips@50000000 { /* AIPS1 */ 101 compatible = "fsl,aips-bus", "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 interrupt-parent = <&tzic>; 105 ranges; 106 107 /* Required by many devices, so better to stay first */ 108 /* 53FD4000 0x4000 CCM */ 109 clock@53fd4000 { 110 compatible = "fsl,imx53-ccm"; 111 /* 63F80000 0x4000 DPLLIP1 */ 112 /* 63F84000 0x4000 DPLLIP2 */ 113 /* 63F88000 0x4000 DPLLIP3 */ 114 reg = <0x53fd4000 0x4000 115 0x63F80000 0x4000 116 0x63F84000 0x4000 117 0x63F88000 0x4000>; 118 interrupt-parent = <&tzic>; 119 interrupts = <71 72>; 120 status = "disabled"; 121 }; 122 123 /* 124 * GPIO modules moved up - to have it attached for 125 * drivers which rely on GPIO 126 */ 127 /* 53F84000 0x4000 GPIO1 */ 128 gpio1: gpio@53f84000 { 129 compatible = "fsl,imx53-gpio"; 130 reg = <0x53f84000 0x4000>; 131 interrupt-parent = <&tzic>; 132 interrupts = <50 51 42 43 44 45 46 47 48 49>; 133 /* TODO: use <> also */ 134 gpio-controller; 135 #gpio-cells = <2>; 136 interrupt-controller; 137 #interrupt-cells = <1>; 138 }; 139 140 /* 53F88000 0x4000 GPIO2 */ 141 gpio2: gpio@53f88000 { 142 compatible = "fsl,imx53-gpio"; 143 reg = <0x53f88000 0x4000>; 144 interrupt-parent = <&tzic>; 145 interrupts = <52 53>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 interrupt-controller; 149 #interrupt-cells = <1>; 150 }; 151 152 /* 53F8C000 0x4000 GPIO3 */ 153 gpio3: gpio@53f8c000 { 154 compatible = "fsl,imx53-gpio"; 155 reg = <0x53f8c000 0x4000>; 156 interrupt-parent = <&tzic>; 157 interrupts = <54 55>; 158 gpio-controller; 159 #gpio-cells = <2>; 160 interrupt-controller; 161 #interrupt-cells = <1>; 162 }; 163 164 /* 53F90000 0x4000 GPIO4 */ 165 gpio4: gpio@53f90000 { 166 compatible = "fsl,imx53-gpio"; 167 reg = <0x53f90000 0x4000>; 168 interrupt-parent = <&tzic>; 169 interrupts = <56 57>; 170 gpio-controller; 171 #gpio-cells = <2>; 172 interrupt-controller; 173 #interrupt-cells = <1>; 174 }; 175 176 /* 53FDC000 0x4000 GPIO5 */ 177 gpio5: gpio@53fdc000 { 178 compatible = "fsl,imx53-gpio"; 179 reg = <0x53fdc000 0x4000>; 180 interrupt-parent = <&tzic>; 181 interrupts = <103 104>; 182 gpio-controller; 183 #gpio-cells = <2>; 184 interrupt-controller; 185 #interrupt-cells = <1>; 186 }; 187 188 /* 53FE0000 0x4000 GPIO6 */ 189 gpio6: gpio@53fe0000 { 190 compatible = "fsl,imx53-gpio"; 191 reg = <0x53fe0000 0x4000>; 192 interrupt-parent = <&tzic>; 193 interrupts = <105 106>; 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-controller; 197 #interrupt-cells = <1>; 198 }; 199 200 /* 53FE4000 0x4000 GPIO5 */ 201 gpio7: gpio@53fe4000 { 202 compatible = "fsl,imx53-gpio"; 203 reg = <0x53fe4000 0x4000>; 204 interrupt-parent = <&tzic>; 205 interrupts = <107 108>; 206 gpio-controller; 207 #gpio-cells = <2>; 208 interrupt-controller; 209 #interrupt-cells = <1>; 210 }; 211 212 spba@50000000 { 213 compatible = "fsl,spba-bus", "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 interrupt-parent = <&tzic>; 217 ranges; 218 219 /* 50004000 0x4000 ESDHC 1 */ 220 esdhc@50004000 { 221 compatible = "fsl,imx53-esdhc"; 222 reg = <0x50004000 0x4000>; 223 interrupt-parent = <&tzic>; interrupts = <1>; 224 status = "disabled"; 225 }; 226 227 /* 50008000 0x4000 ESDHC 2 */ 228 esdhc@50008000 { 229 compatible = "fsl,imx53-esdhc"; 230 reg = <0x50008000 0x4000>; 231 interrupt-parent = <&tzic>; interrupts = <2>; 232 status = "disabled"; 233 }; 234 235 /* 5000C000 0x4000 UART 3 */ 236 uart3: serial@5000c000 { 237 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 238 reg = <0x5000c000 0x4000>; 239 interrupt-parent = <&tzic>; 240 interrupts = <33>; 241 status = "disabled"; 242 }; 243 244 /* 50010000 0x4000 eCSPI1 */ 245 ecspi@50010000 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "fsl,imx53-ecspi"; 249 reg = <0x50010000 0x4000>; 250 interrupt-parent = <&tzic>; 251 interrupts = <36>; 252 status = "disabled"; 253 }; 254 255 /* 50014000 0x4000 SSI2 irq30 */ 256 SSI2: ssi@50014000 { 257 compatible = "fsl,imx53-ssi"; 258 reg = <0x50014000 0x4000>; 259 interrupt-parent = <&tzic>; 260 interrupts = <30>; 261 status = "disabled"; 262 }; 263 264 /* 50020000 0x4000 ESDHC 3 */ 265 esdhc@50020000 { 266 compatible = "fsl,imx53-esdhc"; 267 reg = <0x50020000 0x4000>; 268 interrupt-parent = <&tzic>; 269 interrupts = <3>; 270 status = "disabled"; 271 }; 272 273 /* 50024000 0x4000 ESDHC 4 */ 274 esdhc@50024000 { 275 compatible = "fsl,imx53-esdhc"; 276 reg = <0x50024000 0x4000>; 277 interrupt-parent = <&tzic>; 278 interrupts = <4>; 279 status = "disabled"; 280 }; 281 282 /* 50028000 0x4000 SPDIF */ 283 /* 91 SPDIF */ 284 285 /* 50030000 0x4000 PATA (PORT UDMA) irq70 */ 286 287 /* 50034000 0x4000 SLM */ 288 /* 50038000 0x4000 HSI2C */ 289 /* 64 HS-I2C */ 290 /* 5003C000 0x4000 SPBA */ 291 }; 292 293 usbphy0: usbphy@0 { 294 compatible = "usb-nop-xceiv"; 295 status = "okay"; 296 }; 297 298 usbphy1: usbphy@1 { 299 compatible = "usb-nop-xceiv"; 300 status = "okay"; 301 }; 302 303 usbotg: usb@53f80000 { 304 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 305 reg = <0x53f80000 0x0200>; 306 interrupts = <18>; 307 fsl,usbphy = <&usbphy0>; 308 status = "disabled"; 309 }; 310 311 usbh1: usb@53f80200 { 312 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 313 reg = <0x53f80200 0x0200>; 314 interrupts = <14>; 315 fsl,usbphy = <&usbphy1>; 316 status = "disabled"; 317 }; 318 319 usbh2: usb@53f80400 { 320 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 321 reg = <0x53f80400 0x0200>; 322 interrupts = <16>; 323 status = "disabled"; 324 }; 325 326 usbh3: usb@53f80600 { 327 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 328 reg = <0x53f80600 0x0200>; 329 interrupts = <17>; 330 status = "disabled"; 331 }; 332 333 usbmisc: usbmisc@53f80800 { 334 #index-cells = <1>; 335 compatible = "fsl,imx53-usbmisc"; 336 reg = <0x53f80800 0x200>; 337 }; 338 339 /* 53F98000 0x4000 WDOG1 */ 340 wdog@53f98000 { 341 compatible = "fsl,imx53-wdt"; 342 reg = <0x53f98000 0x4000>; 343 interrupt-parent = <&tzic>; 344 interrupts = <58>; 345 status = "disabled"; 346 }; 347 348 /* 53F9C000 0x4000 WDOG2 (TZ) */ 349 wdog@53f9c000 { 350 compatible = "fsl,imx53-wdt"; 351 reg = <0x53f9c000 0x4000>; 352 interrupt-parent = <&tzic>; 353 interrupts = <59>; 354 status = "disabled"; 355 }; 356 357 /* 53F94000 0x4000 KPP */ 358 keyboard@53f94000 { 359 compatible = "fsl,imx53-kpp"; 360 reg = <0x53f94000 0x4000>; 361 interrupt-parent = <&tzic>; 362 interrupts = <60>; 363 status = "disabled"; 364 }; 365 366 /* 53FA0000 0x4000 GPT */ 367 timer@53fa0000 { 368 compatible = "fsl,imx53-gpt"; 369 reg = <0x53fa0000 0x4000>; 370 interrupt-parent = <&tzic>; 371 interrupts = <39>; 372 status = "disabled"; 373 }; 374 375 /* 53FA4000 0x4000 SRTC */ 376 377 rtc@53fa4000 { 378 compatible = "fsl,imx53-srtc"; 379 reg = <0x53fa4000 0x4000>; 380 interrupt-parent = <&tzic>; 381 interrupts = <24 25>; 382 status = "disabled"; 383 }; 384 385 /* 53FA8000 0x4000 IOMUXC */ 386 iomux@53fa8000 { 387 compatible = "fsl,imx53-iomux"; 388 reg = <0x53fa8000 0x4000>; 389 interrupt-parent = <&tzic>; 390 interrupts = <7>; 391 }; 392 393 /* 53FAC000 0x4000 EPIT1 */ 394 epit1: timer@53fac000 { 395 compatible = "fsl,imx53-epit"; 396 reg = <0x53fac000 0x4000>; 397 interrupt-parent = <&tzic>; 398 interrupts = <40>; 399 status = "disabled"; 400 }; 401 402 /* 53FB0000 0x4000 EPIT2 */ 403 epit2: timer@53fb0000 { 404 compatible = "fsl,imx53-epit"; 405 reg = <0x53fb0000 0x4000>; 406 interrupt-parent = <&tzic>; 407 interrupts = <41>; 408 status = "disabled"; 409 }; 410 411 /* 53FB4000 0x4000 PWM1 */ 412 pwm@53fb4000 { 413 compatible = "fsl,imx53-pwm"; 414 reg = <0x53fb4000 0x4000>; 415 interrupt-parent = <&tzic>; 416 interrupts = <61>; 417 status = "disabled"; 418 }; 419 420 /* 53FB8000 0x4000 PWM2 */ 421 pwm@53fb8000 { 422 compatible = "fsl,imx53-pwm"; 423 reg = <0x53fb8000 0x4000>; 424 interrupt-parent = <&tzic>; 425 interrupts = <94>; 426 status = "disabled"; 427 }; 428 429 /* 53FBC000 0x4000 UART 1 */ 430 uart1: serial@53fbc000 { 431 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 432 reg = <0x53fbc000 0x4000>; 433 interrupt-parent = <&tzic>; 434 interrupts = <31>; 435 status = "disabled"; 436 }; 437 438 /* 53FC0000 0x4000 UART 2 */ 439 uart2: serial@53fc0000 { 440 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 441 reg = <0x53fc0000 0x4000>; 442 interrupt-parent = <&tzic>; 443 interrupts = <32>; 444 status = "disabled"; 445 }; 446 447 /* 53FC0000 0x4000 UART 4 */ 448 uart4: serial@53ff0000 { 449 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 450 reg = <0x53ff0000 0x4000>; 451 interrupt-parent = <&tzic>; 452 interrupts = <13>; 453 status = "disabled"; 454 }; 455 456 /* 53FD0000 0x4000 SRC */ 457 reset@53fd0000 { 458 compatible = "fsl,imx53-src"; 459 reg = <0x53fd0000 0x4000>; 460 interrupt-parent = <&tzic>; 461 interrupts = <75>; 462 status = "disabled"; 463 }; 464 /* 53FD8000 0x4000 GPC */ 465 power@53fd8000 { 466 compatible = "fsl,imx53-gpc"; 467 reg = <0x53fd8000 0x4000>; 468 interrupt-parent = <&tzic>; 469 interrupts = <73 74>; 470 status = "disabled"; 471 }; 472 473 /* 53FE8000 0x4000 PATA (PORT PIO) */ 474 /* 70 PATA Parallel ATA host controller interrupt */ 475 ide@53fe8000 { 476 compatible = "fsl,imx53-ata"; 477 reg = <0x83fe0000 0x4000>; 478 interrupt-parent = <&tzic>; 479 interrupts = <70>; 480 status = "disabled"; 481 }; 482 483 }; 484 485 aips@60000000 { /* AIPS2 */ 486 compatible = "fsl,aips-bus", "simple-bus"; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 interrupt-parent = <&tzic>; 490 ranges; 491 492 /* 53FC0000 0x4000 UART 5 */ 493 uart5: serial@63f90000 { 494 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 495 reg = <0x63f90000 0x4000>; 496 interrupt-parent = <&tzic>; 497 interrupts = <32>; 498 status = "disabled"; 499 }; 500 501 /* 63F94000 0x4000 AHBMAX */ 502 /* 63F98000 0x4000 IIM */ 503 /* 504 * 69 IIM Interrupt request to the processor. 505 * Indicates to the processor that program or 506 * explicit. 507 */ 508 /* 63F9C000 0x4000 CSU */ 509 /* 510 * 27 CSU Interrupt Request 1. Indicates to the 511 * processor that one or more alarm inputs were. 512 */ 513 514 /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */ 515 /* irq76 Neon Monitor Interrupt */ 516 /* irq77 Performance Unit Interrupt */ 517 /* irq78 CTI IRQ */ 518 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */ 519 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */ 520 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */ 521 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */ 522 523 /* 63FA4000 0x4000 OWIRE irq88 */ 524 /* 63FA8000 0x4000 FIRI irq93 */ 525 /* 63FAC000 0x4000 eCSPI2 */ 526 ecspi@63fac000 { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 compatible = "fsl,imx53-ecspi"; 530 reg = <0x63fac000 0x4000>; 531 interrupt-parent = <&tzic>; 532 interrupts = <37>; 533 status = "disabled"; 534 }; 535 536 /* 63FB0000 0x4000 SDMA */ 537 sdma@63fb0000 { 538 compatible = "fsl,imx53-sdma"; 539 reg = <0x63fb0000 0x4000>; 540 interrupt-parent = <&tzic>; 541 interrupts = <6>; 542 }; 543 544 /* 63FB4000 0x4000 SCC */ 545 /* 21 SCC Security Monitor High Priority Interrupt. */ 546 /* 22 SCC Secure (TrustZone) Interrupt. */ 547 /* 23 SCC Regular (Non-Secure) Interrupt. */ 548 549 /* 63FB8000 0x4000 ROMCP */ 550 /* 63FBC000 0x4000 RTIC */ 551 /* 552 * 26 RTIC RTIC (Trust Zone) Interrupt Request. 553 * Indicates that the RTIC has completed hashing the 554 */ 555 556 /* 63FC0000 0x4000 CSPI */ 557 cspi@63fc0000 { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 compatible = "fsl,imx53-cspi"; 561 reg = <0x63fc0000 0x4000>; 562 interrupt-parent = <&tzic>; 563 interrupts = <38>; 564 status = "disabled"; 565 }; 566 567 /* 63FC4000 0x4000 I2C2 */ 568 i2c@63fc4000 { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 572 reg = <0x63fc4000 0x4000>; 573 interrupt-parent = <&tzic>; 574 interrupts = <63>; 575 status = "disabled"; 576 }; 577 578 /* 63FC8000 0x4000 I2C1 */ 579 i2c@63fc8000 { 580 #address-cells = <1>; 581 #size-cells = <0>; 582 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 583 reg = <0x63fc8000 0x4000>; 584 interrupt-parent = <&tzic>; 585 interrupts = <62>; 586 status = "disabled"; 587 }; 588 589 /* 63FCC000 0x4000 SSI1 */ 590 /* 29 SSI1 SSI-1 Interrupt Request */ 591 SSI1: ssi@63fcc000 { 592 compatible = "fsl,imx53-ssi"; 593 reg = <0x63fcc000 0x4000>; 594 interrupt-parent = <&tzic>; 595 interrupts = <29>; 596 status = "disabled"; 597 }; 598 599 /* 63FD0000 0x4000 AUDMUX */ 600 audmux@63fd4000 { 601 compatible = "fsl,imx53-audmux"; 602 reg = <0x63fd4000 0x4000>; 603 status = "disabled"; 604 }; 605 606 /* 63FD8000 0x4000 EXTMC */ 607 /* 8 EXTMC (NFC) */ 608 /* 15 EXTMC */ 609 /* 97 EXTMC Boot sequence completed interrupt */ 610 /* 611 * 101 EMI Indicates all pages have been transferred 612 * to NFC during an auto program operation. 613 */ 614 615 /* 83FE4000 0x4000 SIM */ 616 /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */ 617 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */ 618 619 /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */ 620 /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */ 621 /* 63FE4000 0x4000 MLB */ 622 /* 63FE8000 0x4000 SSI3 */ 623 /* 96 SSI3 SSI-3 Interrupt Request */ 624 SSI3: ssi@63fe8000 { 625 compatible = "fsl,imx51-ssi"; 626 reg = <0x63fe8000 0x4000>; 627 interrupt-parent = <&tzic>; 628 interrupts = <96>; 629 status = "disabled"; 630 }; 631 632 /* 63FEC000 0x4000 FEC */ 633 ethernet@63fec000 { 634 compatible = "fsl,imx53-fec"; 635 reg = <0x63fec000 0x4000>; 636 interrupt-parent = <&tzic>; 637 interrupts = <87>; 638 status = "disabled"; 639 }; 640 641 /* 63FF0000 0x4000 TVE */ 642 /* 92 TVE */ 643 /* 63FF4000 0x4000 VPU */ 644 /* 9 VPU */ 645 /* 100 VPU Idle interrupt from VPU */ 646 647 /* 63FF8000 0x4000 SAHARA */ 648 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */ 649 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */ 650 }; 651 }; 652 653 localbus@18000000 { 654 compatible = "simple-bus"; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 658 ranges; 659 660 vga: ipu3@1E000000 { 661 compatible = "fsl,ipu3"; 662 reg = < 663 0x1E000000 0x08000 /* CM */ 664 0x1E008000 0x08000 /* IDMAC */ 665 0x1E018000 0x08000 /* DP */ 666 0x1E020000 0x08000 /* IC */ 667 0x1E028000 0x08000 /* IRT */ 668 0x1E030000 0x08000 /* CSI0 */ 669 0x1E038000 0x08000 /* CSI1 */ 670 0x1E040000 0x08000 /* DI0 */ 671 0x1E048000 0x08000 /* DI1 */ 672 0x1E050000 0x08000 /* SMFC */ 673 0x1E058000 0x08000 /* DC */ 674 0x1E060000 0x08000 /* DMFC */ 675 0x1E068000 0x08000 /* VDI */ 676 0x1F000000 0x20000 /* CPMEM */ 677 0x1F020000 0x20000 /* LUT */ 678 0x1F040000 0x20000 /* SRM */ 679 0x1F060000 0x20000 /* TPM */ 680 0x1F080000 0x20000 /* DCTMPL */ 681 >; 682 interrupt-parent = <&tzic>; 683 interrupts = < 684 10 /* IPUEX Error */ 685 11 /* IPUEX Sync */ 686 >; 687 status = "disabled"; 688 }; 689 }; 690}; 691 692/* 693 694TODO: Not mapped interrupts 695 6965 DAP 69784 GPU2D (OpenVG) general interrupt 69885 GPU2D (OpenVG) busy signal (for S/W power gating feasibility) 69912 GPU3D 700102 GPU3D Idle interrupt from GPU3D (for S/W power gating) 70190 SJC 702*/ 703