cpufunc_asm_pj4b.S revision 261455
1257454Sian/*- 2257454Sian * Copyright (C) 2011 MARVELL INTERNATIONAL LTD. 3257454Sian * All rights reserved. 4257454Sian * 5257454Sian * Developed by Semihalf. 6257454Sian * 7257454Sian * Redistribution and use in source and binary forms, with or without 8257454Sian * modification, are permitted provided that the following conditions 9257454Sian * are met: 10257454Sian * 1. Redistributions of source code must retain the above copyright 11257454Sian * notice, this list of conditions and the following disclaimer. 12257454Sian * 2. Redistributions in binary form must reproduce the above copyright 13257454Sian * notice, this list of conditions and the following disclaimer in the 14257454Sian * documentation and/or other materials provided with the distribution. 15257454Sian * 3. Neither the name of MARVELL nor the names of contributors 16257454Sian * may be used to endorse or promote products derived from this software 17257454Sian * without specific prior written permission. 18257454Sian * 19257454Sian * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20257454Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21257454Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22257454Sian * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23257454Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24257454Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25257454Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26257454Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27257454Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28257454Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29257454Sian * SUCH DAMAGE. 30257454Sian */ 31314510Sian 32257454Sian#include <machine/asm.h> 33257454Sian__FBSDID("$FreeBSD: stable/10/sys/arm/arm/cpufunc_asm_pj4b.S 261455 2014-02-04 03:36:42Z eadler $"); 34257454Sian 35257454Sian#include <machine/param.h> 36257454Sian 37257454Sian.Lpj4b_cache_line_size: 38261939Sian .word _C_LABEL(arm_pdcache_line_size) 39257454Sian 40261939Sian.Lpj4b_sf_ctrl_reg: 41257454Sian .word 0xf1021820 42300709Sian 43261939Sian 44257454SianENTRY(pj4b_setttb) 45257454Sian /* Cache synchronization is not required as this core has PIPT caches */ 46261939Sian mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ 47257454Sian#ifdef SMP 48257454Sian orr r0, r0, #2 /* Set TTB shared memory flag */ 49270948Sian#endif 50257454Sian mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 51261939Sian mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 52257454Sian RET 53257454SianEND(pj4b_setttb) 54257454Sian 55314510SianENTRY_NP(armv6_icache_sync_all) 56257454Sian /* 57257454Sian * We assume that the code here can never be out of sync with the 58264977Sian * dcache, so that we can safely flush the Icache and fall through 59314510Sian * into the Dcache cleaning code. 60257454Sian */ 61314511Sian mov r0, #0 62318197Smarius mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ 63257454Sian mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */ 64257454Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 65257454Sian RET 66257454SianEND(armv6_icache_sync_all) 67257454Sian 68257454SianENTRY(pj4b_icache_sync_range) 69314511Sian sub r1, r1, #1 70318197Smarius add r1, r0, r1 71318197Smarius mcrr p15, 0, r1, r0, c5 /* invalidate IC range */ 72257454Sian mcrr p15, 0, r1, r0, c12 /* clean DC range */ 73257454Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 74308186Sjhibbits RET 75257454SianEND(pj4b_icache_sync_range) 76257454Sian 77257454SianENTRY(pj4b_dcache_inv_range) 78257454Sian ldr ip, .Lpj4b_cache_line_size 79257454Sian ldr ip, [ip] 80261939Sian sub r1, r1, #1 /* Don't overrun */ 81261939Sian sub r3, ip, #1 82314511Sian and r2, r0, r3 83257454Sian add r1, r1, r2 84257454Sian bic r0, r0, r3 85257454Sian 86300709Sian mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */ 87257454Sian1: 88257454Sian mcr p15, 0, r0, c7, c6, 1 89331501Sian add r0, r0, ip 90257454Sian subs r1, r1, ip 91257454Sian bpl 1b 92257454Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 93257454Sian RET 94257454SianEND(pj4b_dcache_inv_range) 95257454Sian 96257454SianENTRY(armv6_idcache_wbinv_all) 97308186Sjhibbits mov r0, #0 98308186Sjhibbits mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */ 99257454Sian mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */ 100300709Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 101300709Sian RET 102300709SianEND(armv6_idcache_wbinv_all) 103300709Sian 104300709SianENTRY(armv6_dcache_wbinv_all) 105300709Sian mov r0, #0 106257454Sian mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */ 107257454Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 108257454Sian RET 109257454SianEND(armv6_dcache_wbinv_all) 110257454Sian 111257454SianENTRY(pj4b_idcache_wbinv_range) 112257454Sian ldr ip, .Lpj4b_cache_line_size 113257454Sian ldr ip, [ip] 114261815Sian sub r1, r1, #1 /* Don't overrun */ 115261815Sian sub r3, ip, #1 116261815Sian and r2, r0, r3 117261815Sian add r1, r1, r2 118261815Sian bic r0, r0, r3 119261815Sian 120261815Sian mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ 121261815Sian1: 122261815Sian#ifdef SMP 123261815Sian /* Request for ownership */ 124261815Sian ldr r2, [r0] 125261815Sian str r2, [r0] 126261815Sian#endif 127261815Sian mcr p15, 0, r0, c7, c5, 1 128261815Sian mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */ 129261815Sian add r0, r0, ip 130261815Sian subs r1, r1, ip 131261815Sian bpl 1b 132261815Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 133261815Sian RET 134261815SianEND(pj4b_idcache_wbinv_range) 135257454Sian 136257454SianENTRY(pj4b_dcache_wbinv_range) 137257454Sian ldr ip, .Lpj4b_cache_line_size 138257454Sian ldr ip, [ip] 139257454Sian sub r1, r1, #1 /* Don't overrun */ 140257454Sian sub r3, ip, #1 141257454Sian and r2, r0, r3 142257454Sian add r1, r1, r2 143257454Sian bic r0, r0, r3 144257454Sian 145257454Sian mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ 146257454Sian1: 147257454Sian#ifdef SMP 148257454Sian /* Request for ownership */ 149257454Sian ldr r2, [r0] 150257454Sian str r2, [r0] 151257454Sian#endif 152257454Sian mcr p15, 0, r0, c7, c14, 1 153257454Sian add r0, r0, ip 154300709Sian subs r1, r1, ip 155261939Sian bpl 1b 156300709Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 157300709Sian RET 158300709SianEND(pj4b_dcache_wbinv_range) 159300709Sian 160300709SianENTRY(pj4b_dcache_wb_range) 161300709Sian ldr ip, .Lpj4b_cache_line_size 162257454Sian ldr ip, [ip] 163257454Sian sub r1, r1, #1 /* Don't overrun */ 164257454Sian sub r3, ip, #1 165300709Sian and r2, r0, r3 166300709Sian add r1, r1, r2 167257454Sian bic r0, r0, r3 168257454Sian 169257454Sian mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ 170257454Sian1: 171257454Sian#ifdef SMP 172257454Sian /* Request for ownership */ 173257454Sian ldr r2, [r0] 174257454Sian str r2, [r0] 175257454Sian#endif 176257454Sian mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */ 177314510Sian add r0, r0, ip 178257454Sian subs r1, r1, ip 179267171Skevlo bpl 1b 180257454Sian mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 181308186Sjhibbits RET 182308186SjhibbitsEND(pj4b_dcache_wb_range) 183308186Sjhibbits 184257454SianENTRY(pj4b_drain_readbuf) 185257454Sian mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */ 186308186Sjhibbits RET 187257454SianEND(pj4b_drain_readbuf) 188257454Sian 189257454SianENTRY(pj4b_flush_brnchtgt_all) 190257454Sian mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */ 191257454Sian RET 192257454SianEND(pj4b_flush_brnchtgt_all) 193308186Sjhibbits 194257454SianENTRY(pj4b_flush_brnchtgt_va) 195257454Sian mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */ 196257454Sian RET 197257454SianEND(pj4b_flush_brnchtgt_va) 198257454Sian 199257454SianENTRY(get_core_id) 200308186Sjhibbits mrc p15, 0, r0, c0, c0, 5 201257454Sian RET 202308186SjhibbitsEND(get_core_id) 203257454Sian 204257454SianENTRY(pj4b_config) 205257454Sian 206257454Sian /* Set Auxiliary Debug Modes Control 0 register */ 207257454Sian mrc p15, 1, r0, c15, c1, 0 208257454Sian /* ARMADAXP errata fix: ARM-CPU-6136 */ 209257454Sian bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */ 210257454Sian 211257454Sian orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */ 212300709Sian mcr p15, 1, r0, c15, c1, 0 213257454Sian 214257454Sian /* Set Auxiliary Debug Modes Control 1 register */ 215257454Sian mrc p15, 1, r0, c15, c1, 1 216257454Sian /* ARMADAXP errata fix: ARM-CPU-6409 */ 217257454Sian bic r0, r0, #(1 << 2) /* Disable static branch prediction */ 218257454Sian 219257454Sian orr r0, r0, #(1 << 5) /* STREX backoff disable */ 220257454Sian orr r0, r0, #(1 << 8) /* Internal parity handling disable */ 221257454Sian orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */ 222257454Sian mcr p15, 1, r0, c15, c1, 1 223257454Sian 224257454Sian /* Set Auxiliary Function Modes Control 0 register */ 225257454Sian mrc p15, 1, r0, c15, c2, 0 226257454Sian#if defined(SMP) 227257454Sian orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */ 228257454Sian#endif 229257454Sian orr r0, r0, #(1 << 2) /* L1 parite enable */ 230300709Sian orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */ 231257454Sian mcr p15, 1, r0, c15, c2, 0 232257454Sian 233257454Sian /* Set Auxiliary Debug Modes Control 2 register */ 234257454Sian mrc p15, 1, r0, c15, c1, 2 235257454Sian bic r0, r0, #(1 << 23) /* Enable fast LDR */ 236257454Sian orr r0, r0, #(1 << 25) /* Intervention Interleave disable */ 237257454Sian orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */ 238257454Sian orr r0, r0, #(1 << 29) /* Disable MO device read / write */ 239257454Sian orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/ 240257454Sian orr r0, r0, #(1U << 31) /* Enable write evict */ 241257454Sian mcr p15, 1, r0, c15, c1, 2 242257454Sian#if defined(SMP) 243257454Sian /* Set SMP mode in Auxiliary Control Register */ 244257454Sian mrc p15, 0, r0, c1, c0, 1 245257454Sian orr r0, r0, #(1 << 5) 246257454Sian mcr p15, 0, r0, c1, c0, 1 247300709Sian#endif 248257454Sian 249257454Sian /* Load CPU number */ 250257454Sian mrc p15, 0, r0, c0, c0, 5 251257454Sian and r0, r0, #0xf 252257454Sian 253257454Sian /* SF Enable and invalidate */ 254257454Sian ldr r1, .Lpj4b_sf_ctrl_reg 255308186Sjhibbits ldr r2, [r1, r0, lsl #8] 256257454Sian orr r2, r2, #(1 << 0) 257308186Sjhibbits bic r2, r2, #(1 << 8) 258300709Sian str r2, [r1, r0, lsl #8] 259257454Sian 260257454Sian RET 261257454SianEND(pj4b_config) 262257454Sian 263257454Sian