MFC: r342634 (partial)

o Don't allocate resources for SDMA in sdhci(4) if the controller or the
front-end doesn't support SDMA or the latter implements a platform-
specific transfer method instead. While at it, factor out allocation
and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to
keep the code more readable when adding support for ADMA variants.

o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum
of 512 KiB instead of using a fixed 4-KiB-buffer. With the default
MAXPHYS of 128 KiB and depending on the controller and medium, this
reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on
sequential reads while an increase of throughput of up to ~84 % was
seen.

Front-ends for broken controllers that only support an SDMA buffer
boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY
and supply a size via struct sdhci_slot. According to Linux, only -
unsupported in stable/10 anyway - Qualcomm MSM-type SDHCI controllers
are affected by this, though.

Requested by: Shreyank Amartya (unconditional bump to 512 KiB)

o Introduce a SDHCI_DEPEND macro for specifying the dependency of the
front-end modules on the sdhci(4) one and bump the module version
of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order
to ensure that all components are in sync WRT struct sdhci_slot.

o In sdhci(4):
- Make pointers const were applicable, and
- replace a few device_printf(9) calls with slot_printf() for
consistency.

MFC: r339007, r340543, r340654

- Add ACPI identifier for AMD eMMC 5.0 controller [1]
- Add a quirk handling for AMDI0040 controllers allowing them to do HS400. [2]

Submitted by: Rajesh Kumar [1], Shreyank Amartya (original version) [2]

MFC: r333613

The broken DDR52 support of Intel Bay Trail eMMC controllers rumored
in the commit log of r321385 has been confirmed via the public VLI54
erratum. Thus, stop advertising DDR52 for these controllers.
Note that this change should hardly make a difference in practice as
eMMC chips from the same era as these SoCs most likely support HS200
at least, probably even up to HS400ES.

MFC: r338261, r338512

- According to section 2.2.5 of the SDHCI specification version 4.20,
SDHCI_TRNS_ACMD12 is to be set only for multiple-block read/write
commands without data length information, so don't unconditionally
set this bit. The result matches what e. g. Linux does.
- Section 2.2.19 of the SDHCI specification version 4.20 states that
SDHCI_ACMD12_ERR should be only valid if SDHCI_INT_ACMD12ERR is set
and hardware may clear SDHCI_ACMD12_ERR when SDHCI_INT_ACMD12ERR is
cleared (differing silicon behavior is specifically allowed, though).
Thus, read SDHCI_ACMD12_ERR before clearing SDHCI_INT_ACMD12ERR.
While at it, use the 16-bit accessor rather than the 32-bit one for
reading the 16-bit SDHCI_ACMD12_ERR.
- SDHCI_INT_TUNEERR isn't one of the ROC bits in SDHCI_INT_STATUS so
clear it explicitly.
- Add missing prototypes and sort them.
- Explicitly compare a pointer to NULL. The __builtin_expect() of clang
3.4.1 otherwise isn't able to cope with the expression.

MFC: r327339, r327924

- There is no need to keep the tuning error and re-tuning interrupts
enabled (though, no interrupt generation enabled for them) all the
time as soon as (re-)tuning is supported; only enable them and let
them generate interrupts when actually using (re-)tuning.
- Also disable all interrupts except SDHCI_INT_DATA_AVAIL ones while
executing tuning and not just their signaling.
- Set the tuning error and re-tuning interrupt enable bits based on
the SDHCI_TUNING_ENABLED rather than the SDHCI_TUNING_SUPPORTED flag,
i. e. only when (re-)tuning is actually used. Currently, this change
makes no net difference, though.

MFC: r327315

Add quirks for Intel Denverton eMMC 5.0 controllers.

MFC: r321589

- Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE}
for embedded slots. Fail in the sdhci(4) initialization for slot type
shared, which is completely unsupported by this driver at the moment. [1]
For Intel eMMC controllers, taking the embedded slot type into account
obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk
entries.
- Hide the 1.8 V VDD capability when the slot is detected as non-embedded,
as the SDHCI specification explicitly states that 1.8 V VDD is applicable
to embedded slots only. [2]
- Define some easy bits of the SDHCI specification v4.20. [3]
- Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot().

Obtained from: DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3]

MFC: r319350, r320620, r321385, r321490, r321588, r321948

o Use SDHCI_CAN_DRIVE_TYPE_{A,C,D} to check for driver type support in
SDHCI_CAPABILITIES2 instead of SDHCI_CTRL2_DRIVER_TYPE_{A,C,D} which
are meant for setting the driver type in SDHCI_HOST_CONTROL2.

o Correct a typo in the comment part of r320577 (MFCed to stable/10 in
r320899).

o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to
sdhci(4), mmc(4) and mmcsd(4).

On the system where the addition of DDR52 support increased the read
throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields
~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than
quadrupled compared to pre-r315598 (pre-r318495 in stable/10).

However, in fact this isn't a feature-only change; there are boards
based on Intel Bay Trail where DDR52 is problematic and the suggested
workaround is to use HS200 mode instead. So far exact details are
unknown, however, i. e. whether that's due to a defect in these SoCs
or on the boards.

Moreover, due to the above changes requiring to be aware of possible
MMC siblings in the fast path of mmc(4), corresponding information
now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(),
now longer will trigger a panic in low memory situations and all of
mmc(4) operate on the same set of child devices.

o Fix a bug in the failure reporting of mmcsd_delete() that could lead
to a panic.

o Fix 2 bugs on resume, one in mmcsd(4) that could lead to a panic and
another one in mmc(4) that could lead to devices no longer working.

o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]

o Fix missing variable initialization in mmc_switch_status(). [2]

o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]

o Handle the case of device_add_child(9) failing, for example due to
a memory shortage, gracefully in mmc(4) and sdhci(4), including not
leaking memory for the instance variables in case of mmc(4), also
fixing [4].

o Correctly use the size of a pointer rather than that of a pointer to
a pointer (this bug was present in head r321385 only, i. e. not in a
stable branch). [5]

o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd()
gracefully instead of calling panic(9).

o Again, check and handle the return values of some additional function
calls in mmc(4) instead of assuming that everything went right or mark
non-fatal errors by casting the return value to void.

o Correct a typo in the Linux IOCTL compatibility; it should have been
MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.

o Now that we are reaching ever faster speeds (more improvement in this
regard is to be expected when adding ADMA support to sdhci(4)), apply
a few micro-optimizations to mmc(4), mmcsd(4) and sdhci(4).

o Correct confusing and error prone mix-ups between "br" or "bridge" in
mmc(4) and mmcsd(4) where - according to the terminology outlined in
comments of bridge.h and mmcbr_if.m around since their addition in
r163516 - the bus is meant and used instead.

o Remove comment lines from bridge.h incorrectly suggesting that there
would be a MMC bridge base class driver.

o Update comments in bridge.h regarding the star topology of SD and SDIO;
since version 3.00 of the SDHCI specification, for eSD and eSDIO bus
topologies are actually possible in form of so called "shared buses"
(in some subcontext later on renamed to "embedded" buses).

Reported by: Coverity
CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4],
1378432 [5]

MFC: r320577, r320620

Retry up to 2 ms to enable bus power as at least with some Intel
SDHCI/eMMC controllers the first attempt after a D3 to D0 transition,
i. e. when the firmware has put the devices into D3 state before,
can fail.

MFC: r318282

- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
quirk (see r311794 for the corresponding change to the sdhci(4) PCI
PCI front-end), though. However, due to the shared ACPI IDs, this
is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
Lead to Unpredictable System Behavior") silicon bug. When this
erratum hits, typically both SDHCI and XHCI controllers wedge.
According to Intel, using ADMA2 with 64-bit addressing and 96-bit
descriptors serves as a workaround. Until such times when sdhci(4)
has ADMA2 support, flag DMA as broken for affected interfaces.
This turns out to work around the problem, too, at the cost of
performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
and SDXC controllers, too.

MFC: r315598

o Add support for eMMC DDR bus speed mode up to 52 MHz to sdhci(4)
and mmc(4). Given that support for DDR52 is not denoted by SDHCI
capability registers, availability of that timing is indicated by
a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far.

Compared to 50 MHz at SDR high speed typically yielding ~45 MB/s
read throughput with the eMMC chips tested, read performance goes
up to ~80 MB/s at DDR52.

As a side-effect, this change also fixes communication with some
eMMC devices at SDR high speed mode due to the signaling voltage
and UHS bits in the SDHCI controller no longer being left in an
inappropriate state.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.

MFC: r315431

- Adds macros for the content of SDHCI_ADMA_ERR and SDHCI_HOST_CONTROL2
registers.
- Add slot type capability bits. These bits should allow recognizing
removable card slots, embedded cards and shared buses (shared bus
supposedly is always comprised of non-removable cards).
- Dump CAPABILITIES2, ADMA_ERR, HOST_CONTROL2 and ADMA_ADDRESS_LO
registers in sdhci_dumpregs().
- The drive type support flags in the CAPABILITIES2 register are for
drive types A,C,D, drive type B is the default setting (value 0) of
the drive strength field in the SDHCI_HOST_CONTROL2 register.

Obtained from: DragonFlyBSD (9e3c8f63, 455bd1b1)

MFC: r292180 (partial), r297127 (partial), r311911, r311923, r312939,
r313250, r313712, r314811 (partial), r314887 (partial), r315430,
r317981, r315466

o Move the DRIVER_MODULE() statements that declare mmc(4) to be a child
of the various bridge drivers out of dev/mmc.c and into the bridge
drivers.

o Add ACPI platform support for SDHCI driver.

o Fix some overly long lines, whitespace and other bugs according to
style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4).

o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method,
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.

o Trim/adjust includes.

o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
as kernel drivers and their dependency onto mmc(4).

o Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)

Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.

CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.

o Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications.

o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter have been added to ports as sysutils/mmc-utils.
Among others, the `mmc` tool of mmc-utils allows for partitioning
eMMC devices (tested working).

o For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.

o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.

MFC: r273180, r283754, r297329, r299414, r300707, r310309, r310340 (partial),
r310341, r311664, r311793-311794

o Use correct response bits for MMC_RSP_R4-R7 types

o Make sdhci(4) work after suspend/resume for chipsets that require
the frequency quirk. This makes it work on eg ThinkPad T420.

o Add a convenience macro that masks all the bits related to clock divisors
in all versions of the sdhci spec (the HI bits are just unused reserved
bits in earlier versions).

o sdhci/mmc: Minor whitespace cleanups

o Add Braswell PCI IDs for Intel Cherryview

o mmc: Accept even lower voltage for Cherryview

And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698.

o In mmcsd_task(), bio_resid was not being set to 0 on a successful read
or write, resulting in random short-read and short-write returns for
requests. Fixing this fixes nominal block I/O via mmcsd(4).

Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0)

o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers.

o Flesh out the support for Intel Braswell eMMC controllers further.

o In sdhci_init_slot(), use the right capability field for determining
the announced bus width based on MMC_CAP_*_BIT_DATA.

MFC: r296135

Replace several bus_alloc_resource() calls with bus_alloc_resource_any()

Most of these are BARs, and we allocate them in their entirety. The one
outlier in this is amdsbwd(4), which calls bus_set_resource() prior.

MFC r283263, r289359, r308187, r311660, r311693, r311727, r311797:

Raise the SDHCI timeout to 10 seconds and add a sysctl to allow changing
this value at runtime.

Add support for the BCM57765 card reader.

Toggle card insert/remove interrupt enable bits on events.

Add a new sdhci interface method, get_card_present().

Now that the PRESENT_STATE register is only used for the inhibit bits loop
in this function, sdhci_start_command(), eliminate the state variable and
restructure the loop to read the register just once at the top of the loop.

Add support for non-removable media, and a quirk to use polling to detect
card insert/remove events on controllers that don't implement the insert
and remove interrupts.

Add sdhci_handle_card_present_locked() that can be called from the interrupt
handler which already holds the mutex, and have sdhci_handle_card_present()
be just a tiny wrapper that does the locking for external callers.

MFC r279359, r279360:

For new eMMC chips, we must signal controller HC capability in OP_COND command.

Detect, report and use 8-bit bus if is available.

MFC r277306, r277307, r277346:

Add defines for SDHCI 3.0 controllers.

Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT.

Save the command-and-flags value into shadow register when it is written.

MFC r277027:
Handle the possibility that SDHCI_PLATFORM_START_TRANSFER() can fail.

MFC: r276469

- Switching the mode of Ricoh R5CE823 to SD2.0 causes their PCI device ID
to change to 0xe822, which may be persistent across reboots and, thus,
confuse other OSes. Therefore, restore the original mode and frequency
setting on detach and shutdown.
- Report Ricoh R5CE822 as such.
- According to Linux, Ricoh R5CE822 also need SDHCI_QUIRK_LOWER_FREQUENCY.
- Nuke an unused softc member.

MFC: r273050

class, subclass and progif were never used, so don't bother setting
them.

MFC r275944, r275946, r275949, r275950:

Add code to set and reset open-drain mode on the bus when requested.

When command and data interrupts have been aggregated together, don't do
the data-completed processing if a command-error interrupt is also asserted.

Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around
TI OMAP controllers which will return the reset-in-progress bit as zero if
you read the status register too fast after setting the reset bit.

MFC: r270885, r270948

- Nuke unused sdhci_softc.
- Static'ize sdhci_debug local to sdhci.c.
- Const'ify PCI device description strings.
- Nuke redundant resource ID members from sdhci_pci_softc.
- Nuke unused hw.sdhci_pci.debug tunable.
- Add support for using MSI instead of INTx, controllable via the tunable
hw.sdhci.enable_msi (defaulting to on) and tested with a RICOH R5CE823 SD
controller.
- Use NULL instead of 0 for pointers.

MFC r264096, r264097, r264099 r264100, r264101, r264102, r264119:

Fixes to the ti_sdhci and sdhci drivers (fix clock divisor calcs).

Use the ti_sdhci driver instead of ti_mmchs for Pandaboard.

MFC 265208: Honor the max-frequency property if it appears in the fdt data.

MFC r261938, r261939, r261940, r261944, r261945, r261946, r261947, r261956, r261957, r261983, r261094,
r261955, r261958,

Add a driver to provide access to imx6 on-chip one-time-programmble data.

Make it possible to access the ocotp registers before the ocotp device
is attached, by establishing a temporary mapping of the registers when
necessary.

It turns out Freescale cleverly made the ocotp device compatible across
several different families of SoCs, so move it to the freescale directory
and prefix everything with fsl rather than imx6.

Convert the imx6 sdhci "R1B fix" from a busy-loop in the interrupt handler
to a callout.

Increase the wait time for acquiring the SD bus from 10 to 250ms.

If no compatible cards were found after probing the SD bus, say so.

Add timeout logic to sdhci, separate from the timeouts done by the hardware.

After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA
rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing
any possibility of recovering from the error.

Add a helper routine to depth-search the device tree for a node with a
matching 'compatible' property.

MFC r261803, r261808, r261814, r261815, r261816, r261817, r261818, r261826,
r261848, r261855

On armv6 and later, use the WriteNotRead bit of the fault status register
to decide what protections are required by the faulting access.

Use the right symbols for determining arm architecture. Include the
necessary header file which has the new FAULT_WNR symbol defined in it.

Allow the kernel to be loaded at any 1MiB address. This requirement is
because we use the 1MiB section maps as they only need a single pagetable.

Add function for configuring Vybrid PLL4 (Audio) clock frequency output.

imx6 changes ...

- Fix the definition of the SDHCI_STATE_DAT and SDHCI_STATE_CMD fields,
and add SDHCI_RETUNE_REQUEST. None of these are actually used in the
code yet.

- Write translation code for the SDHCI_PRESENT_STATE register.
Freescale moved some bits around in their version of the register,
adjust things so that the sdhci code sees the standard layout.

- Add standard non-removable and cd-gpios properties to the usdhc
devices. That generates references to gpio devices, so uncomment them
even though there isn't a gpio driver to do anything with them yet.

- Add handling of standard "non-removable" property, and also some
workaround code so that if card detect is wired to a gpio pin, for now
we just treat it the same as non-removable (because there isn't a gpio
driver yet).

- Enable both sdcard slots, but not the sdio-based wifi that we don't
yet have a driver for.

- Remove a couple obsolete function declarations.

MFC r261410

Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Style changes and typos fixed.

Allow a hardware driver to pass clock frequencies into the sdhci driver.

The sdhci spec says that if the base or timeout clock frequency in the
capabilities register is zero, the driver must obtain the frequency "from
another source." This change defines that other source to be the low-level
hardware driver, which can pre-set the frequencies in slot.max_clk and
slot.timeout_clk before calling sdhci_init_slot().

This helps with a growing number of SoCs that have sdhci base clock
frequencies that either won't fit into the range allowed by the number of
bits available in the capabilities register, or the frequency is runtime-
configurable.

Add a new SDHCI_QUIRK_DONT_SHIFT_RESPONSE for hardware that pre-shifts
the response bits the way we do in software. While the hardware is just
doing the sensible thing rather than leaving it to the software, it's in
violation of the spec by doing so. Grrrr.

Add named constants for 8-bit bus support. The sdhci and mmc drivers
don't have support for this yet, but some low-level hardware is ready
for it when the higher layers catch up.

When the timeout clock is based on the SD clock, the timeout counter
has to be recalculated every time the SD clock frequency changes.

Also, tidy up the counter calculation... it makes no sense to calculate
a value one larger than the limit, then whine that it's too large and
truncate it to the limit. If the BROKEN_TIMEOUT quirk is set, don't
calculate the counter at all, just set it to the limit value.

Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.

Submitted by: Thomas Skibo <ThomasSkibo (at) sbcglobal.net>
Reviewed by: wkoszek, freebsd-arm@ (no objections raised)

Add hooks for plugging platform-provided transfer backend.

In order to use platorm backend hardware driver should
impement three methods:
- platform_start_transfer and platform_finish_transfer
to start and finish transfer
- platform_will_handle - check whether transaction is
suitable for backend. If not - driver will fall back
to PIO mode.

Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Approved by: ian@

Remove accidentally committed debug panic(9) call

Disable debug accidentally enabled by previous commit

Various timing-related fixes:

- Replace divisor numbers with more descirptive names
- Properly calculate minimum frequency for SDHCI 3.0
- Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clock
- Add min_freq method to sdhci_if.m and provide default
implementation. By re-implementing this method hardware
drivers can control frequency controller operates when
executing initialization sequence

Use DEVMETHOD_END macro defined in sys/bus.h instead of {0, 0} sentinel on device_method_t arrays

Reviewed by: cognet
Approved by: cognet

- Get proper maximum clock frequency for SDHCI v3.0 and higher

Add new quirks:
- Data timeout is broken
- Data timeout uses SD clock
- Capabilities register is unavailable

Add calculations for clock divisor for SDHCI 3.0

Split sdhci driver in two parts: sdhci and sdhci_pci.
sdchi encapsulates a generic SD Host Controller logic that relies on
actual hardware driver for register access.

sdhci_pci implements driver for PCI SDHC controllers using new SDHCI
interface

No kernel config modifications are required, but if you load sdhc
as a module you must switch to sdhci_pci instead.

Return back double spacing.

Fix typo in comment, should be MHz here.

Submitted by: Daan Vreeken <Daan vitsch.nl>

Add support for RICOH R5CE823 card reader, that can be found in
some Lenovo laptops.

The conroller needs a quirk to lower its frequency, and after
that it operates normally.

Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.

The SYSCTL_NODE macro defines a list that stores all child-elements of
that node. If there's no SYSCTL_DECL macro anywhere else, there's no
reason why it shouldn't be static.

Fix read_ivar implementation for MMC and SD.

1. Both mmc_read_ivar() and sdhci_read_ivar() use the expression
'*(int *)result = val' to assign to result which is uintptr_t *.
This does not work on big-endian 64 bit systems.

2. The media_size ivar is declared as 'off_t' which does not fit
into uintptr_t in 32bit systems, change this to long.

Submitted by: kanthms at netlogicmicro com (initial version)

Force DMA for controller found in Lenovo T510 (probably in others too).
This makes reads 10 times faster.

Discussed with: mav

Add support for interruptless kernel dumping.

Fix read_ivar prototype.

Add hw.sdhci.debug sysctl to control debug level.

Cleanup msleep() arguments.
Move wakeup() out of the lock.

Forget current bus power settings on full reset. Chip must be reconfigured.

Do not issue command if there is no card, clock or power.
Controller will not detect command timeout without clock active.

Add controller suspend/resume support.

To be able to correctly suspend/resume with card inserted,
respective support should be also implemented at mmc and mmcsd layers.

Allow card reader bridge driver to report maximum supported transfer size.
sdhci supports up to 65535 blocks transfers, at91_mci - one block.

Enable multiblock operations disabled before to follow at91_mci driver
limitations.

Reviewed by: imp@

Import sdhci (PCI SD Host Controller) driver.
Driver supports PCI devices with class 8 and subclass 5 according to
SD Host Controller Specification.

Update NOTES, enable module and static build.
Enable related mmc and mmcsd modules build.

Discussed on: mobile@, current@