zedboard.dts revision 266382
1/*- 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/zedboard.dts 266382 2014-05-18 00:15:48Z ian $ 27 */ 28 29/dts-v1/; 30 31/ { 32 model = "zedboard"; 33 compatible = "digilent,zedboard"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 interrupt-parent = <&GIC>; 37 38 // cpus { 39 // #address-cells = <1>; 40 // #size-cells = <0>; 41 // cpu@0 { 42 // device-type = "cpu"; 43 // model = "ARM Cortex-A9"; 44 // }; 45 // }; 46 47 memory { 48 // First megabyte isn't accessible by all interconnect masters. 49 device_type = "memory"; 50 reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */ 51 }; 52 53 // Zynq PS System registers. 54 // 55 ps7sys@f8000000 { 56 device_type = "soc"; 57 compatible = "simple-bus"; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges = <0x0 0xf8000000 0xf10000>; 61 62 // SLCR block 63 slcr: slcr@7000 { 64 compatible = "xlnx,zy7_slcr"; 65 reg = <0x0 0x1000>; 66 }; 67 68 // Interrupt controller 69 GIC: gic { 70 compatible = "arm,gic"; 71 interrupt-controller; 72 #address-cells = <0>; 73 #interrupt-cells = <1>; 74 reg = <0xf01000 0x1000>, // distributer registers 75 <0xf00100 0x0100>; // CPU if registers 76 }; 77 78 // L2 cache controller 79 pl310@f02000 { 80 compatible = "arm,pl310"; 81 reg = <0xf02000 0x1000>; 82 interrupts = <34>; 83 interrupt-parent = <&GIC>; 84 }; 85 86 // Device Config 87 devcfg: devcfg@7000 { 88 compatible = "xlnx,zy7_devcfg"; 89 reg = <0x7000 0x1000>; 90 interrupts = <40>; 91 interrupt-parent = <&GIC>; 92 }; 93 94 // triple timer counters0,1 95 ttc0: ttc@1000 { 96 compatible = "xlnx,ttc"; 97 reg = <0x1000 0x1000>; 98 }; 99 ttc1: ttc@2000 { 100 compatible = "xlnx,ttc"; 101 reg = <0x2000 0x1000>; 102 }; 103 104 // ARM Cortex A9 TWD Timer 105 timer@f00600 { 106 compatible = "arm,mpcore-timers"; 107 clock-frequency = <333333333>; // 333Mhz 108 #address-cells = <1>; 109 #size-cells = <0>; 110 reg = <0xf00200 0x100>, // Global Timer Regs 111 <0xf00600 0x20>; // Private Timer Regs 112 interrupts = < 27 29 >; 113 interrupt-parent = <&GIC>; 114 }; 115 116 // system watch-dog timer 117 swdt@5000 { 118 device_type = "watchdog"; 119 compatible = "xlnx,zy7_wdt"; 120 reg = <0x5000 0x1000>; 121 interrupts = <41>; 122 interrupt-parent = <&GIC>; 123 }; 124 125 scuwdt@f00620 { 126 device_type = "watchdog"; 127 compatible = "arm,mpcore_wdt"; 128 reg = <0xf00620 0x20>; 129 interrupts = <30>; 130 interrupt-parent = <&GIC>; 131 reset = <1>; 132 }; 133 }; // pssys@f8000000 134 135 // Zynq PS I/O Peripheral registers. 136 // 137 ps7io@e0000000 { 138 device_type = "soc"; 139 compatible = "simple-bus"; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 ranges = <0x0 0xe0000000 0x300000>; 143 144 // uart0: uart@0000 { 145 // device_type = "serial"; 146 // compatible = "cadence,uart"; 147 // reg = <0x0000 0x1000>; 148 // interrupts = <59>; 149 // interrupt-parent = <&GIC>; 150 // clock-frequency = <50000000>; 151 // }; 152 153 uart1: uart@1000 { 154 device_type = "serial"; 155 compatible = "cadence,uart"; 156 reg = <0x1000 0x1000>; 157 interrupts = <82>; 158 interrupt-parent = <&GIC>; 159 clock-frequency = <50000000>; 160 current-speed = <115200>; 161 }; 162 163 gpio: gpio@a000 { 164 compatible = "xlnx,zy7_gpio"; 165 reg = <0xa000 0x1000>; 166 interrupts = <52>; 167 interrupt-parent = <&GIC>; 168 }; 169 170 // GigE 171 eth0: eth@b000 { 172 // device_type = "network"; 173 174 compatible = "cadence,gem"; 175 reg = <0xb000 0x1000>; 176 interrupts = <54 55>; 177 interrupt-parent = <&GIC>; 178 }; 179 180 // SDIO 181 sdhci0: sdhci@100000 { 182 compatible = "xlnx,zy7_sdhci"; 183 reg = <0x100000 0x1000>; 184 interrupts = <56>; 185 interrupt-parent = <&GIC>; 186 max-frequency = <50000000>; 187 }; 188 189 // QSPI 190 qspi0: qspi@d000 { 191 compatible = "xlnx,zy7_qspi"; 192 reg = <0xd000 0x1000>; 193 interrupts = <51>; 194 interrupt-parent = <&GIC>; 195 spi-clock = <50000000>; 196 ref-clock = <190476000>; 197 }; 198 199 // USB 200 ehci0: ehci@2000 { 201 compatible = "xlnx,zy7_ehci"; 202 reg = <0x2000 0x1000>; 203 interrupts = <53>; 204 interrupt-parent = <&GIC>; 205 phy_vbus_ext; 206 }; 207 208 }; // ps7io@e0000000 209 210 chosen { 211 stdin = &uart1; 212 stdout = &uart1; 213 }; 214}; 215 216