sdhci.c revision 266751
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci.c 266751 2014-05-27 15:30:24Z ian $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/callout.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/lock.h> 36#include <sys/module.h> 37#include <sys/mutex.h> 38#include <sys/resource.h> 39#include <sys/rman.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/stdarg.h> 46 47#include <dev/mmc/bridge.h> 48#include <dev/mmc/mmcreg.h> 49#include <dev/mmc/mmcbrvar.h> 50 51#include "mmcbr_if.h" 52#include "sdhci.h" 53#include "sdhci_if.h" 54 55struct sdhci_softc; 56 57struct sdhci_softc { 58 device_t dev; /* Controller device */ 59 struct resource *irq_res; /* IRQ resource */ 60 int irq_rid; 61 void *intrhand; /* Interrupt handle */ 62 63 int num_slots; /* Number of slots on this controller */ 64 struct sdhci_slot slots[6]; 65}; 66 67static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 68 69int sdhci_debug = 0; 70TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 71SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 72 73#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 74#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 75#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 76#define RD_MULTI_4(slot, off, ptr, count) \ 77 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 78 79#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 80#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 81#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 82#define WR_MULTI_4(slot, off, ptr, count) \ 83 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 84 85static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 86static void sdhci_start(struct sdhci_slot *slot); 87static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 88 89static void sdhci_card_task(void *, int); 90 91/* helper routines */ 92#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 93#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 94#define SDHCI_LOCK_INIT(_slot) \ 95 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 96#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 97#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 98#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 99 100#define SDHCI_DEFAULT_MAX_FREQ 50 101 102#define SDHCI_200_MAX_DIVIDER 256 103#define SDHCI_300_MAX_DIVIDER 2046 104 105static void 106sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 107{ 108 if (error != 0) { 109 printf("getaddr: error %d\n", error); 110 return; 111 } 112 *(bus_addr_t *)arg = segs[0].ds_addr; 113} 114 115static int 116slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 117{ 118 va_list ap; 119 int retval; 120 121 retval = printf("%s-slot%d: ", 122 device_get_nameunit(slot->bus), slot->num); 123 124 va_start(ap, fmt); 125 retval += vprintf(fmt, ap); 126 va_end(ap); 127 return (retval); 128} 129 130static void 131sdhci_dumpregs(struct sdhci_slot *slot) 132{ 133 slot_printf(slot, 134 "============== REGISTER DUMP ==============\n"); 135 136 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 137 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 138 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 139 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 140 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 141 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 142 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 143 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 144 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 145 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 146 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 147 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 148 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 149 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 150 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 151 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 152 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 153 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 154 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 155 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 156 157 slot_printf(slot, 158 "===========================================\n"); 159} 160 161static void 162sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 163{ 164 int timeout; 165 uint8_t res; 166 167 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 168 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 169 SDHCI_CARD_PRESENT)) 170 return; 171 } 172 173 /* Some controllers need this kick or reset won't work. */ 174 if ((mask & SDHCI_RESET_ALL) == 0 && 175 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 176 uint32_t clock; 177 178 /* This is to force an update */ 179 clock = slot->clock; 180 slot->clock = 0; 181 sdhci_set_clock(slot, clock); 182 } 183 184 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 185 186 if (mask & SDHCI_RESET_ALL) { 187 slot->clock = 0; 188 slot->power = 0; 189 } 190 191 /* Wait max 100 ms */ 192 timeout = 100; 193 /* Controller clears the bits when it's done */ 194 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 195 if (timeout == 0) { 196 slot_printf(slot, 197 "Reset 0x%x never completed - 0x%x.\n", 198 (int)mask, (int)res); 199 sdhci_dumpregs(slot); 200 return; 201 } 202 timeout--; 203 DELAY(1000); 204 } 205} 206 207static void 208sdhci_init(struct sdhci_slot *slot) 209{ 210 211 sdhci_reset(slot, SDHCI_RESET_ALL); 212 213 /* Enable interrupts. */ 214 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 215 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 216 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 217 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 218 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 219 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 220 SDHCI_INT_ACMD12ERR; 221 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 222 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 223} 224 225static void 226sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 227{ 228 uint32_t res; 229 uint16_t clk; 230 uint16_t div; 231 int timeout; 232 233 if (clock == slot->clock) 234 return; 235 slot->clock = clock; 236 237 /* Turn off the clock. */ 238 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 239 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 240 /* If no clock requested - left it so. */ 241 if (clock == 0) 242 return; 243 244 /* Recalculate timeout clock frequency based on the new sd clock. */ 245 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 246 slot->timeout_clk = slot->clock / 1000; 247 248 if (slot->version < SDHCI_SPEC_300) { 249 /* Looking for highest freq <= clock. */ 250 res = slot->max_clk; 251 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 252 if (res <= clock) 253 break; 254 res >>= 1; 255 } 256 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 257 div >>= 1; 258 } 259 else { 260 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 261 if (clock >= slot->max_clk) 262 div = 0; 263 else { 264 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 265 if ((slot->max_clk / div) <= clock) 266 break; 267 } 268 } 269 div >>= 1; 270 } 271 272 if (bootverbose || sdhci_debug) 273 slot_printf(slot, "Divider %d for freq %d (max %d)\n", 274 div, clock, slot->max_clk); 275 276 /* Now we have got divider, set it. */ 277 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 278 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 279 << SDHCI_DIVIDER_HI_SHIFT; 280 281 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 282 /* Enable clock. */ 283 clk |= SDHCI_CLOCK_INT_EN; 284 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 285 /* Wait up to 10 ms until it stabilize. */ 286 timeout = 10; 287 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 288 & SDHCI_CLOCK_INT_STABLE)) { 289 if (timeout == 0) { 290 slot_printf(slot, 291 "Internal clock never stabilised.\n"); 292 sdhci_dumpregs(slot); 293 return; 294 } 295 timeout--; 296 DELAY(1000); 297 } 298 /* Pass clock signal to the bus. */ 299 clk |= SDHCI_CLOCK_CARD_EN; 300 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 301} 302 303static void 304sdhci_set_power(struct sdhci_slot *slot, u_char power) 305{ 306 uint8_t pwr; 307 308 if (slot->power == power) 309 return; 310 311 slot->power = power; 312 313 /* Turn off the power. */ 314 pwr = 0; 315 WR1(slot, SDHCI_POWER_CONTROL, pwr); 316 /* If power down requested - left it so. */ 317 if (power == 0) 318 return; 319 /* Set voltage. */ 320 switch (1 << power) { 321 case MMC_OCR_LOW_VOLTAGE: 322 pwr |= SDHCI_POWER_180; 323 break; 324 case MMC_OCR_290_300: 325 case MMC_OCR_300_310: 326 pwr |= SDHCI_POWER_300; 327 break; 328 case MMC_OCR_320_330: 329 case MMC_OCR_330_340: 330 pwr |= SDHCI_POWER_330; 331 break; 332 } 333 WR1(slot, SDHCI_POWER_CONTROL, pwr); 334 /* Turn on the power. */ 335 pwr |= SDHCI_POWER_ON; 336 WR1(slot, SDHCI_POWER_CONTROL, pwr); 337} 338 339static void 340sdhci_read_block_pio(struct sdhci_slot *slot) 341{ 342 uint32_t data; 343 char *buffer; 344 size_t left; 345 346 buffer = slot->curcmd->data->data; 347 buffer += slot->offset; 348 /* Transfer one block at a time. */ 349 left = min(512, slot->curcmd->data->len - slot->offset); 350 slot->offset += left; 351 352 /* If we are too fast, broken controllers return zeroes. */ 353 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 354 DELAY(10); 355 /* Handle unaligned and aligned buffer cases. */ 356 if ((intptr_t)buffer & 3) { 357 while (left > 3) { 358 data = RD4(slot, SDHCI_BUFFER); 359 buffer[0] = data; 360 buffer[1] = (data >> 8); 361 buffer[2] = (data >> 16); 362 buffer[3] = (data >> 24); 363 buffer += 4; 364 left -= 4; 365 } 366 } else { 367 RD_MULTI_4(slot, SDHCI_BUFFER, 368 (uint32_t *)buffer, left >> 2); 369 left &= 3; 370 } 371 /* Handle uneven size case. */ 372 if (left > 0) { 373 data = RD4(slot, SDHCI_BUFFER); 374 while (left > 0) { 375 *(buffer++) = data; 376 data >>= 8; 377 left--; 378 } 379 } 380} 381 382static void 383sdhci_write_block_pio(struct sdhci_slot *slot) 384{ 385 uint32_t data = 0; 386 char *buffer; 387 size_t left; 388 389 buffer = slot->curcmd->data->data; 390 buffer += slot->offset; 391 /* Transfer one block at a time. */ 392 left = min(512, slot->curcmd->data->len - slot->offset); 393 slot->offset += left; 394 395 /* Handle unaligned and aligned buffer cases. */ 396 if ((intptr_t)buffer & 3) { 397 while (left > 3) { 398 data = buffer[0] + 399 (buffer[1] << 8) + 400 (buffer[2] << 16) + 401 (buffer[3] << 24); 402 left -= 4; 403 buffer += 4; 404 WR4(slot, SDHCI_BUFFER, data); 405 } 406 } else { 407 WR_MULTI_4(slot, SDHCI_BUFFER, 408 (uint32_t *)buffer, left >> 2); 409 left &= 3; 410 } 411 /* Handle uneven size case. */ 412 if (left > 0) { 413 while (left > 0) { 414 data <<= 8; 415 data += *(buffer++); 416 left--; 417 } 418 WR4(slot, SDHCI_BUFFER, data); 419 } 420} 421 422static void 423sdhci_transfer_pio(struct sdhci_slot *slot) 424{ 425 426 /* Read as many blocks as possible. */ 427 if (slot->curcmd->data->flags & MMC_DATA_READ) { 428 while (RD4(slot, SDHCI_PRESENT_STATE) & 429 SDHCI_DATA_AVAILABLE) { 430 sdhci_read_block_pio(slot); 431 if (slot->offset >= slot->curcmd->data->len) 432 break; 433 } 434 } else { 435 while (RD4(slot, SDHCI_PRESENT_STATE) & 436 SDHCI_SPACE_AVAILABLE) { 437 sdhci_write_block_pio(slot); 438 if (slot->offset >= slot->curcmd->data->len) 439 break; 440 } 441 } 442} 443 444static void 445sdhci_card_delay(void *arg) 446{ 447 struct sdhci_slot *slot = arg; 448 449 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 450} 451 452static void 453sdhci_card_task(void *arg, int pending) 454{ 455 struct sdhci_slot *slot = arg; 456 457 SDHCI_LOCK(slot); 458 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 459 if (slot->dev == NULL) { 460 /* If card is present - attach mmc bus. */ 461 slot->dev = device_add_child(slot->bus, "mmc", -1); 462 device_set_ivars(slot->dev, slot); 463 SDHCI_UNLOCK(slot); 464 device_probe_and_attach(slot->dev); 465 } else 466 SDHCI_UNLOCK(slot); 467 } else { 468 if (slot->dev != NULL) { 469 /* If no card present - detach mmc bus. */ 470 device_t d = slot->dev; 471 slot->dev = NULL; 472 SDHCI_UNLOCK(slot); 473 device_delete_child(slot->bus, d); 474 } else 475 SDHCI_UNLOCK(slot); 476 } 477} 478 479int 480sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 481{ 482 uint32_t caps, freq; 483 int err; 484 485 SDHCI_LOCK_INIT(slot); 486 slot->num = num; 487 slot->bus = dev; 488 489 /* Allocate DMA tag. */ 490 err = bus_dma_tag_create(bus_get_dma_tag(dev), 491 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 492 BUS_SPACE_MAXADDR, NULL, NULL, 493 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 494 BUS_DMA_ALLOCNOW, NULL, NULL, 495 &slot->dmatag); 496 if (err != 0) { 497 device_printf(dev, "Can't create DMA tag\n"); 498 SDHCI_LOCK_DESTROY(slot); 499 return (err); 500 } 501 /* Allocate DMA memory. */ 502 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 503 BUS_DMA_NOWAIT, &slot->dmamap); 504 if (err != 0) { 505 device_printf(dev, "Can't alloc DMA memory\n"); 506 SDHCI_LOCK_DESTROY(slot); 507 return (err); 508 } 509 /* Map the memory. */ 510 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 511 (void *)slot->dmamem, DMA_BLOCK_SIZE, 512 sdhci_getaddr, &slot->paddr, 0); 513 if (err != 0 || slot->paddr == 0) { 514 device_printf(dev, "Can't load DMA memory\n"); 515 SDHCI_LOCK_DESTROY(slot); 516 if(err) 517 return (err); 518 else 519 return (EFAULT); 520 } 521 522 /* Initialize slot. */ 523 sdhci_init(slot); 524 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 525 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 526 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 527 caps = slot->caps; 528 else 529 caps = RD4(slot, SDHCI_CAPABILITIES); 530 /* Calculate base clock frequency. */ 531 if (slot->version >= SDHCI_SPEC_300) 532 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 533 SDHCI_CLOCK_BASE_SHIFT; 534 else 535 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 536 SDHCI_CLOCK_BASE_SHIFT; 537 if (freq != 0) 538 slot->max_clk = freq * 1000000; 539 /* 540 * If the frequency wasn't in the capabilities and the hardware driver 541 * hasn't already set max_clk we're probably not going to work right 542 * with an assumption, so complain about it. 543 */ 544 if (slot->max_clk == 0) { 545 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 546 device_printf(dev, "Hardware doesn't specify base clock " 547 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 548 } 549 /* Calculate timeout clock frequency. */ 550 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 551 slot->timeout_clk = slot->max_clk / 1000; 552 } else { 553 slot->timeout_clk = 554 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 555 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 556 slot->timeout_clk *= 1000; 557 } 558 /* 559 * If the frequency wasn't in the capabilities and the hardware driver 560 * hasn't already set timeout_clk we'll probably work okay using the 561 * max timeout, but still mention it. 562 */ 563 if (slot->timeout_clk == 0) { 564 device_printf(dev, "Hardware doesn't specify timeout clock " 565 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 566 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 567 } 568 569 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 570 slot->host.f_max = slot->max_clk; 571 slot->host.host_ocr = 0; 572 if (caps & SDHCI_CAN_VDD_330) 573 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 574 if (caps & SDHCI_CAN_VDD_300) 575 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 576 if (caps & SDHCI_CAN_VDD_180) 577 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 578 if (slot->host.host_ocr == 0) { 579 device_printf(dev, "Hardware doesn't report any " 580 "support voltages.\n"); 581 } 582 slot->host.caps = MMC_CAP_4_BIT_DATA; 583 if (caps & SDHCI_CAN_DO_HISPD) 584 slot->host.caps |= MMC_CAP_HSPEED; 585 /* Decide if we have usable DMA. */ 586 if (caps & SDHCI_CAN_DO_DMA) 587 slot->opt |= SDHCI_HAVE_DMA; 588 589 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 590 slot->opt &= ~SDHCI_HAVE_DMA; 591 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 592 slot->opt |= SDHCI_HAVE_DMA; 593 594 /* 595 * Use platform-provided transfer backend 596 * with PIO as a fallback mechanism 597 */ 598 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 599 slot->opt &= ~SDHCI_HAVE_DMA; 600 601 if (bootverbose || sdhci_debug) { 602 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 603 slot->max_clk / 1000000, 604 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 605 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 606 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 607 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 608 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 609 sdhci_dumpregs(slot); 610 } 611 612 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 613 callout_init(&slot->card_callout, 1); 614 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 615 return (0); 616} 617 618void 619sdhci_start_slot(struct sdhci_slot *slot) 620{ 621 sdhci_card_task(slot, 0); 622} 623 624int 625sdhci_cleanup_slot(struct sdhci_slot *slot) 626{ 627 device_t d; 628 629 callout_drain(&slot->timeout_callout); 630 callout_drain(&slot->card_callout); 631 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 632 633 SDHCI_LOCK(slot); 634 d = slot->dev; 635 slot->dev = NULL; 636 SDHCI_UNLOCK(slot); 637 if (d != NULL) 638 device_delete_child(slot->bus, d); 639 640 SDHCI_LOCK(slot); 641 sdhci_reset(slot, SDHCI_RESET_ALL); 642 SDHCI_UNLOCK(slot); 643 bus_dmamap_unload(slot->dmatag, slot->dmamap); 644 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 645 bus_dma_tag_destroy(slot->dmatag); 646 647 SDHCI_LOCK_DESTROY(slot); 648 649 return (0); 650} 651 652int 653sdhci_generic_suspend(struct sdhci_slot *slot) 654{ 655 sdhci_reset(slot, SDHCI_RESET_ALL); 656 657 return (0); 658} 659 660int 661sdhci_generic_resume(struct sdhci_slot *slot) 662{ 663 sdhci_init(slot); 664 665 return (0); 666} 667 668uint32_t 669sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 670{ 671 if (slot->version >= SDHCI_SPEC_300) 672 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 673 else 674 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 675} 676 677int 678sdhci_generic_update_ios(device_t brdev, device_t reqdev) 679{ 680 struct sdhci_slot *slot = device_get_ivars(reqdev); 681 struct mmc_ios *ios = &slot->host.ios; 682 683 SDHCI_LOCK(slot); 684 /* Do full reset on bus power down to clear from any state. */ 685 if (ios->power_mode == power_off) { 686 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 687 sdhci_init(slot); 688 } 689 /* Configure the bus. */ 690 sdhci_set_clock(slot, ios->clock); 691 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 692 if (ios->bus_width == bus_width_4) 693 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 694 else 695 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 696 if (ios->timing == bus_timing_hs) 697 slot->hostctrl |= SDHCI_CTRL_HISPD; 698 else 699 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 700 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 701 /* Some controllers like reset after bus changes. */ 702 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 703 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 704 705 SDHCI_UNLOCK(slot); 706 return (0); 707} 708 709static void 710sdhci_req_done(struct sdhci_slot *slot) 711{ 712 struct mmc_request *req; 713 714 if (slot->req != NULL && slot->curcmd != NULL) { 715 callout_stop(&slot->timeout_callout); 716 req = slot->req; 717 slot->req = NULL; 718 slot->curcmd = NULL; 719 req->done(req); 720 } 721} 722 723static void 724sdhci_timeout(void *arg) 725{ 726 struct sdhci_slot *slot = arg; 727 728 if (slot->curcmd != NULL) { 729 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 730 slot->curcmd->error = MMC_ERR_TIMEOUT; 731 sdhci_req_done(slot); 732 } 733} 734 735static void 736sdhci_set_transfer_mode(struct sdhci_slot *slot, 737 struct mmc_data *data) 738{ 739 uint16_t mode; 740 741 if (data == NULL) 742 return; 743 744 mode = SDHCI_TRNS_BLK_CNT_EN; 745 if (data->len > 512) 746 mode |= SDHCI_TRNS_MULTI; 747 if (data->flags & MMC_DATA_READ) 748 mode |= SDHCI_TRNS_READ; 749 if (slot->req->stop) 750 mode |= SDHCI_TRNS_ACMD12; 751 if (slot->flags & SDHCI_USE_DMA) 752 mode |= SDHCI_TRNS_DMA; 753 754 WR2(slot, SDHCI_TRANSFER_MODE, mode); 755} 756 757static void 758sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 759{ 760 int flags, timeout; 761 uint32_t mask, state; 762 763 slot->curcmd = cmd; 764 slot->cmd_done = 0; 765 766 cmd->error = MMC_ERR_NONE; 767 768 /* This flags combination is not supported by controller. */ 769 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 770 slot_printf(slot, "Unsupported response type!\n"); 771 cmd->error = MMC_ERR_FAILED; 772 sdhci_req_done(slot); 773 return; 774 } 775 776 /* Read controller present state. */ 777 state = RD4(slot, SDHCI_PRESENT_STATE); 778 /* Do not issue command if there is no card, clock or power. 779 * Controller will not detect timeout without clock active. */ 780 if ((state & SDHCI_CARD_PRESENT) == 0 || 781 slot->power == 0 || 782 slot->clock == 0) { 783 cmd->error = MMC_ERR_FAILED; 784 sdhci_req_done(slot); 785 return; 786 } 787 /* Always wait for free CMD bus. */ 788 mask = SDHCI_CMD_INHIBIT; 789 /* Wait for free DAT if we have data or busy signal. */ 790 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 791 mask |= SDHCI_DAT_INHIBIT; 792 /* We shouldn't wait for DAT for stop commands. */ 793 if (cmd == slot->req->stop) 794 mask &= ~SDHCI_DAT_INHIBIT; 795 /* 796 * Wait for bus no more then 250 ms. Typically there will be no wait 797 * here at all, but when writing a crash dump we may be bypassing the 798 * host platform's interrupt handler, and in some cases that handler 799 * may be working around hardware quirks such as not respecting r1b 800 * busy indications. In those cases, this wait-loop serves the purpose 801 * of waiting for the prior command and data transfers to be done, and 802 * SD cards are allowed to take up to 250ms for write and erase ops. 803 * (It's usually more like 20-30ms in the real world.) 804 */ 805 timeout = 250; 806 while (state & mask) { 807 if (timeout == 0) { 808 slot_printf(slot, "Controller never released " 809 "inhibit bit(s).\n"); 810 sdhci_dumpregs(slot); 811 cmd->error = MMC_ERR_FAILED; 812 sdhci_req_done(slot); 813 return; 814 } 815 timeout--; 816 DELAY(1000); 817 state = RD4(slot, SDHCI_PRESENT_STATE); 818 } 819 820 /* Prepare command flags. */ 821 if (!(cmd->flags & MMC_RSP_PRESENT)) 822 flags = SDHCI_CMD_RESP_NONE; 823 else if (cmd->flags & MMC_RSP_136) 824 flags = SDHCI_CMD_RESP_LONG; 825 else if (cmd->flags & MMC_RSP_BUSY) 826 flags = SDHCI_CMD_RESP_SHORT_BUSY; 827 else 828 flags = SDHCI_CMD_RESP_SHORT; 829 if (cmd->flags & MMC_RSP_CRC) 830 flags |= SDHCI_CMD_CRC; 831 if (cmd->flags & MMC_RSP_OPCODE) 832 flags |= SDHCI_CMD_INDEX; 833 if (cmd->data) 834 flags |= SDHCI_CMD_DATA; 835 if (cmd->opcode == MMC_STOP_TRANSMISSION) 836 flags |= SDHCI_CMD_TYPE_ABORT; 837 /* Prepare data. */ 838 sdhci_start_data(slot, cmd->data); 839 /* 840 * Interrupt aggregation: To reduce total number of interrupts 841 * group response interrupt with data interrupt when possible. 842 * If there going to be data interrupt, mask response one. 843 */ 844 if (slot->data_done == 0) { 845 WR4(slot, SDHCI_SIGNAL_ENABLE, 846 slot->intmask &= ~SDHCI_INT_RESPONSE); 847 } 848 /* Set command argument. */ 849 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 850 /* Set data transfer mode. */ 851 sdhci_set_transfer_mode(slot, cmd->data); 852 /* Start command. */ 853 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 854 /* Start timeout callout. */ 855 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot); 856} 857 858static void 859sdhci_finish_command(struct sdhci_slot *slot) 860{ 861 int i; 862 863 slot->cmd_done = 1; 864 /* Interrupt aggregation: Restore command interrupt. 865 * Main restore point for the case when command interrupt 866 * happened first. */ 867 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 868 /* In case of error - reset host and return. */ 869 if (slot->curcmd->error) { 870 sdhci_reset(slot, SDHCI_RESET_CMD); 871 sdhci_reset(slot, SDHCI_RESET_DATA); 872 sdhci_start(slot); 873 return; 874 } 875 /* If command has response - fetch it. */ 876 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 877 if (slot->curcmd->flags & MMC_RSP_136) { 878 /* CRC is stripped so we need one byte shift. */ 879 uint8_t extra = 0; 880 for (i = 0; i < 4; i++) { 881 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 882 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 883 slot->curcmd->resp[3 - i] = val; 884 else { 885 slot->curcmd->resp[3 - i] = 886 (val << 8) | extra; 887 extra = val >> 24; 888 } 889 } 890 } else 891 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 892 } 893 /* If data ready - finish. */ 894 if (slot->data_done) 895 sdhci_start(slot); 896} 897 898static void 899sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 900{ 901 uint32_t target_timeout, current_timeout; 902 uint8_t div; 903 904 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 905 slot->data_done = 1; 906 return; 907 } 908 909 slot->data_done = 0; 910 911 /* Calculate and set data timeout.*/ 912 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 913 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 914 div = 0xE; 915 } else { 916 target_timeout = 1000000; 917 div = 0; 918 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 919 while (current_timeout < target_timeout && div < 0xE) { 920 ++div; 921 current_timeout <<= 1; 922 } 923 /* Compensate for an off-by-one error in the CaFe chip.*/ 924 if (div < 0xE && 925 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 926 ++div; 927 } 928 } 929 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 930 931 if (data == NULL) 932 return; 933 934 /* Use DMA if possible. */ 935 if ((slot->opt & SDHCI_HAVE_DMA)) 936 slot->flags |= SDHCI_USE_DMA; 937 /* If data is small, broken DMA may return zeroes instead of data, */ 938 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 939 (data->len <= 512)) 940 slot->flags &= ~SDHCI_USE_DMA; 941 /* Some controllers require even block sizes. */ 942 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 943 ((data->len) & 0x3)) 944 slot->flags &= ~SDHCI_USE_DMA; 945 /* Load DMA buffer. */ 946 if (slot->flags & SDHCI_USE_DMA) { 947 if (data->flags & MMC_DATA_READ) 948 bus_dmamap_sync(slot->dmatag, slot->dmamap, 949 BUS_DMASYNC_PREREAD); 950 else { 951 memcpy(slot->dmamem, data->data, 952 (data->len < DMA_BLOCK_SIZE) ? 953 data->len : DMA_BLOCK_SIZE); 954 bus_dmamap_sync(slot->dmatag, slot->dmamap, 955 BUS_DMASYNC_PREWRITE); 956 } 957 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 958 /* Interrupt aggregation: Mask border interrupt 959 * for the last page and unmask else. */ 960 if (data->len == DMA_BLOCK_SIZE) 961 slot->intmask &= ~SDHCI_INT_DMA_END; 962 else 963 slot->intmask |= SDHCI_INT_DMA_END; 964 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 965 } 966 /* Current data offset for both PIO and DMA. */ 967 slot->offset = 0; 968 /* Set block size and request IRQ on 4K border. */ 969 WR2(slot, SDHCI_BLOCK_SIZE, 970 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 971 /* Set block count. */ 972 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 973} 974 975void 976sdhci_finish_data(struct sdhci_slot *slot) 977{ 978 struct mmc_data *data = slot->curcmd->data; 979 980 slot->data_done = 1; 981 /* Interrupt aggregation: Restore command interrupt. 982 * Auxiliary restore point for the case when data interrupt 983 * happened first. */ 984 if (!slot->cmd_done) { 985 WR4(slot, SDHCI_SIGNAL_ENABLE, 986 slot->intmask |= SDHCI_INT_RESPONSE); 987 } 988 /* Unload rest of data from DMA buffer. */ 989 if (slot->flags & SDHCI_USE_DMA) { 990 if (data->flags & MMC_DATA_READ) { 991 size_t left = data->len - slot->offset; 992 bus_dmamap_sync(slot->dmatag, slot->dmamap, 993 BUS_DMASYNC_POSTREAD); 994 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 995 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 996 } else 997 bus_dmamap_sync(slot->dmatag, slot->dmamap, 998 BUS_DMASYNC_POSTWRITE); 999 } 1000 /* If there was error - reset the host. */ 1001 if (slot->curcmd->error) { 1002 sdhci_reset(slot, SDHCI_RESET_CMD); 1003 sdhci_reset(slot, SDHCI_RESET_DATA); 1004 sdhci_start(slot); 1005 return; 1006 } 1007 /* If we already have command response - finish. */ 1008 if (slot->cmd_done) 1009 sdhci_start(slot); 1010} 1011 1012static void 1013sdhci_start(struct sdhci_slot *slot) 1014{ 1015 struct mmc_request *req; 1016 1017 req = slot->req; 1018 if (req == NULL) 1019 return; 1020 1021 if (!(slot->flags & CMD_STARTED)) { 1022 slot->flags |= CMD_STARTED; 1023 sdhci_start_command(slot, req->cmd); 1024 return; 1025 } 1026/* We don't need this until using Auto-CMD12 feature 1027 if (!(slot->flags & STOP_STARTED) && req->stop) { 1028 slot->flags |= STOP_STARTED; 1029 sdhci_start_command(slot, req->stop); 1030 return; 1031 } 1032*/ 1033 if (sdhci_debug > 1) 1034 slot_printf(slot, "result: %d\n", req->cmd->error); 1035 if (!req->cmd->error && 1036 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1037 sdhci_reset(slot, SDHCI_RESET_CMD); 1038 sdhci_reset(slot, SDHCI_RESET_DATA); 1039 } 1040 1041 sdhci_req_done(slot); 1042} 1043 1044int 1045sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1046{ 1047 struct sdhci_slot *slot = device_get_ivars(reqdev); 1048 1049 SDHCI_LOCK(slot); 1050 if (slot->req != NULL) { 1051 SDHCI_UNLOCK(slot); 1052 return (EBUSY); 1053 } 1054 if (sdhci_debug > 1) { 1055 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1056 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1057 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1058 (req->cmd->data)?req->cmd->data->flags:0); 1059 } 1060 slot->req = req; 1061 slot->flags = 0; 1062 sdhci_start(slot); 1063 SDHCI_UNLOCK(slot); 1064 if (dumping) { 1065 while (slot->req != NULL) { 1066 sdhci_generic_intr(slot); 1067 DELAY(10); 1068 } 1069 } 1070 return (0); 1071} 1072 1073int 1074sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1075{ 1076 struct sdhci_slot *slot = device_get_ivars(reqdev); 1077 uint32_t val; 1078 1079 SDHCI_LOCK(slot); 1080 val = RD4(slot, SDHCI_PRESENT_STATE); 1081 SDHCI_UNLOCK(slot); 1082 return (!(val & SDHCI_WRITE_PROTECT)); 1083} 1084 1085int 1086sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1087{ 1088 struct sdhci_slot *slot = device_get_ivars(reqdev); 1089 int err = 0; 1090 1091 SDHCI_LOCK(slot); 1092 while (slot->bus_busy) 1093 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1094 slot->bus_busy++; 1095 /* Activate led. */ 1096 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1097 SDHCI_UNLOCK(slot); 1098 return (err); 1099} 1100 1101int 1102sdhci_generic_release_host(device_t brdev, device_t reqdev) 1103{ 1104 struct sdhci_slot *slot = device_get_ivars(reqdev); 1105 1106 SDHCI_LOCK(slot); 1107 /* Deactivate led. */ 1108 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1109 slot->bus_busy--; 1110 SDHCI_UNLOCK(slot); 1111 wakeup(slot); 1112 return (0); 1113} 1114 1115static void 1116sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1117{ 1118 1119 if (!slot->curcmd) { 1120 slot_printf(slot, "Got command interrupt 0x%08x, but " 1121 "there is no active command.\n", intmask); 1122 sdhci_dumpregs(slot); 1123 return; 1124 } 1125 if (intmask & SDHCI_INT_TIMEOUT) 1126 slot->curcmd->error = MMC_ERR_TIMEOUT; 1127 else if (intmask & SDHCI_INT_CRC) 1128 slot->curcmd->error = MMC_ERR_BADCRC; 1129 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1130 slot->curcmd->error = MMC_ERR_FIFO; 1131 1132 sdhci_finish_command(slot); 1133} 1134 1135static void 1136sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1137{ 1138 1139 if (!slot->curcmd) { 1140 slot_printf(slot, "Got data interrupt 0x%08x, but " 1141 "there is no active command.\n", intmask); 1142 sdhci_dumpregs(slot); 1143 return; 1144 } 1145 if (slot->curcmd->data == NULL && 1146 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1147 slot_printf(slot, "Got data interrupt 0x%08x, but " 1148 "there is no active data operation.\n", 1149 intmask); 1150 sdhci_dumpregs(slot); 1151 return; 1152 } 1153 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1154 slot->curcmd->error = MMC_ERR_TIMEOUT; 1155 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1156 slot->curcmd->error = MMC_ERR_BADCRC; 1157 if (slot->curcmd->data == NULL && 1158 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1159 SDHCI_INT_DMA_END))) { 1160 slot_printf(slot, "Got data interrupt 0x%08x, but " 1161 "there is busy-only command.\n", intmask); 1162 sdhci_dumpregs(slot); 1163 slot->curcmd->error = MMC_ERR_INVALID; 1164 } 1165 if (slot->curcmd->error) { 1166 /* No need to continue after any error. */ 1167 if (slot->flags & PLATFORM_DATA_STARTED) { 1168 slot->flags &= ~PLATFORM_DATA_STARTED; 1169 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1170 } else 1171 sdhci_finish_data(slot); 1172 return; 1173 } 1174 1175 /* Handle PIO interrupt. */ 1176 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1177 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1178 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1179 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1180 slot->flags |= PLATFORM_DATA_STARTED; 1181 } else 1182 sdhci_transfer_pio(slot); 1183 } 1184 /* Handle DMA border. */ 1185 if (intmask & SDHCI_INT_DMA_END) { 1186 struct mmc_data *data = slot->curcmd->data; 1187 size_t left; 1188 1189 /* Unload DMA buffer... */ 1190 left = data->len - slot->offset; 1191 if (data->flags & MMC_DATA_READ) { 1192 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1193 BUS_DMASYNC_POSTREAD); 1194 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1195 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1196 } else { 1197 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1198 BUS_DMASYNC_POSTWRITE); 1199 } 1200 /* ... and reload it again. */ 1201 slot->offset += DMA_BLOCK_SIZE; 1202 left = data->len - slot->offset; 1203 if (data->flags & MMC_DATA_READ) { 1204 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1205 BUS_DMASYNC_PREREAD); 1206 } else { 1207 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1208 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1209 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1210 BUS_DMASYNC_PREWRITE); 1211 } 1212 /* Interrupt aggregation: Mask border interrupt 1213 * for the last page. */ 1214 if (left == DMA_BLOCK_SIZE) { 1215 slot->intmask &= ~SDHCI_INT_DMA_END; 1216 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1217 } 1218 /* Restart DMA. */ 1219 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1220 } 1221 /* We have got all data. */ 1222 if (intmask & SDHCI_INT_DATA_END) { 1223 if (slot->flags & PLATFORM_DATA_STARTED) { 1224 slot->flags &= ~PLATFORM_DATA_STARTED; 1225 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1226 } else 1227 sdhci_finish_data(slot); 1228 } 1229} 1230 1231static void 1232sdhci_acmd_irq(struct sdhci_slot *slot) 1233{ 1234 uint16_t err; 1235 1236 err = RD4(slot, SDHCI_ACMD12_ERR); 1237 if (!slot->curcmd) { 1238 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1239 "there is no active command.\n", err); 1240 sdhci_dumpregs(slot); 1241 return; 1242 } 1243 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1244 sdhci_reset(slot, SDHCI_RESET_CMD); 1245} 1246 1247void 1248sdhci_generic_intr(struct sdhci_slot *slot) 1249{ 1250 uint32_t intmask; 1251 1252 SDHCI_LOCK(slot); 1253 /* Read slot interrupt status. */ 1254 intmask = RD4(slot, SDHCI_INT_STATUS); 1255 if (intmask == 0 || intmask == 0xffffffff) { 1256 SDHCI_UNLOCK(slot); 1257 return; 1258 } 1259 if (sdhci_debug > 2) 1260 slot_printf(slot, "Interrupt %#x\n", intmask); 1261 1262 /* Handle card presence interrupts. */ 1263 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1264 WR4(slot, SDHCI_INT_STATUS, intmask & 1265 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1266 1267 if (intmask & SDHCI_INT_CARD_REMOVE) { 1268 if (bootverbose || sdhci_debug) 1269 slot_printf(slot, "Card removed\n"); 1270 callout_stop(&slot->card_callout); 1271 taskqueue_enqueue(taskqueue_swi_giant, 1272 &slot->card_task); 1273 } 1274 if (intmask & SDHCI_INT_CARD_INSERT) { 1275 if (bootverbose || sdhci_debug) 1276 slot_printf(slot, "Card inserted\n"); 1277 callout_reset(&slot->card_callout, hz / 2, 1278 sdhci_card_delay, slot); 1279 } 1280 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1281 } 1282 /* Handle command interrupts. */ 1283 if (intmask & SDHCI_INT_CMD_MASK) { 1284 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1285 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1286 } 1287 /* Handle data interrupts. */ 1288 if (intmask & SDHCI_INT_DATA_MASK) { 1289 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1290 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1291 } 1292 /* Handle AutoCMD12 error interrupt. */ 1293 if (intmask & SDHCI_INT_ACMD12ERR) { 1294 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1295 sdhci_acmd_irq(slot); 1296 } 1297 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1298 intmask &= ~SDHCI_INT_ACMD12ERR; 1299 intmask &= ~SDHCI_INT_ERROR; 1300 /* Handle bus power interrupt. */ 1301 if (intmask & SDHCI_INT_BUS_POWER) { 1302 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1303 slot_printf(slot, 1304 "Card is consuming too much power!\n"); 1305 intmask &= ~SDHCI_INT_BUS_POWER; 1306 } 1307 /* The rest is unknown. */ 1308 if (intmask) { 1309 WR4(slot, SDHCI_INT_STATUS, intmask); 1310 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1311 intmask); 1312 sdhci_dumpregs(slot); 1313 } 1314 1315 SDHCI_UNLOCK(slot); 1316} 1317 1318int 1319sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1320{ 1321 struct sdhci_slot *slot = device_get_ivars(child); 1322 1323 switch (which) { 1324 default: 1325 return (EINVAL); 1326 case MMCBR_IVAR_BUS_MODE: 1327 *result = slot->host.ios.bus_mode; 1328 break; 1329 case MMCBR_IVAR_BUS_WIDTH: 1330 *result = slot->host.ios.bus_width; 1331 break; 1332 case MMCBR_IVAR_CHIP_SELECT: 1333 *result = slot->host.ios.chip_select; 1334 break; 1335 case MMCBR_IVAR_CLOCK: 1336 *result = slot->host.ios.clock; 1337 break; 1338 case MMCBR_IVAR_F_MIN: 1339 *result = slot->host.f_min; 1340 break; 1341 case MMCBR_IVAR_F_MAX: 1342 *result = slot->host.f_max; 1343 break; 1344 case MMCBR_IVAR_HOST_OCR: 1345 *result = slot->host.host_ocr; 1346 break; 1347 case MMCBR_IVAR_MODE: 1348 *result = slot->host.mode; 1349 break; 1350 case MMCBR_IVAR_OCR: 1351 *result = slot->host.ocr; 1352 break; 1353 case MMCBR_IVAR_POWER_MODE: 1354 *result = slot->host.ios.power_mode; 1355 break; 1356 case MMCBR_IVAR_VDD: 1357 *result = slot->host.ios.vdd; 1358 break; 1359 case MMCBR_IVAR_CAPS: 1360 *result = slot->host.caps; 1361 break; 1362 case MMCBR_IVAR_TIMING: 1363 *result = slot->host.ios.timing; 1364 break; 1365 case MMCBR_IVAR_MAX_DATA: 1366 *result = 65535; 1367 break; 1368 } 1369 return (0); 1370} 1371 1372int 1373sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1374{ 1375 struct sdhci_slot *slot = device_get_ivars(child); 1376 1377 switch (which) { 1378 default: 1379 return (EINVAL); 1380 case MMCBR_IVAR_BUS_MODE: 1381 slot->host.ios.bus_mode = value; 1382 break; 1383 case MMCBR_IVAR_BUS_WIDTH: 1384 slot->host.ios.bus_width = value; 1385 break; 1386 case MMCBR_IVAR_CHIP_SELECT: 1387 slot->host.ios.chip_select = value; 1388 break; 1389 case MMCBR_IVAR_CLOCK: 1390 if (value > 0) { 1391 uint32_t max_clock; 1392 uint32_t clock; 1393 int i; 1394 1395 max_clock = slot->max_clk; 1396 clock = max_clock; 1397 1398 if (slot->version < SDHCI_SPEC_300) { 1399 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1400 i <<= 1) { 1401 if (clock <= value) 1402 break; 1403 clock >>= 1; 1404 } 1405 } 1406 else { 1407 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1408 i += 2) { 1409 if (clock <= value) 1410 break; 1411 clock = max_clock / (i + 2); 1412 } 1413 } 1414 1415 slot->host.ios.clock = clock; 1416 } else 1417 slot->host.ios.clock = 0; 1418 break; 1419 case MMCBR_IVAR_MODE: 1420 slot->host.mode = value; 1421 break; 1422 case MMCBR_IVAR_OCR: 1423 slot->host.ocr = value; 1424 break; 1425 case MMCBR_IVAR_POWER_MODE: 1426 slot->host.ios.power_mode = value; 1427 break; 1428 case MMCBR_IVAR_VDD: 1429 slot->host.ios.vdd = value; 1430 break; 1431 case MMCBR_IVAR_TIMING: 1432 slot->host.ios.timing = value; 1433 break; 1434 case MMCBR_IVAR_CAPS: 1435 case MMCBR_IVAR_HOST_OCR: 1436 case MMCBR_IVAR_F_MIN: 1437 case MMCBR_IVAR_F_MAX: 1438 case MMCBR_IVAR_MAX_DATA: 1439 return (EINVAL); 1440 } 1441 return (0); 1442} 1443 1444MODULE_VERSION(sdhci, 1); 1445