ti_sdhci.c revision 266751
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/arm/ti/ti_sdhci.c 266751 2014-05-27 15:30:24Z ian $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/gpio.h> 35#include <sys/kernel.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/resource.h> 39#include <sys/rman.h> 40#include <sys/taskqueue.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <machine/intr.h> 45 46#include <dev/fdt/fdt_common.h> 47#include <dev/ofw/ofw_bus.h> 48#include <dev/ofw/ofw_bus_subr.h> 49 50#include <dev/mmc/bridge.h> 51#include <dev/mmc/mmcreg.h> 52#include <dev/mmc/mmcbrvar.h> 53 54#include <dev/sdhci/sdhci.h> 55#include "sdhci_if.h" 56 57#include <arm/ti/ti_cpuid.h> 58#include <arm/ti/ti_prcm.h> 59#include "gpio_if.h" 60 61struct ti_sdhci_softc { 62 device_t dev; 63 device_t gpio_dev; 64 struct resource * mem_res; 65 struct resource * irq_res; 66 void * intr_cookie; 67 struct sdhci_slot slot; 68 uint32_t mmchs_device_id; 69 uint32_t mmchs_reg_off; 70 uint32_t sdhci_reg_off; 71 uint32_t baseclk_hz; 72 uint32_t wp_gpio_pin; 73 uint32_t cmd_and_mode; 74 uint32_t sdhci_clkdiv; 75 boolean_t disable_highspeed; 76 boolean_t force_card_present; 77}; 78 79/* 80 * Table of supported FDT compat strings. 81 * 82 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 83 * of the documented names. 84 * 85 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 86 */ 87static struct ofw_compat_data compat_data[] = { 88 {"ti,omap3-hsmmc", 1}, 89 {"ti,omap4-hsmmc", 1}, 90 {"ti,mmchs", 1}, 91 {NULL, 0}, 92}; 93 94/* 95 * The MMCHS hardware has a few control and status registers at the beginning of 96 * the device's memory map, followed by the standard sdhci register block. 97 * Different SoCs have the register blocks at different offsets from the 98 * beginning of the device. Define some constants to map out the registers we 99 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 100 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 101 */ 102#define OMAP3_MMCHS_REG_OFFSET 0x000 103#define OMAP4_MMCHS_REG_OFFSET 0x100 104#define AM335X_MMCHS_REG_OFFSET 0x100 105#define SDHCI_REG_OFFSET 0x100 106 107#define MMCHS_SYSCONFIG 0x010 108#define MMCHS_SYSCONFIG_RESET (1 << 1) 109#define MMCHS_SYSSTATUS 0x014 110#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 111#define MMCHS_CON 0x02C 112#define MMCHS_CON_DW8 (1 << 5) 113#define MMCHS_CON_DVAL_8_4MS (3 << 9) 114#define MMCHS_SYSCTL 0x12C 115#define MMCHS_SYSCTL_CLKD_MASK 0x3FF 116#define MMCHS_SYSCTL_CLKD_SHIFT 6 117#define MMCHS_SD_CAPA 0x140 118#define MMCHS_SD_CAPA_VS18 (1 << 26) 119#define MMCHS_SD_CAPA_VS30 (1 << 25) 120#define MMCHS_SD_CAPA_VS33 (1 << 24) 121 122static inline uint32_t 123ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 124{ 125 126 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 127} 128 129static inline void 130ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 131{ 132 133 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 134} 135 136static inline uint32_t 137RD4(struct ti_sdhci_softc *sc, bus_size_t off) 138{ 139 140 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 141} 142 143static inline void 144WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 145{ 146 147 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 148} 149 150static uint8_t 151ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 152{ 153 struct ti_sdhci_softc *sc = device_get_softc(dev); 154 155 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 156} 157 158static uint16_t 159ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 160{ 161 struct ti_sdhci_softc *sc = device_get_softc(dev); 162 uint32_t clkdiv, val32; 163 164 /* 165 * The MMCHS hardware has a non-standard interpretation of the sdclock 166 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 167 * but doesn't split them into low:high fields. Instead they're a 168 * single number in the range 0..1023 and the number is exactly the 169 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 170 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 171 * here extracts the MMCHS representation from the hardware word, cleans 172 * those bits out, applies the 2N adjustment, and plugs the result into 173 * the bit positions for the 2.0 or 3.0 divisor in the returned register 174 * value. The ti_sdhci_write_2() routine performs the opposite 175 * transformation when the SDHCI driver writes to the register. 176 */ 177 if (off == SDHCI_CLOCK_CONTROL) { 178 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 179 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 180 MMCHS_SYSCTL_CLKD_MASK) / 2; 181 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 182 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 183 if (slot->version >= SDHCI_SPEC_300) 184 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 185 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 186 return (val32 & 0xffff); 187 } 188 189 /* 190 * Standard 32-bit handling of command and transfer mode. 191 */ 192 if (off == SDHCI_TRANSFER_MODE) { 193 return (sc->cmd_and_mode >> 16); 194 } else if (off == SDHCI_COMMAND_FLAGS) { 195 return (sc->cmd_and_mode & 0x0000ffff); 196 } 197 198 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 199} 200 201static uint32_t 202ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 203{ 204 struct ti_sdhci_softc *sc = device_get_softc(dev); 205 uint32_t val32; 206 207 val32 = RD4(sc, off); 208 209 /* 210 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 211 * that flag from the returned capabilities. 212 */ 213 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 214 val32 &= ~SDHCI_CAN_DO_HISPD; 215 216 /* 217 * Force the card-present state if necessary. 218 */ 219 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 220 val32 |= SDHCI_CARD_PRESENT; 221 222 return (val32); 223} 224 225static void 226ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 227 uint32_t *data, bus_size_t count) 228{ 229 struct ti_sdhci_softc *sc = device_get_softc(dev); 230 231 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 232} 233 234static void 235ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 236 uint8_t val) 237{ 238 struct ti_sdhci_softc *sc = device_get_softc(dev); 239 uint32_t val32; 240 241 val32 = RD4(sc, off & ~3); 242 val32 &= ~(0xff << (off & 3) * 8); 243 val32 |= (val << (off & 3) * 8); 244 245 WR4(sc, off & ~3, val32); 246} 247 248static void 249ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 250 uint16_t val) 251{ 252 struct ti_sdhci_softc *sc = device_get_softc(dev); 253 uint32_t clkdiv, val32; 254 255 /* 256 * Translate between the hardware and SDHCI 2.0 or 3.0 representations 257 * of the clock divisor. See the comments in ti_sdhci_read_2() for 258 * details. 259 */ 260 if (off == SDHCI_CLOCK_CONTROL) { 261 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 262 if (slot->version >= SDHCI_SPEC_300) 263 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 264 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 265 clkdiv *= 2; 266 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 267 clkdiv = MMCHS_SYSCTL_CLKD_MASK; 268 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 269 val32 &= 0xffff0000; 270 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 271 MMCHS_SYSCTL_CLKD_SHIFT); 272 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 273 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 274 return; 275 } 276 277 /* 278 * Standard 32-bit handling of command and transfer mode. 279 */ 280 if (off == SDHCI_TRANSFER_MODE) { 281 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 282 ((uint32_t)val & 0x0000ffff); 283 return; 284 } else if (off == SDHCI_COMMAND_FLAGS) { 285 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 286 ((uint32_t)val << 16); 287 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 288 return; 289 } 290 291 val32 = RD4(sc, off & ~3); 292 val32 &= ~(0xffff << (off & 3) * 8); 293 val32 |= ((val & 0xffff) << (off & 3) * 8); 294 WR4(sc, off & ~3, val32); 295} 296 297static void 298ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 299 uint32_t val) 300{ 301 struct ti_sdhci_softc *sc = device_get_softc(dev); 302 303 WR4(sc, off, val); 304} 305 306static void 307ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 308 uint32_t *data, bus_size_t count) 309{ 310 struct ti_sdhci_softc *sc = device_get_softc(dev); 311 312 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 313} 314 315static void 316ti_sdhci_intr(void *arg) 317{ 318 struct ti_sdhci_softc *sc = arg; 319 320 sdhci_generic_intr(&sc->slot); 321} 322 323static int 324ti_sdhci_update_ios(device_t brdev, device_t reqdev) 325{ 326 struct ti_sdhci_softc *sc = device_get_softc(brdev); 327 struct sdhci_slot *slot; 328 struct mmc_ios *ios; 329 uint32_t val32; 330 331 slot = device_get_ivars(reqdev); 332 ios = &slot->host.ios; 333 334 /* 335 * There is an 8-bit-bus bit in the MMCHS control register which, when 336 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 337 * registers. Set that bit first according to whether an 8-bit bus is 338 * requested, then let the standard driver handle everything else. 339 */ 340 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 341 if (ios->bus_width == bus_width_8) 342 ti_mmchs_write_4(sc, MMCHS_CON, val32 | MMCHS_CON_DW8); 343 else 344 ti_mmchs_write_4(sc, MMCHS_CON, val32 & ~MMCHS_CON_DW8); 345 346 return (sdhci_generic_update_ios(brdev, reqdev)); 347} 348 349static int 350ti_sdhci_get_ro(device_t brdev, device_t reqdev) 351{ 352 struct ti_sdhci_softc *sc = device_get_softc(brdev); 353 unsigned int readonly = 0; 354 355 /* If a gpio pin is configured, read it. */ 356 if (sc->gpio_dev != NULL) { 357 GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 358 } 359 360 return (readonly); 361} 362 363static int 364ti_sdhci_detach(device_t dev) 365{ 366 367 return (EBUSY); 368} 369 370static void 371ti_sdhci_hw_init(device_t dev) 372{ 373 struct ti_sdhci_softc *sc = device_get_softc(dev); 374 clk_ident_t clk; 375 uint32_t regval; 376 unsigned long timeout; 377 378 /* Enable the controller and interface/functional clocks */ 379 clk = MMC0_CLK + sc->mmchs_device_id; 380 if (ti_prcm_clk_enable(clk) != 0) { 381 device_printf(dev, "Error: failed to enable MMC clock\n"); 382 return; 383 } 384 385 /* Get the frequency of the source clock */ 386 if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) { 387 device_printf(dev, "Error: failed to get source clock freq\n"); 388 return; 389 } 390 391 /* Issue a softreset to the controller */ 392 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 393 timeout = 1000; 394 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & MMCHS_SYSSTATUS_RESETDONE)) { 395 if (--timeout == 0) { 396 device_printf(dev, "Error: Controller reset operation timed out\n"); 397 break; 398 } 399 DELAY(100); 400 } 401 402 /* Reset both the command and data state machines */ 403 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 404 timeout = 1000; 405 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) { 406 if (--timeout == 0) { 407 device_printf(dev, "Error: Software reset operation timed out\n"); 408 break; 409 } 410 DELAY(100); 411 } 412 413 /* 414 * The attach() routine has examined fdt data and set flags in 415 * slot.host.caps to reflect what voltages we can handle. Set those 416 * values in the CAPA register. The manual says that these values can 417 * only be set once, "before initialization" whatever that means, and 418 * that they survive a reset. So maybe doing this will be a no-op if 419 * u-boot has already initialized the hardware. 420 */ 421 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 422 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 423 regval |= MMCHS_SD_CAPA_VS18; 424 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 425 regval |= MMCHS_SD_CAPA_VS30; 426 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 427 428 /* Set initial host configuration (1-bit, std speed, pwr off). */ 429 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 430 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 431 432 /* Set the initial controller configuration. */ 433 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 434} 435 436static int 437ti_sdhci_attach(device_t dev) 438{ 439 struct ti_sdhci_softc *sc = device_get_softc(dev); 440 int rid, err; 441 pcell_t prop; 442 phandle_t node; 443 444 sc->dev = dev; 445 446 /* 447 * Get the MMCHS device id from FDT. If it's not there use the newbus 448 * unit number (which will work as long as the devices are in order and 449 * none are skipped in the fdt). Note that this is a property we made 450 * up and added in freebsd, it doesn't exist in the published bindings. 451 */ 452 node = ofw_bus_get_node(dev); 453 if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) { 454 sc->mmchs_device_id = device_get_unit(dev); 455 device_printf(dev, "missing mmchs-device-id attribute in FDT, " 456 "using unit number (%d)", sc->mmchs_device_id); 457 } else 458 sc->mmchs_device_id = fdt32_to_cpu(prop); 459 460 /* 461 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 462 * device, and only 1p8v on other devices unless an external transceiver 463 * is used. The only way we could know about a transceiver is fdt data. 464 * Note that we have to do this before calling ti_sdhci_hw_init() so 465 * that it can set the right values in the CAPA register, which can only 466 * be done once and never reset. 467 */ 468 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 469 if (sc->mmchs_device_id == 0 || OF_hasprop(node, "ti,dual-volt")) { 470 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 471 } 472 473 /* 474 * See if we've got a GPIO-based write detect pin. This is not the 475 * standard documented property for this, we added it in freebsd. 476 */ 477 if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 478 sc->wp_gpio_pin = 0xffffffff; 479 else 480 sc->wp_gpio_pin = fdt32_to_cpu(prop); 481 482 if (sc->wp_gpio_pin != 0xffffffff) { 483 sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 484 if (sc->gpio_dev == NULL) 485 device_printf(dev, "Error: No GPIO device, " 486 "Write Protect pin will not function\n"); 487 else 488 GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 489 GPIO_PIN_INPUT); 490 } 491 492 /* 493 * Set the offset from the device's memory start to the MMCHS registers. 494 * Also for OMAP4 disable high speed mode due to erratum ID i626. 495 */ 496 if (ti_chip() == CHIP_OMAP_3) 497 sc->mmchs_reg_off = OMAP3_MMCHS_REG_OFFSET; 498 else if (ti_chip() == CHIP_OMAP_4) { 499 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 500 sc->disable_highspeed = true; 501 } else if (ti_chip() == CHIP_AM335X) 502 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 503 else 504 panic("Unknown OMAP device\n"); 505 506 /* 507 * The standard SDHCI registers are at a fixed offset (the same on all 508 * SoCs) beyond the MMCHS registers. 509 */ 510 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 511 512 /* Resource setup. */ 513 rid = 0; 514 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 515 RF_ACTIVE); 516 if (!sc->mem_res) { 517 device_printf(dev, "cannot allocate memory window\n"); 518 err = ENXIO; 519 goto fail; 520 } 521 522 rid = 0; 523 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 524 RF_ACTIVE); 525 if (!sc->irq_res) { 526 device_printf(dev, "cannot allocate interrupt\n"); 527 err = ENXIO; 528 goto fail; 529 } 530 531 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 532 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 533 device_printf(dev, "cannot setup interrupt handler\n"); 534 err = ENXIO; 535 goto fail; 536 } 537 538 /* Initialise the MMCHS hardware. */ 539 ti_sdhci_hw_init(dev); 540 541 /* 542 * The capabilities register can only express base clock frequencies in 543 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 544 * faster than that, the hardware sets the frequency to zero in the 545 * register. When the register contains zero, the sdhci driver expects 546 * slot.max_clk to already have the right value in it. 547 */ 548 sc->slot.max_clk = sc->baseclk_hz; 549 550 /* 551 * The MMCHS timeout counter is based on the output sdclock. Tell the 552 * sdhci driver to recalculate the timeout clock whenever the output 553 * sdclock frequency changes. 554 */ 555 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 556 557 /* 558 * The MMCHS hardware shifts the 136-bit response data (in violation of 559 * the spec), so tell the sdhci driver not to do the same in software. 560 */ 561 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 562 563 /* 564 * DMA is not really broken, I just haven't implemented it yet. 565 */ 566 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 567 568 /* 569 * Set up the hardware and go. Note that this sets many of the 570 * slot.host.* fields, so we have to do this before overriding any of 571 * those values based on fdt data, below. 572 */ 573 sdhci_init_slot(dev, &sc->slot, 0); 574 575 /* 576 * The SDHCI controller doesn't realize it, but we can support 8-bit 577 * even though we're not a v3.0 controller. If there's an fdt bus-width 578 * property, honor it. 579 */ 580 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 581 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 582 MMC_CAP_8_BIT_DATA); 583 switch (prop) { 584 case 8: 585 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 586 /* FALLTHROUGH */ 587 case 4: 588 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 589 break; 590 case 1: 591 break; 592 default: 593 device_printf(dev, "Bad bus-width value %u\n", prop); 594 break; 595 } 596 } 597 598 /* 599 * If the slot is flagged with the non-removable property, set our flag 600 * to always force the SDHCI_CARD_PRESENT bit on. 601 */ 602 node = ofw_bus_get_node(dev); 603 if (OF_hasprop(node, "non-removable")) 604 sc->force_card_present = true; 605 606 bus_generic_probe(dev); 607 bus_generic_attach(dev); 608 609 sdhci_start_slot(&sc->slot); 610 611 return (0); 612 613fail: 614 if (sc->intr_cookie) 615 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 616 if (sc->irq_res) 617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 618 if (sc->mem_res) 619 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 620 621 return (err); 622} 623 624static int 625ti_sdhci_probe(device_t dev) 626{ 627 628 if (!ofw_bus_status_okay(dev)) 629 return (ENXIO); 630 631 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 632 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 633 return (BUS_PROBE_DEFAULT); 634 } 635 636 return (ENXIO); 637} 638 639static device_method_t ti_sdhci_methods[] = { 640 /* Device interface */ 641 DEVMETHOD(device_probe, ti_sdhci_probe), 642 DEVMETHOD(device_attach, ti_sdhci_attach), 643 DEVMETHOD(device_detach, ti_sdhci_detach), 644 645 /* Bus interface */ 646 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 647 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 648 DEVMETHOD(bus_print_child, bus_generic_print_child), 649 650 /* MMC bridge interface */ 651 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 652 DEVMETHOD(mmcbr_request, sdhci_generic_request), 653 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 654 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 655 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 656 657 /* SDHCI registers accessors */ 658 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 659 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 660 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 661 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 662 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 663 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 664 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 665 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 666 667 DEVMETHOD_END 668}; 669 670static devclass_t ti_sdhci_devclass; 671 672static driver_t ti_sdhci_driver = { 673 "sdhci_ti", 674 ti_sdhci_methods, 675 sizeof(struct ti_sdhci_softc), 676}; 677 678DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 679MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 680