330938 |
14-Mar-2018 |
jhb |
Convert pci_delete_child() to a bus_child_deleted() method.
Instead of providing a wrapper around device_delete_child() that the PCI bus and child bus drivers must call explicitly, move the bulk of the logic from pci_delete_child() into a bus_child_deleted() method (pci_child_deleted()). This allows PCI devices to be safely deleted via device_delete_child(). - Add a bus_child_deleted method to the ACPI PCI bus which clears the device_t associated with the corresponding ACPI handle in addition to the normal PCI bus cleanup. - Change cardbus_detach_card to call device_delete_children() and move CardBus-specific delete logic into a new cardbus_child_deleted() method. - Use device_delete_child() instead of pci_delete_child() in the SRIOV code. - Add a bus_child_deleted method to the OpenFirmware PCI bus drivers which frees the OpenFirmware device info for each PCI device.
To preserve KBI, a pci_delete_child() function is left in place that just calls device_delete_child().
PR: 226562 Requested by: dexuan |
318273 |
14-May-2017 |
marius |
MFC: r317578
Fix a bug introduced as part of r287726 (MFCed to stable/10 in r292789); use the right device_t for determining the softc of the bridge in psycho_route_interrupt(). [1] While at it, update the corresponding comment that the code in question is also necessary for U30s in addition to E450s (a fact that has been known for ages).
PR: 218478 [1] Submitted by: Yoshihiko Iwama [1] |
305615 |
08-Sep-2016 |
pfg |
MFC r303891, r303892: sys: replace comma with semicolon when pertinent.
Uses of commas instead of a semicolons can easily go undetected. The comma can serve as a statement separator but this shouldn't be abused when statements are meant to be standalone. |
292789 |
27-Dec-2015 |
marius |
MFC: r287726
- Factor out the common and generic parts of the sparc64 host-PCI-bridge drivers into the revived sys/sparc64/pci/ofw_pci.c, previously already serving a similar purpose. This has been done with sun4v in mind, which explains a) the otherwise not that obvious scheme employed and b) why reusing sys/powerpc/ofw/ofw_pci.c was even lesser an option. - Add a workaround for QEMU once again not emulating real machines, in this case by not providing the OFW_PCI_CS_MEM64 range. [1]
Submitted by: jhb [1] |
284455 |
16-Jun-2015 |
emaste |
MFC r281930 by jhb:
Update this driver to not save copies of registers that are no longer used after r281874. While here, also update it to always write the parent's PCI bus number to the primary bus register. |
280970 |
01-Apr-2015 |
jhb |
MFC 261790: Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386.
PR: 197076 |
266020 |
14-May-2014 |
ian |
MFC r258800, r258802, r258805, r258806, r258807, r258851, r258857, r259199, r259484, r259513, r259514, r259516
The kernel stack guard pages are only below the stack pointer, not above.
Remove unnecessary double-setting of the thread's onfault state in copyinstr().
Open Firmware mandates that certain cross-references, in particular those in /chosen, be ihandles. The ePAPR spec makes those cross-reference phandles, since FDT has no concept of ihandles. Have the OF FDT CI module interpret queries about ihandles as cross-reference phandles.
Real OF systems have an ihandle under /chosen/stdout, not a phandle. Use the right type.
Rearchitect platform memory map parsing to make it less Open Firmware-centric.
Remove fdtbus_bs_tag definition, which is now obsolete. The remainder of this file is also slated for future demolition.
Return the correct IEEE 1275 code for "nextprop".
Use the common Open Firmware PCI interrupt routing code instead of the duplicate version in dev/fdt.
Configure interrupt sense based on device tree information.
Simplify the ofw_bus_lookup_imap() API slightly: make it allocate maskbuf internally instead of requiring the caller to allocate it. |
263763 |
26-Mar-2014 |
dim |
MFC r262613:
Merge the projects/clang-sparc64 branch back to head. This brings in several updates from the llvm and clang trunks to make the sparc64 backend fully functional.
Apart from one patch to sys/sparc64/include/pcpu.h which is still under discussion, this makes it possible to let clang fully build world and kernel for sparc64.
Any assistance with testing this on actual sparc64 hardware is greatly appreciated, as there will unavoidably be bugs left.
Many thanks go to Roman Divacky for his upstream work on getting the sparc64 backend into shape.
MFC r262985:
Repair a few minor mismerges from r262261 in the clang-sparc64 project branch. This is also to minimize differences with upstream. |
262621 |
28-Feb-2014 |
dim |
MFC r262472:
Make sure a for loop in fire_alloc_msix() terminates, by making the loop counter signed.
Reviewed by: marius |
256281 |
10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
|
248965 |
01-Apr-2013 |
ian |
Fix low-level uart drivers that set their fifo sizes in the softc too late.
uart(4) allocates send and receiver buffers in attach() before it calls the low-level driver's attach routine. Many low-level drivers set the fifo sizes in their attach routine, which is too late. Other drivers set them in the probe() routine, so that they're available when uart(4) allocates buffers. This fixes the ones that were setting the values too late by moving the code to probe().
|
247914 |
07-Mar-2013 |
gavin |
Correct two spelling mistakes in a comment.
|
247620 |
02-Mar-2013 |
marius |
Revert the part of r247600 which turned the overtemperature and power fail interrupt shutdown handlers into filters. Shutdown_nice(9) acquires a sleep lock, which filters shouldn't do. It also seems that kern_reboot(9) still may require Giant to be hold.
Submitted by: bde
|
247600 |
02-Mar-2013 |
marius |
- While Netra X1 generally show no ill effects when registering a power fail interrupt handler, there seems to be either a broken batch of them or a tendency to develop a defect which causes this interrupt to fire inadvertedly. Given that apart from this problem these machines work just fine, add a tunable allowing the setup of the power fail interrupt to be disabled. While at it, remove the DEBUGGER_ON_POWERFAIL compile time option and make that behavior also selectable via the newly added tunable. - Apparently, it's no longer a problem to call shutdown_nice(9) from within an interrupt filter (some other drivers in the tree do the same). So change the power fail interrupt from an handler in order to simplify the code and get rid of a !INTR_MPSAFE handler. - Use NULL instead of 0 for pointers.
MFC after: 1 week
|
247574 |
01-Mar-2013 |
marius |
- In sbbc_pci_attach() just pass the already obtained bus tag and handle instead of acquiring these anew. - Use NULL instead of 0 for pointers.
MFC after: 1 week
|
247573 |
01-Mar-2013 |
marius |
- Remove an unused header. - Use NULL instead of 0 for pointers. - Let ofw_pcib_probe() return BUS_PROBE_DEFAULT instead of 0 so specialized PCI-PCI-bridge drivers may attach instead. - Add WARs for PLX Technology PEX 8114 bridges and PEX 8532 switches. Ideally, these should live in MI code but at least for the latter we're missing the necessary infrastructure there.
MFC after: 1 week
|
242625 |
05-Nov-2012 |
dim |
Remove duplicate const specifiers in many drivers (I hope I got all of them, please let me know if not). Most of these are of the form:
static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] };
The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata).
I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files).
Reviewed by: yongari, marius MFC after: 1 week
|
239941 |
31-Aug-2012 |
marius |
Add a global MD macro for the VIS block size instead of duplicating it and using magic values all over the place.
MFC after: 1 week
|
233701 |
30-Mar-2012 |
marius |
- Remove erroneous trailing semicolon. [1] - Correctly determine the maximum payload size for setting the TX link frequent NACK latency and replay timer thresholds.
Submitted by: stefanf [1] MFC after: 3 days
|
233421 |
24-Mar-2012 |
marius |
Given that this is a host-PCI-Express bridge driver, create the parent DMA tag with a 4 GB boundary as required by PCI-Express. With r232403 in place this actually is redundant. However, the host-PCI-Express bridge driver is the more appropriate place for implementing this restriction.
MFC after: 3 days
|
233018 |
15-Mar-2012 |
nwhitehorn |
Make ofw_bus_get_node() consistently return -1 when there is no associated OF node, instead of a random mixture of 0 and -1. Update all checks for 0 to check for -1 instead.
MFC after: 4 weeks
|
232403 |
02-Mar-2012 |
jhb |
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines.
MFC after: 2 weeks
|
230664 |
28-Jan-2012 |
marius |
As it turns out r227960 may still be insufficient with PREEMPTION so try harder to get the CDMA sync interrupt delivered and also in a more efficient way: - wrap the whole process of sending and receiving the CDMA sync interrupt in a critical section so we don't get preempted, - send the CDMA sync interrupt to the CPU that is actually waiting for it to happen so we don't take a detour via another CPU, - instead of waiting for up to 15 seconds for the interrupt to trigger try the whole process for up to 15 times using a one second timeout (the code was also changed to just ignore belated interrupts of a previous tries should they appear).
According to testing done by Peter Jeremy with the debugging also added as part of this commit the first two changes apparently are sufficient to now properly get the CDMA sync interrupts delivered at the first try though.
|
227960 |
25-Nov-2011 |
marius |
Increase the CDMA sync timeout for Schizo bridges to 15 seconds as used by OpenSolaris. One second turned out to be not enough for certain loads while 10 seconds were sufficient. Reported by: Peter Jeremy
MFC after: 3 days
|
227848 |
22-Nov-2011 |
marius |
s,KOBJMETHOD_END,DEVMETHOD_END,g in order to fully hide the explicit mention of kobj(9) from device drivers.
|
227843 |
22-Nov-2011 |
marius |
- There's no need to overwrite the default device method with the default one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
|
225931 |
02-Oct-2011 |
marius |
Make sparc64 compatible with NEW_PCIB and enable it: - Implement bus_adjust_resource() methods as far as necessary and in non-PCI bridge drivers as far as feasible without rototilling them. - As NEW_PCIB does a layering violation by activating resources at layers above pci(4) without previously bubbling up their allocation there, move the assignment of bus tags and handles from the bus_alloc_resource() to the bus_activate_resource() methods like at least the other NEW_PCIB enabled architectures do. This is somewhat unfortunate as previously sparc64 (ab)used resource activation to indicate whether SYS_RES_MEMORY resources should be mapped into KVA, which is only necessary if their going to be accessed via the pointer returned from rman_get_virtual() but not for bus_space(9) as the later always uses physical access on sparc64. Besides wasting KVA if we always map in SYS_RES_MEMORY resources, a driver also may deliberately not map them in if the firmware already has done so, possibly in a special way. So in order to still allow a driver to decide whether a SYS_RES_MEMORY resource should be mapped into KVA we let it indicate that by calling bus_space_map(9) with BUS_SPACE_MAP_LINEAR as actually documented in the bus_space(9) page. This is implemented by allocating a separate bus tag per SYS_RES_MEMORY resource and passing the resource via the previously unused bus tag cookie so we later on can call rman_set_virtual() in sparc64_bus_mem_map(). As a side effect this now also allows to actually indicate that a SYS_RES_MEMORY resource should be mapped in as cacheable and/or read-only via BUS_SPACE_MAP_CACHEABLE and BUS_SPACE_MAP_READONLY respectively. - Do some minor cleanup like taking advantage of rman_init_from_resource(), factor out the common part of bus tag allocation into a newly added sparc64_alloc_bus_tag(), hook up some missing newbus methods and replace some homegrown versions with the generic counterparts etc. - While at it, let apb_attach() (which can't use the generic NEW_PCIB code as APB bridges just don't have the base and limit registers implemented) regarding the config space registers cached in pcib_softc and the SYSCTL reporting nodes set up.
|
225891 |
01-Oct-2011 |
marius |
Re-reading the Schizo errata suggests that it's actually tolerable to also use the streaming buffer of pre version 5/revision 2.3 hardware as long as we stay away from context flushes (which iommu(4) so far doesn't take advantage of). OpenSolaris does the same.
|
223960 |
12-Jul-2011 |
marius |
- Current testing shows that (ab)using the JBC performance counter in bus cycle mode as timecounter just works fine. My best guess is that a firmware update has fixed this, check at run-time whether it advances and use a positive quality if it does. The latter will cause this timecounter to be used instead of the tick counter based one, which just sucks for SMP. - Remove a redundant NULL assignment from the timecounter initialization.
|
223959 |
12-Jul-2011 |
marius |
- Add a missing shift in schizo_get_timecount(). This happened to be non-fatal as STX_CTRL_PERF_CNT_CNT0_SHIFT actually is zero, if we were using the second counter in the upper 32 bits this would be required though as the MI timecounter code doesn't support 64-bit counters/counter registers. - Remove a redundant NULL assignment from the timecounter initialization.
|
221393 |
03-May-2011 |
jhb |
Reimplement how PCI-PCI bridges manage their I/O windows. Previously the driver would verify that requests for child devices were confined to any existing I/O windows, but the driver relied on the firmware to initialize the windows and would never grow the windows for new requests. Now the driver actively manages the I/O windows.
This is implemented by allocating a bus resource for each I/O window from the parent PCI bus and suballocating that resource to child devices. The suballocations are managed by creating an rman for each I/O window. The suballocated resources are mapped by passing the bus_activate_resource() call up to the parent PCI bus. Windows are grown when needed by using bus_adjust_resource() to adjust the resource allocated from the parent PCI bus. If the adjust request succeeds, the window is adjusted and the suballocation request for the child device is retried.
When growing a window, the rman_first_free_region() and rman_last_free_region() routines are used to determine if the front or end of the existing I/O window is free. From using that, the smallest ranges that need to be added to either the front or back of the window are computed. The driver will first try to grow the window in whichever direction requires the smallest growth first followed by the other direction if that fails.
Subtractive bridges will first attempt to satisfy requests for child resources from I/O windows (including attempts to grow the windows). If that fails, the request is passed up to the parent PCI bus directly however.
The PCI-PCI bridge driver will try to use firmware-assigned ranges for child BARs first and only allocate a "fresh" range if that specific range cannot be accommodated in the I/O window. This allows systems where the firmware assigns resources during boot but later wipes the I/O windows (some ACPI BIOSen are known to do this) to "rediscover" the original I/O window ranges.
The ACPI Host-PCI bridge driver has been adjusted to correctly honor hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge makes a wildcard request for an I/O window range.
The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option is enabled. This is a transition aide to allow platforms that do not yet support bus_activate_resource() and bus_adjust_resource() in their Host-PCI bridge drivers (and possibly other drivers as needed) to use the old driver for now. Once all platforms support the new driver, the kernel option and old driver will be removed.
PR: kern/143874 kern/149306 Tested by: mav
|
220147 |
29-Mar-2011 |
marius |
Allocate memory for a DMA method table only in case we need to override the iommu(4) provided one, i.e. in case of Hummingbird and Sabre bridges, otherwise just use the iommu(4) one. This also fixes a bug introduced in r220039 which caused an empty DMA method table to be used for the second of a pair of Psycho bridges.
|
220039 |
26-Mar-2011 |
marius |
- A closer inspection of the OpenSolaris code indicates that the DMA syncing for Hummingbird and Sabre bridges should be applied with every BUS_DMASYNC_POSTREAD instead of in a wrapper around interrupt handlers for devices behind PCI-PCI bridges only as suggested by the documentation (code for the latter actually exists in OpenSolaris but is disabled by default), which also makes more sense. - Take advantage of the ofw_pci_setup_device method introduced in r220038 for disabling bus parking for certain EBus bridges in order to - Mark some unused parameters as such.
|
220038 |
26-Mar-2011 |
marius |
- Merge the *_SET macros from fire(4) which generally print out the register changes when compiled with SCHIZO_DEBUG and take advantage of them. - Add support for the XMITS Fireplane/Safari to PCI-X bridges. I tought I'd need this for a Sun Fire 3800, which then turned out to not being equipped with such a bridge though. The support for these should be complete but given that it hasn't actually been tested probing is disabled for now. This required a way to alter the XMITS configuration in case a PCI-X device is found further down the device tree so the sparc64 specific ofw_pci kobj was revived with a ofw_pci_setup_device method, which is called by the ofw_pcibus code for every device added. - A closer inspection of the OpenSolaris code indicates that consistent DMA flushing/syncing as well as the block store workaround should be applied with every BUS_DMASYNC_POSTREAD instead of in a wrapper around interrupt handlers for devices behind PCI-PCI bridges only as suggested by the documentation (code for the latter actually exists in OpenSolaris but is disabled by default), which also makes more sense. - Add a workaround for Casinni/Skyhawk combinations. Chances are that this solves the crashes seen when using the the on-board Casinni NICs of Sun Fire V480 equipped with centerplanes other than 501-6780 or 501-6790. This also takes advantage of the ofw_pci_setup_device method. - Mark some unused parameters as such.
|
219785 |
19-Mar-2011 |
marius |
- Make a panic message better reflect the actual problem. - A closer inspection of the OpenSolaris code indicates the block store workaround is only necessary in case of BUS_DMASYNC_POSTREAD. - Mark some unused parameters as such.
|
219780 |
19-Mar-2011 |
marius |
In case reading PCIR_MINGNT fails don't use it for calculating the latency. This is more or less a theoretical problem though as it typically indicates way bigger problems.
|
219567 |
12-Mar-2011 |
marius |
Sync licenses and the corresponding RCS IDs with NetBSD, mainly switching the licenses of Matthew R. Green and the TNF to 2-clause.
Obtained from: NetBSD
|
218930 |
21-Feb-2011 |
marius |
Resurrect ofw_pci_if.m from r178578.
|
218909 |
21-Feb-2011 |
brucec |
Fix typos - remove duplicate "the".
PR: bin/154928 Submitted by: Eitan Adler <lists at eitanadler.com> MFC after: 3 days
|
216962 |
04-Jan-2011 |
marius |
Inherit the APB and the generic OFW PCI-PCI bridge driver from the generic PCI-PCI bridge driver in order to safe some code.
|
216961 |
04-Jan-2011 |
marius |
Reserve INTR_MD[1-4] similarly to what BUS_DMA_BUS[1-4] are intended for and switch sparc64 to use the first one for bus error filter handlers of bridge drivers instead of (ab)using INTR_FAST for that so we eventually can get rid of the latter.
Reviewed by: jhb MFC after: 1 month
|
215349 |
15-Nov-2010 |
marius |
Convert drivers somehow missed in r200874 to multipass probing.
|
212378 |
09-Sep-2010 |
jhb |
Catch up to rename of the constant for the Master Data Parity Error bit in the PCI status register.
Pointed out by: mdf Pointy hat to: jhb
|
209298 |
18-Jun-2010 |
nwhitehorn |
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent.
MFC after: 8.1-RELEASE
|
208097 |
14-May-2010 |
marius |
- Enable DMA write parity error interrupts on Schizo with a working implementation. - Revert the Sun Fire V890 WAR of r205254. Instead let schizo_pci_bus() only panic in case of fatal errors as the interrupt triggered by the error the firmware of these and also Sun Fire 280R with version 7 Schizo caused may happen as late as using the HBA and not only prior to touching the PCI bus (in the former case the actual error still is fatal but we clear it before touching the PCI bus). While at it count and export non-fatal error interrupts via sysctl(9). - Remove unnecessary locking from schizo_ue().
|
206453 |
10-Apr-2010 |
marius |
Add missing copyright shebang.
|
206451 |
10-Apr-2010 |
marius |
Add sbbc(4), a driver for the BootBus controller found in Serengeti and StarCat systems which provides time-of-day services for both as well as console service for Serengeti, i.e. Sun Fire V1280. While the latter is described with a device type of serial in the OFW device tree, it isn't actually an UART. Nevertheless the console service is handled by uart(4) as this allowed to re-use quite a bit of MD and MI code. Actually, this idea is stolen from Linux which interfaces the sun4v hypervisor console with the Linux counterpart of uart(4).
|
206020 |
31-Mar-2010 |
marius |
Use device_get_nameunit(9) rather than device_get_name(9) so one can identify the reporting bridge in machines with multiple PCI domains.
|
206019 |
31-Mar-2010 |
marius |
Don't re-implement device_get_nameunit(9).
|
206018 |
31-Mar-2010 |
marius |
- Take advantage of the INTCLR_* macros. - Right-justify the backslashes as per style(9).
|
205254 |
17-Mar-2010 |
marius |
- Add quirk handling for Sun Fire V1280. The firmware of these machines provides no ino-bitmap properties so forge them using the default set of controller interrupts and let schizo_setup_intr() take care of the children, hoping for non-fancy routing. - Add quirk handling for Sun Fire V890. When booting these machines from disk a Schizo comes up with PCI error residing which triggers as soon as we register schizo_pci_bus() even when clearing it from all involved registers (it's no longer indicated once we're in schizo_pci_bus() though). Thus make PCI bus errors non-fatal until we actually touch the bus. With this change schizo_pci_bus() typically triggers once during attach in this case. Obviously this approach isn't exactly race free but it's about the best we can do about this problem as we're not guaranteed that the interrupt will actually trigger on V890 either, as it certainly doesn't when for example netbooting them.
|
203094 |
27-Jan-2010 |
marius |
- Zero the MSI/MSI-X queue argument, otherwise mtx_init(9) can panic indicating an already initialized lock. - Check for an empty MSI/MSI-X queue entry before asserting that we have received a MSI/MSI-X message in order to not panic in case of stray MSI/ MSI-X queue interrupts which may happen in case of using an interrupt handler rather than a filter.
MFC after: 3 days
|
202023 |
10-Jan-2010 |
marius |
When setting up MSIs with a filter ensure that the event queue interrupt is cleared as it might have triggered before and given we supply NULL as ic_clear, inthand_add() won't do this for us in this case.
|
202003 |
10-Jan-2010 |
marius |
- According to OpenSolaris it's sufficient to align the MSIs of a device in the table based on the count rather than the maxcount. Also the previous code didn't work properly as it would have been necessary to reserve the entire maxcount range in order keep later requests from filling the spare MSIs between count and maxcount, which would be complicated to unreserve in fire_release_msi(). - For MSIs with filters rather than handlers only don't clear the event queue interrupt via fire_intr_clear() since given that these are executed directly would clear it while we're still processing the event queue, which in turn would lead to lost MSIs. - Save one level of indentation in fire_setup_intr(). - Correct a bug in fire_teardown_intr() which prevented it from correctly restoring the MSI in the resource, causing allocation of a resource representing an MSI to fail after the first pass when repeatedly loading and unloading a driver module.
|
201395 |
02-Jan-2010 |
marius |
- Preserve the PROM IOMMU in order to allow OFW drivers to continue to work. - Sanity check the parameters passed to the implementations of the pcib_{read,write}_config() methods. Using illegal values can cause no real harm but it doesn't hurt to avoid unnecessary data error traps requiring to flush and re-enable the level 1 caches.
|
201200 |
29-Dec-2009 |
marius |
- Remove a redundant variable and an unnecessary cast. - Fix whitespace.
|
201199 |
29-Dec-2009 |
marius |
- Prefer i and j over i and n for temporary integer variables. - Wrap/shorten too long lines. - Remove a redundant variable and an unnecessary cast in schizo(4).
|
201126 |
28-Dec-2009 |
marius |
Account for firmware versions which include the CDMA interrupts in the OFW device tree.
MFC after: 3 days
|
201052 |
27-Dec-2009 |
marius |
Add a driver for the `Fire' JBus to PCIe bridges found in at least the Sun Fire V215/V245 and Sun Ultra 25/45 machines. This driver also already includes all the code to support the `Oberon' Uranus to PCIe bridges found in the Fujitsu-Siemens based Mx000 machines but due to lack of access to such a system for testing, probing of these bridges is currently disabled. Unfortunately, the event queue mechanism of these bridges for MSIs/ MSI-Xs matches our current MD and MI interrupt frameworks like square pegs fit into round holes so for now we are generous and use one event queue per MSI, which limits us to 35 MSIs/MSI-Xs per Host-PCIe-bridge (we use one event queue for the PCIe error messages). This seems tolerable as long as most devices just use one MSI/MSI-X anyway. Adding knowledge about MSIs/MSI-Xs to the MD interrupt code should allow us to decouple the 1:1 mapping at the cost of no longer being able to bind MSIs/MSI-Xs to specific CPUs as we currently have no reliable way to quiesce a device during the transition of its MSIs/ MSI-Xs to another event queue. This would still require the problem of interrupt storms generated by devices which have no one-shot behavior or can't/don't mask interrupts while the filter/handler is executed (like the older PCIe NICs supported by bge(4)) to be solved though.
Committed from: 26C3
|
200987 |
25-Dec-2009 |
marius |
- Hook up the default implementations of the MSI/MSI-X pcib_if methods so requests may bubble up to a host-PCI bridge driver. - Distinguish between PCI and PCIe bridges in the device description so it's a bit easier to follow what hangs off of what in the dmesg. Unfortunately we can't also tell PCI and PCI-X apart based on the information provided in the OFW device tree. - Add quirk handling for the ALi M5249 found in Fire-based machines which are used as a PCIe-PCIe bridge there. These are obviously subtractive decoding as as they have a PCI-ISA bridge on their secondary side (and likewise don't include the ISA I/O range in their bridge decode) but don't indicate this via the class code. Given that this quirk isn't likely to apply to all ALi M5249 and I have no datasheet for these chips so I could implement a check using the chip specific bits enabling subtractive decoding this quirk handling is added to the MD code rather than the MI one.
|
200948 |
24-Dec-2009 |
marius |
Merge from amd64/i386: Implement support for interrupt descriptions.
|
200921 |
23-Dec-2009 |
marius |
- Add quirk handling for ALi M5229, mainly setting the magic "force enable IDE I/O" bit which prevents data access traps with revision 0xc8 in Fire-based machines when pci(4) enables PCIM_CMD_PORTEN. - Like for sun4v also don't add the PCI side of host-PCIe bridges to the bus on sun4u as they don't have configuration space implement there either.
|
200920 |
23-Dec-2009 |
marius |
- Sort the prototypes. - Add macros to ease the access of device configuration space in ofw_pcibus_setup_device().
|
200918 |
23-Dec-2009 |
marius |
Add structures for OFW MSI/MSI-X support. These are identical for both sun4u and sun4v.
|
200874 |
22-Dec-2009 |
marius |
Enroll these drivers in multipass probing. The motivation behind this is that the JBus to EBus bridges share the interrupt controller of a sibling JBus to PCIe bridge (at least as far as the OFW device tree is concerned, in reality they are part of the same chip) so we have to probe and attach the latter first. That happens to be also the case due to the fact that the JBus to PCIe bridges appear first in the OFW device tree but it doesn't hurt to ensure the right order.
|
200815 |
21-Dec-2009 |
marius |
Provide and consume missing module dependency information.
|
197164 |
13-Sep-2009 |
marius |
Factor out the duplicated macro for the device type used in the OFW device tree for PCI bridges and add a new one for PCI Express. While at it, take advantage of the former for the rman(9) work- around in jbusppm(4).
|
190113 |
19-Mar-2009 |
marius |
Bring the implementation of the pnpinfo string function more in line with the rest of this file.
|
190109 |
19-Mar-2009 |
marius |
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const.
PR: 131371 [1]
|
190108 |
19-Mar-2009 |
marius |
- Take advantage of KOBJMETHOD_END. - Hook up the streaming buffer (not used by iommu(4) by default, yet) if available and usable. [1] - Move the message regarding belated registration as interrupt control under bootverbose as this isn't something the user should worry about.
Tested by: Michael Moll [1]
|
190101 |
19-Mar-2009 |
marius |
Take advantage of KOBJMETHOD_END.
|
190099 |
19-Mar-2009 |
marius |
- Sort device methods. - Take advantage of KOBJMETHOD_END.
|
186290 |
18-Dec-2008 |
marius |
- Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Ensure we use the right softc in case the interrupt of a child is is routed to the companion PBM instead. This hasn't been seen in the wild so far but given that it's the case for the Schizo interrupts, handling this situation also for child interrupts as a precaution seemed a good idea. - Deal with broken firmware versions which miss child entries in the ino-bitmap as seen on V880 by belatedly registering as interrupt controller in schizo_setup_intr(). [1] - Add missing '\n' when printing the warning regarding Schizo Errata I-13.
Reported and tested by: Beat Gaetzi [1]
|
186128 |
15-Dec-2008 |
nwhitehorn |
Adapt parts of the sparc64 Open Firmware bus enumeration code (in particular, the code for parsing interrupt maps) to PowerPC and reflect their new MI status by moving them to the shared dev/ofw directory.
This commit also modifies the OFW PCI enumeration procedure on PowerPC to allow the bus to find non-firmware-enumerated devices that Apple likes to add, and adds some useful Open Firmware properties (compat and name) to the pnpinfo string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the change to PCI enumeration on PowerPC, X has started working again on PPC machines with Grackle hostbridges.
Reviewed by: marius Obtained from: sparc64
|
185133 |
20-Nov-2008 |
marius |
- According to OpenSolaris, CDMA flushing/syncing for Tomatillos and XMITS has to be basically done in the same manner as for the Sabres, i.e. only for devices behind PCI-PCI-bridges and after a PIO read on the far side of the farest PCI-PCI-bridge. Given that the Tomatillo documentation mentions no difference to the Schizo bridges in this regard and this is also still part of the procedure described Schizo documentation this seems about right so adjust accordingly (the unconditional CDMA flushing/syncing previously done was based on how Linux behaves). - Implement CDMA flushing/syncing for Schizo version >= 5, which requires the workaround described in Schizo Errata I-23. According to Schizo Errata I-13 it's just unusable with version < 5 though. [1] - Don't register the Schizo streaming buffer for now until it's usage is sorted out according to the erratas. - Register our interrupt filters with the revived INTR_FAST so they these interrupts can even interrupt filters of device drivers as necessary. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem.
Reported by: Michael Moll [1]
|
184428 |
28-Oct-2008 |
marius |
- Turn off interrupts instead of only entering a critical section while doing the block store workaround so we restore the correct floating-point registers state in case of nested floating-point operations resulting from nested interrupts. This allows the VIS-based block copy/zero functions to be used on machines requiring this workaround. Alternatively, we could take care of saving the floating-point registers here, which would be more inefficiently though and also involves turning off interrupts. - It turns out that the SCZ_PCI_DMA_SYNC register doesn't work like the TOMXMS_PCI_DMA_SYNC_PEND one (but more like the corresponding register in of Hummingbird and Sabre bridges) and writing the INO of the respective device to it causes a Safari bus error. However, due to the Schizo errata I-23, SCZ_PCI_DMA_SYNC can't be used as intended either, so remove consistent DMA syncing for Schzio bridges for now, which means that add-on cards with non-"sun4u compliant" (whatever that means exactly) PCI-PCI-bridges should be avoided until the proper workaround is implemented. [1]
Reported by: Michael Moll [1]
|
183423 |
28-Sep-2008 |
marius |
Add a driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to PCI 2.2 bridges. In theory, this driver should also handle `XMITS' Fireplane/Safari to PCI-X bridges but due to lack of access to such hardware, support for these hasn't be fleshed out, yet.
|
183152 |
18-Sep-2008 |
marius |
Clear any possibly pending PCI error bits left by the firmware. These could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
|
182110 |
24-Aug-2008 |
marius |
Announce the speed of the PCI bus for informational purpose.
MFC after: 3 days
|
182108 |
24-Aug-2008 |
marius |
The PCI specifications don't explain the details on how to calculate the latency based on the Min_Gnt register so use the algorithm found in OpenSolaris as they probably know how to interpret the value Sun puts into these registers (previously, the latency calculated for 66MHz was most likely wrong) and for bridges additionally set up the secondary latency register. Also set up the bridge control register the way it's done in OpenSolaris. As the latency register don't apply to PCI-Express and the bridge control setup wasn't tested on sun4v (besides most likely not being needed), expand the #ifndef SUN4V accordingly.
MFC after: 3 days
|
182020 |
22-Aug-2008 |
marius |
cosmetic changes and style fixes
|
178840 |
07-May-2008 |
marius |
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c
MFC after: 1 week
|
178728 |
02-May-2008 |
marius |
Remove an header which is unused for sun4v.
MFC after: 3 days
|
178579 |
26-Apr-2008 |
marius |
Remove the MD isa_irq_pending() and the underlying PCI-specific infrastructure. Its only consumer ever was sio(4) and thus was unused on sparc64 since removing the last traces of sio(4) in sparc64 configuration files in favor for uart(4) over three years ago. If similar functionality is required again it should be brought back as an MD intr_pending() which works for all busses by using for example interrupt controller hooks.
|
178443 |
23-Apr-2008 |
marius |
o Rename ic_eoi to ic_clear to emphasize the functions it points don't send and EOI which works like on amd64/i386 and blocks all interrupts on the relevant interrupt controller. o Replace the post_filter and post_inthread hooks registered when creating the interrupt events with just ic_clear as on sparc64 we don't need to do any disable->EOI->enable dance to unblock all but the relevant interrupt while running the filter or handler; just not clearing the interrupt already has the same effect. o Merge from amd64/i386: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. - Add support for binding interrupts to CPUs, including for the bus_bind_intr(9) interface, a assign_cpu hook and initially shuffling interrupts arround in a round-robin fashion.
Reviewed by: jhb MFC after: 1 month
|
178279 |
17-Apr-2008 |
marius |
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges.
MFC after: 1 month
|
174898 |
25-Dec-2007 |
rwatson |
Add a new 'why' argument to kdb_enter(), and a set of constants to use for that argument. This will allow DDB to detect the broad category of reason why the debugger has been entered, which it can use for the purposes of deciding which DDB script to run.
Assign approximate why values to all current consumers of the kdb_enter() interface.
|
174134 |
01-Dec-2007 |
marius |
Fix a non-fatal off-by-one error in the previous revision.
|
174117 |
30-Nov-2007 |
marius |
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members.
MFC after: 3 days
|
172394 |
30-Sep-2007 |
marius |
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled.
Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
|
172333 |
26-Sep-2007 |
marius |
- Use the actual clock frequency of the PCI bus instead of assuming 33MHz for calculating the latency timer values for its children. Inspired by NetBSD doing the same and Linux as well as OpenSolaris using a similar approach. While at it rename a variable and change its type to be more appropriate fuer values of PCI properties so the variable can be more easily reused. - Initialize the cache line size register of PCI devices to a legal value; the cache line size is limited to 64 bytes by the Fireplane/Safari, JBus and UPA interconnection busses. Setting it to an unsupported value caused bad performance at least with GEM as it causes them to not do cache line bursts and to not issue cache line commands on the PCI bus.
Approved by: re (kensmith) MFC after: 1 week
|
172066 |
06-Sep-2007 |
marius |
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc.
Reviewed by: marcel (earlier version) Approved by: re (kensmith)
|
171730 |
05-Aug-2007 |
marius |
- Divorce the IOTSBs, which so far where handled via a global list instead of per IOMMU, so we no longer need to program all of them identically in systems having multiple IOMMUs. This continues the rototilling of the nexus(4) done about 5 months ago, which amongst others changed nexus(4) and the drivers for host-to-foo bridges to provide bus_get_dma_tag methods, allowing to handle DMA tags in a hierarchical way and to link them with devices. This still doesn't move the silicon bug workarounds for Sabre (and in the uncommitted schizo(4) for Tomatillo) bridges into special bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy() this still requires too much hackery, i.e. per-child parent DMA tags in the parent driver. - Let the host-to-foo drivers supply the maximum physical address of the IOMMU accompanying the bridges. Previously iommu(4) hard- coded an upper limit of 16GB, which actually only applies to the IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants as well as the U2S in fact can can translate to up to 2TB, i.e. translate to 41-bit physical addresses. According to the recently available Tomatillo documentation these bridges even translate to 43-bit physical addresses and hints at the Schizo bridges doing 43 bits as well. This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on sparc64" was refering to and pretty much obsoletes the lack of support for bounce buffers on sparc64.
Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual.
Approved by: re (kensmith)
|
170930 |
18-Jun-2007 |
marius |
- Move ofw_pci_alloc_busno() to the ofw_pci KOBJ interface, allowing the driver for the host-PCI-bridge to indicate that reenumeration of the PCI busses isn't supported by returning -1 instead of a valid PCI bus number. This is needed in order support both Tomatillo, which don't support reenumeration and thus are apparently intended to be used for independently numbered PCI domains only, and Psycho bridges, whose busses need to be reenumerated on at least some E450, without the #ifndef currently used for sun4v in order to support multiple independently PCI domains. The actual allocation/incrementation of the PCI bus numbers is now done in psycho(4), though it no longer establish a mapping between bus numbers and device nodes like ofw_pci_alloc_busno() did as that functionality wasn't used (but can easily brought back if really needed). The now no longer used sys/sparc64/pci/ofw_pci.c is also removed from sys/conf/files.sun4v as ofw_pci_alloc_busno() wasn't used there in the first place. - In ofw_pci_default_{adjust_busrange,intr_pending}() sanity check that the device has a parent before passing it on. - Make psycho_softcs static to sys/sparc64/pci/psycho.c as it's not used outside of that module. - In sys/sparc64/pci/ofw_pcib_subr.c remove the superfluous inclusion of opt_global.h and correct the debug output for adjusting the subordinate bus number.
|
170929 |
18-Jun-2007 |
marius |
For sun4u also add PCI busses with a device unit number of -1 instead of using the PCI bus number, like it's already done for sun4v in order to deal properly with independently numbered PCI domains which can't be reenumerated (in the case of sun4u f.e. Tomatillo bridges). For machines where we need to reenumerate all PCI busses this change obviously introduces the theoretical cosmetic problem that the device number of the PCI bus no longer equals to its PCI bus number. In practice this doesn't happen as both are assigned linearly and in parallel.
|
170887 |
17-Jun-2007 |
marius |
Remove unused softc.
|
170851 |
16-Jun-2007 |
marius |
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
|
170387 |
06-Jun-2007 |
piso |
Teach the bridge wrapper how to handle the filter+ithread case.
Reviewed by: marius
|
169793 |
20-May-2007 |
marius |
Delete the unused/not really used sparc64 (as in sun4u) cache.h, iommureg.h (which already began to bitrot) and iommuvar.h from the sun4v source and adjust some of the source which is shared between sparc64 and sun4v as appropriate.
|
167308 |
07-Mar-2007 |
marius |
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits.
Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though.
PR: 76052 [1] Approved by: re (kensmith)
|
166901 |
23-Feb-2007 |
piso |
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr()
o add an int return code to all fast handlers
o retire INTR_FAST/IH_FAST
For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current
Reviewed by: many Approved by: re@
|
166092 |
18-Jan-2007 |
marius |
Remove the compat shims for the ISA old-stlye in{b,w,l}()/out{b,w,l}() and friends along with all hacks required to implement them. None of the drivers currently built (as part of GENERIC, LINT or modules) on sparc64 or sun4v and none of those we might want to use there in future uses them, AFAICT there actually never was a driver hooked up to the sparc64 or sun4v build that correctly used these functions (and it looks like that due to a bug read{b,w,l}()/write{b,w,l}() and the other functions working on a memory handle never actually worked on sun4v). All they ever were good for on sparc64 and sun4v was erroneously dragging in dependencies on isa(4) in drivers like f.e. dpt(4), si(4) and syscons(4) in source files that supposedly were bus-neutral and hiding issues with drivers like f.e. ng_bt3c(4) that used these functions with busses other than isa(4) and therefore couldn't work on these platforms.
|
165886 |
08-Jan-2007 |
marius |
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues.
Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
|
165885 |
08-Jan-2007 |
marius |
In ofw_pcibus_attach() skip dupe PCI devices reported by the firmware (mainly 'pmu' and its 'lomp' dupe found in a couple of later USII{e,i}-based machines) by checking whether a device with the same triple of bus number, slot and function already has been added. This is the simple yet effective approach introduced in OpenBSD some time ago, but which has the flaw that it assumes that the device and its dupe(s) found in the OFW device tree are equal or at least the one encountered first is in some way the more important one (this is the case with 'pmu' and 'lomp'; the 'pmu' node has couple of properties and children while the 'lomp' one misses most of these). If there's ever a device/dupe pair where we don't encounter the more important node first, we'll probably need to introduce a quirk list in order to add the desired device but prevent its dupe(s) from being added.
MFC after: 1 week
|
163260 |
12-Oct-2006 |
kmacy |
The T2000 has multiple PCI domains requiring bus allocation to be done differently. This pulls in changes by jmg from perforce and makes them sun4v only for now.
Approved by: scottl (acting as backup for mentor rwatson)
|
163146 |
09-Oct-2006 |
kmacy |
kernel clean up to make the sun4v kernel build
Reviewed by: jmg Approved by: rwatson (mentor)
|
157896 |
20-Apr-2006 |
imp |
Set the rid for any resource obtained from rman_reserve_resource.
Reviewed by: wollman, jmg (as were the other commits fixing this problem)
|
154870 |
26-Jan-2006 |
marius |
- Register the generic implementations for the device shutdown, suspend and resume methods so these events propagate through the device driver hierarchy. - In dma(4) enable the chaining of the DMA engine interrupt handler for the LANCE devices via a dma_setup_intr(). This was commented out before as I was unsure whether I'd use it but this is probably cleaner than fiddling with the DMA engine interrupt in the LANCE driver directly. - In ebus_setup_dinfo() free 'intrs' instead of 'reg' twice in case setting up a child fails due to routing one of its interrupts fails. [1]
Found by: Coverity Prevent [1] MFC after: 3 days
|
154600 |
20-Jan-2006 |
jhb |
Make the ACPI and OpenFirmware PCI bus drivers subclasses of the generic PCI bus driver.
|
154079 |
06-Jan-2006 |
jhb |
- Make pcib_devclass private to sys/dev/pci/pci_pci.c and change all the various pcib drivers to use their own private devclass_t variables for their modules. - Use the DEFINE_CLASS_0() macro to declare drivers for the various pcib drivers while I'm here.
|
153560 |
20-Dec-2005 |
jhb |
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
|
153342 |
12-Dec-2005 |
marius |
Fix a bug introduced in rev. 1.5; for retrieving the device_t of the parent bridge of a PCI-PCI bridge we need two device_get_parent().
|
153061 |
03-Dec-2005 |
marius |
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
|
153059 |
03-Dec-2005 |
marius |
- Adhere style(9) (don't use function calls in initializers). - Use FBSDID.
|
153057 |
03-Dec-2005 |
marius |
- Adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t). - Use FBSDID.
|
153055 |
03-Dec-2005 |
marius |
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway.
MFC after: 1 month
|
153052 |
03-Dec-2005 |
marius |
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
|
152698 |
22-Nov-2005 |
marius |
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally.
PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
|
152696 |
22-Nov-2005 |
marius |
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one:
- Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code).
PR: 76052 [1]
|
152684 |
22-Nov-2005 |
marius |
- Convert these bus drivers to make use of the newly introduced set of ofw_bus_gen_get_*() for providing the ofw_bus KOBJ interface in order to reduce code duplication. - While here sync the various sparc64 bus drivers a bit (handle failure to attach a child gracefully instead of panicing, move the printing of child resources common to bus_print_child() and bus_probe_nomatch() implementations of a bus into a <bus>_print_res() function, ...) and fix some minor bugs and nits (plug memory leaks present when attaching a bus or child device fails, remove unused struct members, ...).
Additional testing by: kris (central(4) and fhc(4))
|
145610 |
28-Apr-2005 |
marcel |
Slightly reformat apb_alloc_resource() to create some horizontal space for enhancements. Shorten apb_map_checkrange() to apb_checkrange() for the same reason. No functional change.
|
144033 |
23-Mar-2005 |
jmg |
fix kldloading of pci driver modules after boot on sparc64... since we weren't using the pci module, we weren't restoring the pci state...
Submitted by: imp MFC after: 5 days
|
140512 |
20-Jan-2005 |
marius |
At least on some U30 there's a spurious duplicate device node of an EBus bridge in the device tree which lacks the mandatory (also by the OFW PCI bus binding spec) "reg" property. Change the code to just ignore nodes missing the "reg" property instead of panicing when encountering such a node. Also ignore nodes without a "name" property (guaranteed by the OFW PCI bus binding spec). This brings the behaviour of the MD OFW PCI code regarding such incomplete nodes in line with the EBus and the SBus code.
Tested by: Cyril Tikhomiroff <tikho@anor.net> MFC after: 1 month
|
139825 |
07-Jan-2005 |
imp |
/* -> /*- for license, minor formatting changes
|
133774 |
15-Aug-2004 |
marius |
Correct some uses of the wrong members of the *min()/*max()-familiy, e.g. min() on unsigned long. None of these are believed to have been fatal though.
Reviewed by: tmm
|
133589 |
12-Aug-2004 |
marius |
- Introduce an ofw_bus kobj-interface for retrieving the OFW node and a subset ("compatible", "device_type", "model" and "name") of the standard properties in drivers for devices on Open Firmware supported busses. The standard properties "reg", "interrupts" und "address" are not covered by this interface because they are only of interest in the respective bridge code. There's a remaining standard property "status" which is unclear how to support properly but which also isn't used in FreeBSD at present. This ofw_bus kobj-interface allows to replace the various (ebus_get_node(), ofw_pci_get_node(), etc.) and partially inconsistent (central_get_type() vs. sbus_get_device_type(), etc.) existing IVAR ones with a common one. This in turn allows to simplify and remove code-duplication in drivers for devices that can hang off of more than one OFW supported bus. - Convert the sparc64 Central, EBus, FHC, PCI and SBus bus drivers and the drivers for their children to use the ofw_bus kobj-interface. The IVAR- interfaces of the Central, EBus and FHC are entirely replaced by this. The PCI bus driver used its own kobj-interface and now also uses the ofw_bus one. The IVARs special to the SBus, e.g. for retrieving the burst size, remain. Beware: this causes an ABI-breakage for modules of drivers which used the IVAR-interfaces, i.e. esp(4), hme(4), isp(4) and uart(4), which need to be recompiled. The style-inconsistencies introduced in some of the bus drivers will be fixed by tmm@ in a generic clean-up of the respective drivers later (he requested to add the changes in the "new" style). - Convert the powerpc MacIO bus driver and the drivers for its children to use the ofw_bus kobj-interface. This invloves removing the IVARs related to the "reg" property which were unused and a leftover from the NetBSD origini of the code. There's no ABI-breakage caused by this because none of these driver are currently built as modules. There are other powerpc bus drivers which can be converted to the ofw_bus kobj-interface, e.g. the PCI bus driver, which should be done together with converting powerpc to use the OFW PCI code from sparc64. - Make the SBus and FHC front-end of zs(4) and the sparc64 eeprom(4) take advantage of the ofw_bus kobj-interface and simplify them a bit.
Reviewed by: grehan, tmm Approved by: re (scottl) Discussed with: tmm Tested with: Sun AX1105, AXe, Ultra 2, Ultra 60; PPC cross-build on i386
|
131949 |
10-Jul-2004 |
marcel |
Update for the KDB framework: o Call kdb_enter() instead of Debugger().
|
131537 |
03-Jul-2004 |
imp |
These don't need RMAN_RESOURCE_VISIBLE now that rman is visible
|
131376 |
30-Jun-2004 |
marius |
These need __RMAN_RESOURCE_VISIBLE, too.
|
130068 |
04-Jun-2004 |
phk |
Add missing <sys/module.h> #includes
|
130025 |
03-Jun-2004 |
phk |
Add missing <sys/module.h> instances which were shadowed by the nested include in <sys/kernel.h>
|
129051 |
08-May-2004 |
marius |
- Remove the old sparc64 OFW PCI code (as opposed to the former "options OFW_NEWPCI"). This is a bit overdue, the new sparc64 OFW PCI code which is meant to replace the old one is in place for 10 months and enabled by default in GENERIC for 8 months. FreeBSD 5.2 and 5.2.1 also shipped with the new code enabled by default. - Some minor clean-up, e.g. remove functions that encapsulated the #ifdefs for OFW_NEWPCI, remove unused resp. no longer required includes, etc.
Approved by: tmm, no objections on freebsd-sparc64
|
128625 |
25-Apr-2004 |
tmm |
Some code cleanup: - Fix some comments; remove numerous superfluous or outdated ones. - Correctly pass on the requesting device when handing requests up to the parent bus. - Use the complete device name, including unit number, to build the IOMMU instance name. - Inline a function that was only used once, and was trivial.
|
123864 |
26-Dec-2003 |
obrien |
Don't confuse NULL with 0.
|
119737 |
04-Sep-2003 |
tmm |
- Clear the CE AFSR bits which indicate the error condition when handling a correctable DMA error. Failing to do so can cause the error interrupt to be triggered over and over again. - Clean up the comments for UEAFSR_* constants, fix a typo (UEAFSR_BLK is (1 << 23), not (1 << 22)), and add two more. Also, add similar constants for the CE AFSR bits.
|
119338 |
23-Aug-2003 |
imp |
s=include <ofw/=include <dev/ofw/= to reflect removal of -I$S/dev
|
119291 |
22-Aug-2003 |
imp |
Prefer new location of pci include files (which have only been in the tree for two or more years now), except in a few places where there's code to be compatible with older versions of FreeBSD.
|
117126 |
01-Jul-2003 |
scottl |
Mega busdma API commit.
Add two new arguments to bus_dma_tag_create(): lockfunc and lockfuncarg. Lockfunc allows a driver to provide a function for managing its locking semantics while using busdma. At the moment, this is used for the asynchronous busdma_swi and callback mechanism. Two lockfunc implementations are provided: busdma_lock_mutex() performs standard mutex operations on the mutex that is specified from lockfuncarg. dftl_lock() is a panic implementation and is defaulted to when NULL, NULL are passed to bus_dma_tag_create(). The only time that NULL, NULL should ever be used is when the driver ensures that bus_dmamap_load() will not be deferred. Drivers that do not provide their own locking can pass busdma_lock_mutex,&Giant args in order to preserve the former behaviour.
sparc64 and powerpc do not provide real busdma_swi functions, so this is largely a noop on those platforms. The busdma_swi on is64 is not properly locked yet, so warnings will be emitted on this platform when busdma callback deferrals happen.
If anyone gets panics or warnings from dflt_lock() being called, please let me know right away.
Reviewed by: tmm, gibbs
|
117119 |
01-Jul-2003 |
tmm |
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now.
The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code.
There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics.
A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon.
In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups.
In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon.
Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
|
116659 |
22-Jun-2003 |
jmg |
add support for peeking at pci busses on UltraSparc systems. This prevents data access errors when trying to read/write to non-existant PCI devices.
fix the psycho bridge to use peek for probing devices. This no longer fakes it if the OFW node doesn't exist (and the reg == 0).
Reviewed by: jake, tmm
|
116541 |
18-Jun-2003 |
tmm |
Further cleanup of the sparc64 busdma implementation: - Move prototypes for sparc64-specific helper functions from bus.h to bus_private.h - Move the method pointers from struct bus_dma_tag into a separate structure; this saves some memory, and allows to use a single method table for each busdma backend, so that the bus drivers need no longer be changed if the methods tables need to be modified. - Remove the hierarchical tag method lookup. It was never really useful, since the layering is fixed, and the current implementations do not need to call into parent implementations anyway. Each tag inherits its method table pointer and cookie from the parent (or the root tag) now, and the method wrapper macros directly use the method table of the tag. - Add a method table to the non-IOMMU backend, remove unnecessary prototypes, remove the extra parent tag argument. - Rename sparc64_dmamem_alloc_map() and sparc64_dmamem_free_map() to sparc64_dma_alloc_map() and sparc64_dma_free_map(), move them to a better place and use them for all map allocations and deallocations. - Add a method table to the iommu backend, and staticize functions, remove the extra parent tag argument. - Change the psycho and sbus drivers to just set cookie and method table in the root tag. - Miscellaneous small fixes.
|
116303 |
13-Jun-2003 |
jmg |
Hardwire APB's PCI buses down. If we don't do this, pciconf -l returns selectors that are incorrect to use with pciconf -[rw]
Fixes-PR: sparc64/50789 Ok's by: tmm
|
116259 |
12-Jun-2003 |
tmm |
Remove the PSYCHO_STRAY option - it was never really useful. Adjust a nearby comment. PSYCHO_DEBUG remains, as it is quite useful for debugging interrupt routing problems.
|
116213 |
11-Jun-2003 |
tmm |
Remove the psycho and sbus iommu function stubs, and put the pointer to the iommu_state structure directly into dt_cookie. The stubs have not been needed for a long time now.
|
115417 |
30-May-2003 |
tmm |
Fix interrupt assignment for non-builtin PCI devices on e450s.
This machine uses a non-standard scheme to specify the interrupts to be assigned for devices in PCI slots; instead of giving the INO or full interrupt number (which is done for the other devices in this box), the firmware interrupt properties contain intpin numbers, which have to be swizzled as usual on PCI-PCI bridges; however, the PCI host bridge nodes have no interrupt map, so we need to guess the correct INO by slot number of the device or the closest PCI-PCI bridge leading to it, and the intpin.
To do this, this fix makes the following changes: - Add a newbus method for sparc64 PCI host bridges to guess the INO, and glue code in ofw_pci_orb_callback() to invoke it based on a new quirk entry. The guessing is only done for interrupt numbers too low to contain any IGN found on e450s. - Create another new quirk entry was created to prevent mapping of EBus interrupts at PCI level; the e450 has full INOs in the interrupt properties of EBus devices, so trying to remap them could cause problems. - Set both quirk entries for e450s; remove the no-swizzle entry. - Determine the psycho half (bus A or B) a driver instance manages in psycho_attach() - Implement the new guessing method for psycho, using the slot number, psycho half and property value (intpin).
Thanks go to the testers, especially Brian Denehy, who tested many kernels for me until I had found the right workaround.
Tested by: Brian Denehy <B.Denehy@90east.com>, jake, fenner, Marius Strobl <marius@alchemy.franken.de>, Marian Dobre <mari@onix.ro> Approved by: re (scottl)
|
115343 |
27-May-2003 |
scottl |
Bring back bus_dmasync_op_t. It is now a typedef to an int, though the BUS_DMASYNC_ definitions remain as before. The does not change the ABI, and reverts the API to be a bit more compatible and flexible. This has survived a full 'make universe'.
Approved by: re (bmah)
|
115316 |
26-May-2003 |
scottl |
De-orbit bus_dmamem_alloc_size(). It's a hack and was never used anyways. No need for it to pollute the 5.x API any further.
Approved by: re (bmah)
|
114484 |
02-May-2003 |
tmm |
- Reduce the DVMA preallocation limit from 128kB to 32kB. 128kB were quite excessive, and caused the available space to be used up too easily. The new limit should be a better estimation of how much the caller will need at most. - Double the IOTSB size 64kB, for a DVMA area size of 64MB.
This should fix DMA problems on e450s and other large machines due to DVMA space exhaustion, which were introduced in my last IOMMU code revision in January.
Reported and tested by: fenner
|
113347 |
10-Apr-2003 |
mux |
Change the operation parameter of bus_dmamap_sync() from an enum to an int and redefine the BUS_DMASYNC_* constants as flags. This allows us to specify several operations in one call to bus_dmamap_sync() as in NetBSD.
|
113238 |
08-Apr-2003 |
jake |
Use vm_paddr_t for physical addresses.
|
112696 |
27-Mar-2003 |
jake |
Set the cache line size for subordinate pci bridges as well as for their child devices. This fixes dma timeouts for devices behind the bridge.
Reported by: simokawa Tested by: simokawa
|
111119 |
19-Feb-2003 |
imp |
Back out M_* changes, per decision of the TRB.
Approved by: trb
|
110047 |
29-Jan-2003 |
scottl |
Fix some more missing dt_ prefixes for dma tag fields.
|
110030 |
29-Jan-2003 |
scottl |
Implement bus_dmamem_alloc_size() and bus_dmamem_free_size() as counterparts to bus_dmamem_alloc() and bus_dmamem_free(). This allows the caller to specify the size of the allocation instead of it defaulting to the max_size field of the busdma tag.
This is intended to aid in converting drivers to busdma. Lots of hardware cannot understand scatter/gather lists, which forces the driver to copy the i/o buffers to a single contiguous region before sending it to the hardware. Without these new methods, this would require a new busdma tag for each operation, or a complex internal allocator/cache for each driver.
Allocations greater than PAGE_SIZE are rounded up to the next PAGE_SIZE by contigmalloc(), so this is not suitable for multiple static allocations that would be better served by a single fixed-length subdivided allocation.
Reviewed by: jake (sparc64)
|
109623 |
21-Jan-2003 |
alfred |
Remove M_TRYWAIT/M_WAITOK/M_WAIT. Callers should use 0. Merge M_NOWAIT/M_DONTWAIT into a single flag M_NOWAIT.
|
108830 |
06-Jan-2003 |
tmm |
Change the iommu code to be able to handle more than one DVMA area per map. Use this new feature to implement iommu_dvmamap_load_mbuf() and iommu_dvmamap_load_uio() functions in terms of a new helper function, iommu_dvmamap_load_buffer(). Reimplement the iommu_dvmamap_load() to use it, too. This requires some changes to the map format; in addition to that, remove unused or redundant members. Add SBus and Psycho wrappers for the new functions, and make them available through the respective DMA tags.
|
108815 |
06-Jan-2003 |
tmm |
Prefix the members of struct bus_space_tag and struct bus_dma_tag with a uniqifier. No functional changes.
|
108805 |
06-Jan-2003 |
tmm |
Initialize the cache line size register of all PCI devices in the initial setup pass.
|
108800 |
06-Jan-2003 |
tmm |
- remove some outdated comments - tweak the announce message a bit - remove '\n's from a few panic() calls - don't use the DVMA base adress the firmware reports; instead, figure it out from the appropriate register on Sabres and let the IOMMU code choose it on Psychos. This also makes the IOMMU TSB size freely selectable.
|
108470 |
30-Dec-2002 |
schweikh |
Fix typos, mostly s/ an / a / where appropriate and a few s/an/and/ Add FreeBSD Id tag where missing.
|
107658 |
06-Dec-2002 |
tmm |
Exclude yet more interrupt mapping registers from the OBIO INO search, namely the ones for the timers, error handling and power management. The registers for the timers, power management and PCI bus b errors are reserved on Sabres (US-IIi) and can lead to false matches there. Since all of them are never used for devices on the bus, they can be omitted safely.
Approved by: re
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107477 |
01-Dec-2002 |
tmm |
Always initialize the UPA target module id in the interrupt mapping register to the one of the processor doing the interrupt setup. This is required since this field is preinitialized to 0, but there exist machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2 processors).
Add some more macros for handle the interrupt mapping registers, and rename some existing ones for consistency.
Approved by: re
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107476 |
01-Dec-2002 |
tmm |
1.) Do not look for PCI INOs in the FFB interrupt mapping registers; they are nevers used for PCI interrupts, but can cause false matches since they are fully programmable. 2.) Skip the mapping registers for slot a2 and a3 on "psycho" bridges, since they are not present there. Again, this could cause false matches, which would result in the interrupt being delivered at most once.
Submitted by: jake (2) Approved by: re
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107472 |
01-Dec-2002 |
tmm |
Reverse the quirk table entry for swizzling on a missing interrupt map; this is now done on all machines except for some known problematic ones.
Add an additional guard to make sure that the interrupt numbers are in the correct range before swizzling. This should catch any remaining models for which the swizzle is inappropriate.
Correct the swizzle calculation to account for the fact that the parent interrupt numbers to be swizzled are 1-based.
Approved by: re
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107471 |
01-Dec-2002 |
tmm |
Fix some comments describing psycho registers.
Approved by: re
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106910 |
14-Nov-2002 |
tmm |
Don't register the powerfail interrupt as fast in the non-DEBUGGER_ON_POWERFAIL case so that shutdown_nice() can be called without problems.
Reported & tested by: Gavin Atkinson <gavin@ury.york.ac.uk>
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106555 |
07-Nov-2002 |
tmm |
Add two new workaround for firmware anomalies: 1. At least some Netra t1 models have PCI buses with no associated interrupt map, but obviously expect the PCI swizzle to be done with the interrupt number from the higher level as intpin. In this case, the mapping also needs to continue at parent bus nodes. To handle that, add a quirk table based on the "name" property of the root node to avoid breaking other boxen. This property is now retrieved and printed at boot. 2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped at all, and full interrupt numbers (not just INOs) are given in the interrupt properties. This is more or less cosmetical; the PCI interrupt numbers would be wrong, but the psycho resource allocation method would pass the right numbers on anyway.
Tested by: mux (1), Maxim Mazurok <maxim@km.ua> (2)
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105283 |
16-Oct-2002 |
tmm |
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this.
These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
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105274 |
16-Oct-2002 |
tmm |
Use a linked list to keep the psycho softcs instead of a statically sized array. While being there, deuglify the psycho pair detection loop which became quite awkward in a previous code reorganization.
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104075 |
28-Sep-2002 |
jake |
Renamed intr_enqueue to intr_vector and intr_dequeue to intr_fast, to better reflect how they are called.
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100188 |
16-Jul-2002 |
tmm |
When multiple IOMMUs are present in a system, use a single TSB for all of them, and couple them by always performing all operations on all present IOMMUs. This is required because with the current API there is no way to determine on which bus a busdma operation is performed.
While being there, clean up the iommu code a bit.
This should be a step in the direction of allow some of larger machines to work; tests have shown that there still seem to be problems left.
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98148 |
12-Jun-2002 |
tmm |
Add PCI bus enumeration and latency timer setup to the sparc64 MD PCI code. Both tasks are not always performed completely by the firmware. The former is required to get some e450 models to boot; the latter fixes the repeated fifo underruns with hme(4)s and gem(4)s observed on some machines (and probably performance problems with other peripherals as well).
|
93682 |
02-Apr-2002 |
tmm |
Do not try to set up the PCI bus B error interrupt on "sabre"s, since it is only available on "psycho"s. The same applies to the power management interrupt, which is not enabled by default though.
|
93070 |
24-Mar-2002 |
tmm |
Revamp the busdma implementation a bit: - change the IOMMU support code so that it supports overcommittting the available DVMA memory, while still allocating as lazily as possible. This is achieved by limiting the preallocation, and deferring the allocation to map load time when it fails. In the latter case, the DVMA memory reserved for unloaded maps can be stolen to free up enough memory for loading a map. - allow NULL settings in the method tables, and search the parent tags until an appropriate implementation is found. This allows to remove some kluges in the old implementation.
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93067 |
24-Mar-2002 |
tmm |
Make the OpenFirmware interrupt mapping code more generic, to reduce the bus-dependent code and to be able to support more systems. The core of the new code is mostly obtained from NetBSD. Kluge the interrupt routing methods of the psycho and apb drivers so that an intline of 0 can be handled for now; real routing is still not possible (all intline registers are preinitialized instead); this will require a sparc64-specific adaption of the driver for generic PCI-PCI bridges with a custom routing method to work right.
|
93066 |
24-Mar-2002 |
tmm |
Map the device memory belonging to resources of type SYS_RES_MEMORY into KVA upon activation so that rman_get_virtual() works as expected.
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93053 |
23-Mar-2002 |
tmm |
Add code to print the fault virtual address for uncorrectable DMA errors caused by IOMMU misses to aid debugging. This will only work on UltraSPARC-IIi and IIe.
|
93046 |
23-Mar-2002 |
tmm |
Add PCIfunctions 2 and 3 of the PCIO2 chip to the intpin quirk table.
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92212 |
13-Mar-2002 |
jake |
Add a DEBUGGER_ON_POWERFAIL option. This makes the power button on ultra 10s work like an NMI button.
|
90617 |
13-Feb-2002 |
tmm |
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
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90613 |
13-Feb-2002 |
tmm |
Don't panic when no interrupt map can be found for a PCI bus; this seems to happen on some models, like the Netra T1.
|
88823 |
02-Jan-2002 |
tmm |
Correct the defintion of struct ofw_upa_regs, and use it instead of struct ofw_nexus_reg. Implement UPA device memory management in the nexus driver. Adapt the psycho driver to these changes, and do some minor cleanup work while being there.
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88701 |
30-Dec-2001 |
tmm |
Do not include pcib.h, which only existed in my development tree, and do not use struct pcib_softc when struct apb_softc would be correct.
Spotted by: jake Pointy hat to: tmm
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88371 |
21-Dec-2001 |
tmm |
Add a workaround for quirky PCI devices that set the intpin register to 0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
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88369 |
21-Dec-2001 |
tmm |
Make the apb driver independent of the standard PCI bridge driver.
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86234 |
09-Nov-2001 |
tmm |
Add a file forgotten in the previous commit (a kobj interface that defines methods that need to be implemented by sparc64 host bridge drivers).
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86231 |
09-Nov-2001 |
tmm |
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
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