pccbb_pci.c revision 280970
1/*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29/*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59/* 60 * Driver for PCI to CardBus Bridge chips 61 * 62 * References: 63 * TI Datasheets: 64 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 65 * 66 * Written by Jonathan Chen <jon@freebsd.org> 67 * The author would like to acknowledge: 68 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 69 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 70 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 71 * * David Cross: Author of the initial ugly hack for a specific cardbus card 72 */ 73 74#include <sys/cdefs.h> 75__FBSDID("$FreeBSD: stable/10/sys/dev/pccbb/pccbb_pci.c 280970 2015-04-01 21:48:54Z jhb $"); 76 77#include <sys/param.h> 78#include <sys/systm.h> 79#include <sys/proc.h> 80#include <sys/condvar.h> 81#include <sys/errno.h> 82#include <sys/kernel.h> 83#include <sys/lock.h> 84#include <sys/malloc.h> 85#include <sys/mutex.h> 86#include <sys/sysctl.h> 87#include <sys/kthread.h> 88#include <sys/bus.h> 89#include <machine/bus.h> 90#include <sys/rman.h> 91#include <machine/resource.h> 92#include <sys/module.h> 93 94#include <dev/pci/pcireg.h> 95#include <dev/pci/pcivar.h> 96#include <dev/pci/pcib_private.h> 97 98#include <dev/pccard/pccardreg.h> 99#include <dev/pccard/pccardvar.h> 100 101#include <dev/exca/excareg.h> 102#include <dev/exca/excavar.h> 103 104#include <dev/pccbb/pccbbreg.h> 105#include <dev/pccbb/pccbbvar.h> 106 107#include "power_if.h" 108#include "card_if.h" 109#include "pcib_if.h" 110 111#define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 112#define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 113 114#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 115 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 116#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 117 pci_write_config(DEV, REG, ( \ 118 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 119 120static void cbb_chipinit(struct cbb_softc *sc); 121static int cbb_pci_filt(void *arg); 122 123static struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127} yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 163 164 /* ENE */ 165 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 170 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 171 172 /* Ricoh chips */ 173 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 174 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 175 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 176 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 177 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 178 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 179 180 /* Toshiba products */ 181 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 182 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 183 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 184 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 185 186 /* Cirrus Logic */ 187 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 188 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 189 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 190 191 /* 02Micro */ 192 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 203 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 204 205 /* SMC */ 206 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 207 208 /* sentinel */ 209 {0 /* null id */, "unknown", CB_UNKNOWN}, 210}; 211 212/************************************************************************/ 213/* Probe/Attach */ 214/************************************************************************/ 215 216static int 217cbb_chipset(uint32_t pci_id, const char **namep) 218{ 219 struct yenta_chipinfo *ycp; 220 221 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 222 continue; 223 if (namep != NULL) 224 *namep = ycp->yc_name; 225 return (ycp->yc_chiptype); 226} 227 228static int 229cbb_pci_probe(device_t brdev) 230{ 231 const char *name; 232 uint32_t progif; 233 uint32_t baseclass; 234 uint32_t subclass; 235 236 /* 237 * Do we know that we support the chipset? If so, then we 238 * accept the device. 239 */ 240 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 241 device_set_desc(brdev, name); 242 return (BUS_PROBE_DEFAULT); 243 } 244 245 /* 246 * We do support generic CardBus bridges. All that we've seen 247 * to date have progif 0 (the Yenta spec, and successors mandate 248 * this). 249 */ 250 baseclass = pci_get_class(brdev); 251 subclass = pci_get_subclass(brdev); 252 progif = pci_get_progif(brdev); 253 if (baseclass == PCIC_BRIDGE && 254 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 255 device_set_desc(brdev, "PCI-CardBus Bridge"); 256 return (BUS_PROBE_GENERIC); 257 } 258 return (ENXIO); 259} 260 261/* 262 * Still need this because the pci code only does power for type 0 263 * header devices. 264 */ 265static void 266cbb_powerstate_d0(device_t dev) 267{ 268 u_int32_t membase, irq; 269 270 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 271 /* Save important PCI config data. */ 272 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 273 irq = pci_read_config(dev, PCIR_INTLINE, 4); 274 275 /* Reset the power state. */ 276 device_printf(dev, "chip is in D%d power mode " 277 "-- setting to D0\n", pci_get_powerstate(dev)); 278 279 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 280 281 /* Restore PCI config data. */ 282 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 283 pci_write_config(dev, PCIR_INTLINE, irq, 4); 284 } 285} 286 287/* 288 * Print out the config space 289 */ 290static void 291cbb_print_config(device_t dev) 292{ 293 int i; 294 295 device_printf(dev, "PCI Configuration space:"); 296 for (i = 0; i < 256; i += 4) { 297 if (i % 16 == 0) 298 printf("\n 0x%02x: ", i); 299 printf("0x%08x ", pci_read_config(dev, i, 4)); 300 } 301 printf("\n"); 302} 303 304static int 305cbb_pci_attach(device_t brdev) 306{ 307#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 308 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 309 uint32_t pribus; 310#endif 311 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 312 struct sysctl_ctx_list *sctx; 313 struct sysctl_oid *soid; 314 int rid; 315 device_t parent; 316 317 parent = device_get_parent(brdev); 318 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 319 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 320 sc->dev = brdev; 321 sc->cbdev = NULL; 322 sc->exca[0].pccarddev = NULL; 323 sc->domain = pci_get_domain(brdev); 324 sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); 325 sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 326 sc->pribus = pcib_get_bus(parent); 327#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 328 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 329 pcib_setup_secbus(brdev, &sc->bus, 1); 330#endif 331 SLIST_INIT(&sc->rl); 332 cbb_powerstate_d0(brdev); 333 334 rid = CBBR_SOCKBASE; 335 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 336 RF_ACTIVE); 337 if (!sc->base_res) { 338 device_printf(brdev, "Could not map register memory\n"); 339 mtx_destroy(&sc->mtx); 340 return (ENOMEM); 341 } else { 342 DEVPRINTF((brdev, "Found memory at %08lx\n", 343 rman_get_start(sc->base_res))); 344 } 345 346 sc->bst = rman_get_bustag(sc->base_res); 347 sc->bsh = rman_get_bushandle(sc->base_res); 348 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 349 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 350 sc->exca[0].chipset = EXCA_CARDBUS; 351 sc->chipinit = cbb_chipinit; 352 sc->chipinit(sc); 353 354 /*Sysctls*/ 355 sctx = device_get_sysctl_ctx(brdev); 356 soid = device_get_sysctl_tree(brdev); 357 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 358 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 359 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 360 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 361 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 362 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 363 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 364 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 365#if 0 366 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 367 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 368 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 369 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memroy window open"); 370 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 371 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 372 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 373 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 374#endif 375 376#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 377 /* 378 * This is a gross hack. We should be scanning the entire pci 379 * tree, assigning bus numbers in a way such that we (1) can 380 * reserve 1 extra bus just in case and (2) all sub busses 381 * are in an appropriate range. 382 */ 383 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); 384 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 385 if (sc->bus.sec == 0 || sc->pribus != pribus) { 386 if (curr_bus_number <= sc->pribus) 387 curr_bus_number = sc->pribus + 1; 388 if (pribus != sc->pribus) { 389 DEVPRINTF((brdev, "Setting primary bus to %d\n", 390 sc->pribus)); 391 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 392 } 393 sc->bus.sec = curr_bus_number++; 394 sc->bus.sub = curr_bus_number++; 395 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 396 sc->bus.sec, sc->bus.sub)); 397 pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1); 398 pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1); 399 } 400#endif 401 402 /* attach children */ 403 sc->cbdev = device_add_child(brdev, "cardbus", -1); 404 if (sc->cbdev == NULL) 405 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 406 else if (device_probe_and_attach(sc->cbdev) != 0) 407 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 408 409 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 410 if (sc->exca[0].pccarddev == NULL) 411 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 412 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 413 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 414 415 /* Map and establish the interrupt. */ 416 rid = 0; 417 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 418 RF_SHAREABLE | RF_ACTIVE); 419 if (sc->irq_res == NULL) { 420 device_printf(brdev, "Unable to map IRQ...\n"); 421 goto err; 422 } 423 424 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 425 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 426 device_printf(brdev, "couldn't establish interrupt\n"); 427 goto err; 428 } 429 430 /* reset 16-bit pcmcia bus */ 431 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 432 433 /* turn off power */ 434 cbb_power(brdev, CARD_OFF); 435 436 /* CSC Interrupt: Card detect interrupt on */ 437 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 438 439 /* reset interrupt */ 440 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 441 442 if (bootverbose) 443 cbb_print_config(brdev); 444 445 /* Start the thread */ 446 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 447 "%s event thread", device_get_nameunit(brdev))) { 448 device_printf(brdev, "unable to create event thread.\n"); 449 panic("cbb_create_event_thread"); 450 } 451 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 452 return (0); 453err: 454 if (sc->irq_res) 455 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 456 if (sc->base_res) { 457 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 458 sc->base_res); 459 } 460 mtx_destroy(&sc->mtx); 461 return (ENOMEM); 462} 463 464static void 465cbb_chipinit(struct cbb_softc *sc) 466{ 467 uint32_t mux, sysctrl, reg; 468 469 /* Set CardBus latency timer */ 470 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 471 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 472 473 /* Set PCI latency timer */ 474 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 475 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 476 477 /* Restore bus configuration */ 478 pci_write_config(sc->dev, PCIR_PRIBUS_2, sc->pribus, 1); 479 pci_write_config(sc->dev, PCIR_SECBUS_2, sc->bus.sec, 1); 480 pci_write_config(sc->dev, PCIR_SUBBUS_2, sc->bus.sub, 1); 481 482 /* Enable memory access */ 483 pci_enable_busmaster(sc->dev); 484 /* XXX: This should not be necessary, but some chipsets require it */ 485 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, | PCIM_CMD_PORTEN, 2); 486 487 /* disable Legacy IO */ 488 switch (sc->chipset) { 489 case CB_RF5C46X: 490 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 491 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 492 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 493 break; 494 default: 495 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 496 break; 497 } 498 499 /* Use PCI interrupt for interrupt routing */ 500 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 501 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 502 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 503 | CBBM_BRIDGECTRL_WRITE_POST_EN, 504 2); 505 506 /* 507 * XXX this should be a function table, ala OLDCARD. This means 508 * that we could more easily support ISA interrupts for pccard 509 * cards if we had to. 510 */ 511 switch (sc->chipset) { 512 case CB_TI113X: 513 /* 514 * The TI 1031, TI 1130 and TI 1131 all require another bit 515 * be set to enable PCI routing of interrupts, and then 516 * a bit for each of the CSC and Function interrupts we 517 * want routed. 518 */ 519 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 520 | CBBM_CBCTRL_113X_PCI_INTR | 521 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 522 1); 523 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 524 & ~(CBBM_DEVCTRL_INT_SERIAL | 525 CBBM_DEVCTRL_INT_PCI), 1); 526 break; 527 case CB_TI12XX: 528 /* 529 * Some TI 12xx (and [14][45]xx) based pci cards 530 * sometimes have issues with the MFUNC register not 531 * being initialized due to a bad EEPROM on board. 532 * Laptops that this matters on have this register 533 * properly initialized. 534 * 535 * The TI125X parts have a different register. 536 */ 537 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 538 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 539 if (mux == 0) { 540 mux = (mux & ~CBBM_MFUNC_PIN0) | 541 CBBM_MFUNC_PIN0_INTA; 542 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 543 mux = (mux & ~CBBM_MFUNC_PIN1) | 544 CBBM_MFUNC_PIN1_INTB; 545 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 546 } 547 /*FALLTHROUGH*/ 548 case CB_TI125X: 549 /* 550 * Disable zoom video. Some machines initialize this 551 * improperly and exerpience has shown that this helps 552 * prevent strange behavior. 553 */ 554 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 555 break; 556 case CB_O2MICRO: 557 /* 558 * Issue #1: INT# generated at the same time as 559 * selected ISA IRQ. When IREQ# or STSCHG# is active, 560 * in addition to the ISA IRQ being generated, INT# 561 * will also be generated at the same time. 562 * 563 * Some of the older controllers have an issue in 564 * which the slot's PCI INT# will be asserted whenever 565 * IREQ# or STSCGH# is asserted even if ExCA registers 566 * 03h or 05h have an ISA IRQ selected. 567 * 568 * The fix for this issue, which will work for any 569 * controller (old or new), is to set ExCA registers 570 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 571 * These bits are undocumented. By setting this 572 * register (of each slot) to '1010xxxxb' a routing of 573 * IREQ# to INTC# and STSCHG# to INTC# is selected. 574 * Since INTC# isn't connected there will be no 575 * unexpected PCI INT when IREQ# or STSCHG# is active. 576 * However, INTA# (slot 0) or INTB# (slot 1) will 577 * still be correctly generated if NO ISA IRQ is 578 * selected (ExCA regs 03h or 05h are cleared). 579 */ 580 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 581 reg = (reg & 0x0f) | 582 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 583 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 584 break; 585 case CB_TOPIC97: 586 /* 587 * Disable Zoom Video, ToPIC 97, 100. 588 */ 589 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 590 /* 591 * ToPIC 97, 100 592 * At offset 0xa1: INTERRUPT CONTROL register 593 * 0x1: Turn on INT interrupts. 594 */ 595 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 596 | TOPIC97_INTCTRL_INTIRQSEL, 1); 597 /* 598 * ToPIC97, 100 599 * Need to assert support for low voltage cards 600 */ 601 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL, 602 EXCA_TOPIC97_CTRL_LV_MASK); 603 goto topic_common; 604 case CB_TOPIC95: 605 /* 606 * SOCKETCTRL appears to be TOPIC 95/B specific 607 */ 608 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 609 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 610 611 topic_common:; 612 /* 613 * At offset 0xa0: SLOT CONTROL 614 * 0x80 Enable CardBus Functionality 615 * 0x40 Enable CardBus and PC Card registers 616 * 0x20 Lock ID in exca regs 617 * 0x10 Write protect ID in config regs 618 * Clear the rest of the bits, which defaults the slot 619 * in legacy mode to 0x3e0 and offset 0. (legacy 620 * mode is determined elsewhere) 621 */ 622 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 623 TOPIC_SLOTCTRL_SLOTON | 624 TOPIC_SLOTCTRL_SLOTEN | 625 TOPIC_SLOTCTRL_ID_LOCK | 626 TOPIC_SLOTCTRL_ID_WP, 1); 627 628 /* 629 * At offset 0xa3 Card Detect Control Register 630 * 0x80 CARDBUS enbale 631 * 0x01 Cleared for hardware change detect 632 */ 633 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 634 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 635 break; 636 } 637 638 /* 639 * Need to tell ExCA registers to CSC interrupts route via PCI 640 * interrupts. There are two ways to do this. One is to set 641 * INTR_ENABLE and the other is to set CSC to 0. Since both 642 * methods are mutually compatible, we do both. 643 */ 644 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 645 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 646 647 cbb_disable_func_intr(sc); 648 649 /* close all memory and io windows */ 650 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 651 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 652 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 653 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 654 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 655 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 656 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 657 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 658} 659 660static int 661cbb_route_interrupt(device_t pcib, device_t dev, int pin) 662{ 663 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 664 665 return (rman_get_start(sc->irq_res)); 666} 667 668static int 669cbb_pci_shutdown(device_t brdev) 670{ 671 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 672 673 /* 674 * We're about to pull the rug out from the card, so mark it as 675 * gone to prevent harm. 676 */ 677 sc->cardok = 0; 678 679 /* 680 * Place the cards in reset, turn off the interrupts and power 681 * down the socket. 682 */ 683 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 684 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 685 cbb_set(sc, CBB_SOCKET_MASK, 0); 686 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 687 cbb_power(brdev, CARD_OFF); 688 689 /* 690 * For paranoia, turn off all address decoding. Really not needed, 691 * it seems, but it can't hurt 692 */ 693 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 694 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 695 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 696 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 697 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 698 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 699 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 700 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 701 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 702 return (0); 703} 704 705static int 706cbb_pci_filt(void *arg) 707{ 708 struct cbb_softc *sc = arg; 709 uint32_t sockevent; 710 uint8_t csc; 711 int retval = FILTER_STRAY; 712 713 /* 714 * Some chips also require us to read the old ExCA registe for card 715 * status change when we route CSC vis PCI. This isn't supposed to be 716 * required, but it clears the interrupt state on some chipsets. 717 * Maybe there's a setting that would obviate its need. Maybe we 718 * should test the status bits and deal with them, but so far we've 719 * not found any machines that don't also give us the socket status 720 * indication above. 721 * 722 * This call used to be unconditional. However, further research 723 * suggests that we hit this condition when the card READY interrupt 724 * fired. So now we only read it for 16-bit cards, and we only claim 725 * the interrupt if READY is set. If this still causes problems, then 726 * the next step would be to read this if we have a 16-bit card *OR* 727 * we have no card. We treat the READY signal as if it were the power 728 * completion signal. Some bridges may double signal things here, bit 729 * signalling twice should be OK since we only sleep on the powerintr 730 * in one place and a double wakeup would be benign there. 731 */ 732 if (sc->flags & CBB_16BIT_CARD) { 733 csc = exca_getb(&sc->exca[0], EXCA_CSC); 734 if (csc & EXCA_CSC_READY) { 735 atomic_add_int(&sc->powerintr, 1); 736 wakeup((void *)&sc->powerintr); 737 retval = FILTER_HANDLED; 738 } 739 } 740 741 /* 742 * Read the socket event. Sometimes, the theory goes, the PCI bus is 743 * so loaded that it cannot satisfy the read request, so we get 744 * garbage back from the following read. We have to filter out the 745 * garbage so that we don't spontaneously reset the card under high 746 * load. PCI isn't supposed to act like this. No doubt this is a bug 747 * in the PCI bridge chipset (or cbb brige) that's being used in 748 * certain amd64 laptops today. Work around the issue by assuming 749 * that any bits we don't know about being set means that we got 750 * garbage. 751 */ 752 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 753 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 754 /* 755 * If anything has happened to the socket, we assume that the 756 * card is no longer OK, and we shouldn't call its ISR. We 757 * set cardok as soon as we've attached the card. This helps 758 * in a noisy eject, which happens all too often when users 759 * are ejecting their PC Cards. 760 * 761 * We use this method in preference to checking to see if the 762 * card is still there because the check suffers from a race 763 * condition in the bouncing case. 764 */ 765#define DELTA (CBB_SOCKET_MASK_CD) 766 if (sockevent & DELTA) { 767 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 768 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 769 sc->cardok = 0; 770 cbb_disable_func_intr(sc); 771 wakeup(&sc->intrhand); 772 } 773#undef DELTA 774 775 /* 776 * Wakeup anybody waiting for a power interrupt. We have to 777 * use atomic_add_int for wakups on other cores. 778 */ 779 if (sockevent & CBB_SOCKET_EVENT_POWER) { 780 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 781 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 782 atomic_add_int(&sc->powerintr, 1); 783 wakeup((void *)&sc->powerintr); 784 } 785 786 /* 787 * Status change interrupts aren't presently used in the 788 * rest of the driver. For now, just ACK them. 789 */ 790 if (sockevent & CBB_SOCKET_EVENT_CSTS) 791 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 792 retval = FILTER_HANDLED; 793 } 794 return retval; 795} 796 797#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 798static struct resource * 799cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 800 u_long start, u_long end, u_long count, u_int flags) 801{ 802 struct cbb_softc *sc; 803 804 sc = device_get_softc(bus); 805 if (type == PCI_RES_BUS) 806 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 807 count, flags)); 808 return (cbb_alloc_resource(bus, child, type, rid, start, end, count, 809 flags)); 810} 811 812static int 813cbb_pci_adjust_resource(device_t bus, device_t child, int type, 814 struct resource *r, u_long start, u_long end) 815{ 816 struct cbb_softc *sc; 817 818 sc = device_get_softc(bus); 819 if (type == PCI_RES_BUS) { 820 if (!rman_is_region_manager(r, &sc->bus.rman)) 821 return (EINVAL); 822 return (rman_adjust_resource(r, start, end)); 823 } 824 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 825} 826 827static int 828cbb_pci_release_resource(device_t bus, device_t child, int type, int rid, 829 struct resource *r) 830{ 831 struct cbb_softc *sc; 832 int error; 833 834 sc = device_get_softc(bus); 835 if (type == PCI_RES_BUS) { 836 if (!rman_is_region_manager(r, &sc->bus.rman)) 837 return (EINVAL); 838 if (rman_get_flags(r) & RF_ACTIVE) { 839 error = bus_deactivate_resource(child, type, rid, r); 840 if (error) 841 return (error); 842 } 843 return (rman_release_resource(r)); 844 } 845 return (cbb_release_resource(bus, child, type, rid, r)); 846} 847#endif 848 849/************************************************************************/ 850/* PCI compat methods */ 851/************************************************************************/ 852 853static int 854cbb_maxslots(device_t brdev) 855{ 856 return (0); 857} 858 859static uint32_t 860cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 861{ 862 /* 863 * Pass through to the next ppb up the chain (i.e. our grandparent). 864 */ 865 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 866 b, s, f, reg, width)); 867} 868 869static void 870cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 871 int width) 872{ 873 /* 874 * Pass through to the next ppb up the chain (i.e. our grandparent). 875 */ 876 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 877 b, s, f, reg, val, width); 878} 879 880static device_method_t cbb_methods[] = { 881 /* Device interface */ 882 DEVMETHOD(device_probe, cbb_pci_probe), 883 DEVMETHOD(device_attach, cbb_pci_attach), 884 DEVMETHOD(device_detach, cbb_detach), 885 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 886 DEVMETHOD(device_suspend, cbb_suspend), 887 DEVMETHOD(device_resume, cbb_resume), 888 889 /* bus methods */ 890 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 891 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 892#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 893 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), 894 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), 895 DEVMETHOD(bus_release_resource, cbb_pci_release_resource), 896#else 897 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 898 DEVMETHOD(bus_release_resource, cbb_release_resource), 899#endif 900 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 901 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 902 DEVMETHOD(bus_driver_added, cbb_driver_added), 903 DEVMETHOD(bus_child_detached, cbb_child_detached), 904 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 905 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 906 DEVMETHOD(bus_child_present, cbb_child_present), 907 908 /* 16-bit card interface */ 909 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 910 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 911 912 /* power interface */ 913 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 914 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 915 916 /* pcib compatibility interface */ 917 DEVMETHOD(pcib_maxslots, cbb_maxslots), 918 DEVMETHOD(pcib_read_config, cbb_read_config), 919 DEVMETHOD(pcib_write_config, cbb_write_config), 920 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 921 922 DEVMETHOD_END 923}; 924 925static driver_t cbb_driver = { 926 "cbb", 927 cbb_methods, 928 sizeof(struct cbb_softc) 929}; 930 931DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 932MODULE_DEPEND(cbb, exca, 1, 1, 1); 933