schizo.c revision 266020
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/schizo.c 266020 2014-05-14 14:17:51Z ian $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/sysctl.h> 56#include <sys/time.h> 57#include <sys/timetc.h> 58 59#include <dev/ofw/ofw_bus.h> 60#include <dev/ofw/ofw_pci.h> 61#include <dev/ofw/openfirm.h> 62 63#include <machine/bus.h> 64#include <machine/bus_common.h> 65#include <machine/bus_private.h> 66#include <machine/fsr.h> 67#include <machine/iommureg.h> 68#include <machine/iommuvar.h> 69#include <machine/resource.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/schizoreg.h> 76#include <sparc64/pci/schizovar.h> 77 78#include "pcib_if.h" 79 80static const struct schizo_desc *schizo_get_desc(device_t); 81static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82 driver_filter_t); 83static void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84 bus_dmasync_op_t op); 85static void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 86 bus_dmasync_op_t op); 87static void schizo_intr_enable(void *); 88static void schizo_intr_disable(void *); 89static void schizo_intr_assign(void *); 90static void schizo_intr_clear(void *); 91static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 92static int schizo_get_intrmap(struct schizo_softc *, u_int, 93 bus_addr_t *, bus_addr_t *); 94static timecounter_get_t schizo_get_timecount; 95 96/* Interrupt handlers */ 97static driver_filter_t schizo_pci_bus; 98static driver_filter_t schizo_ue; 99static driver_filter_t schizo_ce; 100static driver_filter_t schizo_host_bus; 101static driver_filter_t schizo_cdma; 102 103/* IOMMU support */ 104static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 105 106/* 107 * Methods 108 */ 109static device_probe_t schizo_probe; 110static device_attach_t schizo_attach; 111static bus_read_ivar_t schizo_read_ivar; 112static bus_setup_intr_t schizo_setup_intr; 113static bus_alloc_resource_t schizo_alloc_resource; 114static bus_activate_resource_t schizo_activate_resource; 115static bus_adjust_resource_t schizo_adjust_resource; 116static bus_get_dma_tag_t schizo_get_dma_tag; 117static pcib_maxslots_t schizo_maxslots; 118static pcib_read_config_t schizo_read_config; 119static pcib_write_config_t schizo_write_config; 120static pcib_route_interrupt_t schizo_route_interrupt; 121static ofw_bus_get_node_t schizo_get_node; 122static ofw_pci_setup_device_t schizo_setup_device; 123 124static device_method_t schizo_methods[] = { 125 /* Device interface */ 126 DEVMETHOD(device_probe, schizo_probe), 127 DEVMETHOD(device_attach, schizo_attach), 128 DEVMETHOD(device_shutdown, bus_generic_shutdown), 129 DEVMETHOD(device_suspend, bus_generic_suspend), 130 DEVMETHOD(device_resume, bus_generic_resume), 131 132 /* Bus interface */ 133 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 134 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 135 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 136 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 137 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 138 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 139 DEVMETHOD(bus_adjust_resource, schizo_adjust_resource), 140 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 141 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 142 143 /* pcib interface */ 144 DEVMETHOD(pcib_maxslots, schizo_maxslots), 145 DEVMETHOD(pcib_read_config, schizo_read_config), 146 DEVMETHOD(pcib_write_config, schizo_write_config), 147 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 148 149 /* ofw_bus interface */ 150 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 151 152 /* ofw_pci interface */ 153 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 154 155 DEVMETHOD_END 156}; 157 158static devclass_t schizo_devclass; 159 160DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 161 sizeof(struct schizo_softc)); 162EARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 163 BUS_PASS_BUS); 164 165static SLIST_HEAD(, schizo_softc) schizo_softcs = 166 SLIST_HEAD_INITIALIZER(schizo_softcs); 167 168static const struct intr_controller schizo_ic = { 169 schizo_intr_enable, 170 schizo_intr_disable, 171 schizo_intr_assign, 172 schizo_intr_clear 173}; 174 175struct schizo_icarg { 176 struct schizo_softc *sica_sc; 177 bus_addr_t sica_map; 178 bus_addr_t sica_clr; 179}; 180 181#define SCHIZO_CDMA_TIMEOUT 1 /* 1 second per try */ 182#define SCHIZO_CDMA_TRIES 15 183#define SCHIZO_PERF_CNT_QLTY 100 184 185#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 186 bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 187#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 188 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 189#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 190 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 191 192#ifndef SCHIZO_DEBUG 193#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 194 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 195#else 196#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 197 device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 198 (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 199 (unsigned long long)(v)); \ 200 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 201 } while (0) 202#endif 203 204#define SCHIZO_PCI_READ_8(sc, offs) \ 205 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 206#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 207 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 208#define SCHIZO_CTRL_READ_8(sc, offs) \ 209 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 210#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 211 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 212#define SCHIZO_PCICFG_READ_8(sc, offs) \ 213 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 214#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 215 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 216#define SCHIZO_ICON_READ_8(sc, offs) \ 217 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 218#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 219 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 220 221#define SCHIZO_PCI_SET(sc, offs, v) \ 222 SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 223#define SCHIZO_CTRL_SET(sc, offs, v) \ 224 SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 225 226struct schizo_desc { 227 const char *sd_string; 228 int sd_mode; 229 const char *sd_name; 230}; 231 232static const struct schizo_desc schizo_compats[] = { 233 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 234#if 0 235 { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 236#endif 237 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 238 { NULL, 0, NULL } 239}; 240 241static const struct schizo_desc * 242schizo_get_desc(device_t dev) 243{ 244 const struct schizo_desc *desc; 245 const char *compat; 246 247 compat = ofw_bus_get_compat(dev); 248 if (compat == NULL) 249 return (NULL); 250 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 251 if (strcmp(desc->sd_string, compat) == 0) 252 return (desc); 253 return (NULL); 254} 255 256static int 257schizo_probe(device_t dev) 258{ 259 const char *dtype; 260 261 dtype = ofw_bus_get_type(dev); 262 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 263 schizo_get_desc(dev) != NULL) { 264 device_set_desc(dev, "Sun Host-PCI bridge"); 265 return (0); 266 } 267 return (ENXIO); 268} 269 270static int 271schizo_attach(device_t dev) 272{ 273 struct ofw_pci_ranges *range; 274 const struct schizo_desc *desc; 275 struct schizo_softc *asc, *sc, *osc; 276 struct timecounter *tc; 277 uint64_t ino_bitmap, reg; 278 phandle_t node; 279 uint32_t prop, prop_array[2]; 280 int i, j, mode, rid, tsbsize; 281 282 sc = device_get_softc(dev); 283 node = ofw_bus_get_node(dev); 284 desc = schizo_get_desc(dev); 285 mode = desc->sd_mode; 286 287 sc->sc_dev = dev; 288 sc->sc_node = node; 289 sc->sc_mode = mode; 290 sc->sc_flags = 0; 291 292 /* 293 * The Schizo has three register banks: 294 * (0) per-PBM PCI configuration and status registers, but for bus B 295 * shared with the UPA64s interrupt mapping register banks 296 * (1) shared Schizo controller configuration and status registers 297 * (2) per-PBM PCI configuration space 298 * 299 * The Tomatillo has four register banks: 300 * (0) per-PBM PCI configuration and status registers 301 * (1) per-PBM Tomatillo controller configuration registers, but on 302 * machines having the `jbusppm' device shared with its Estar 303 * register bank for bus A 304 * (2) per-PBM PCI configuration space 305 * (3) per-PBM interrupt concentrator registers 306 */ 307 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 308 20) & 1; 309 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 310 i++) { 311 rid = i; 312 sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 313 SYS_RES_MEMORY, &rid, 314 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 315 i == STX_PCI) || i == STX_CTRL)) || 316 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 317 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 318 if (sc->sc_mem_res[i] == NULL) 319 panic("%s: could not allocate register bank %d", 320 __func__, i); 321 } 322 323 /* 324 * Match other Schizos that are already configured against 325 * the controller base physical address. This will be the 326 * same for a pair of devices that share register space. 327 */ 328 osc = NULL; 329 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 330 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 331 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 332 /* Found partner. */ 333 osc = asc; 334 break; 335 } 336 } 337 if (osc == NULL) { 338 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 339 M_NOWAIT | M_ZERO); 340 if (sc->sc_mtx == NULL) 341 panic("%s: could not malloc mutex", __func__); 342 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 343 } else { 344 if (sc->sc_mode != SCHIZO_MODE_SCZ) 345 panic("%s: no partner expected", __func__); 346 if (mtx_initialized(osc->sc_mtx) == 0) 347 panic("%s: mutex not initialized", __func__); 348 sc->sc_mtx = osc->sc_mtx; 349 } 350 351 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 352 panic("%s: could not determine IGN", __func__); 353 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 354 -1) 355 panic("%s: could not determine version", __func__); 356 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 357 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 358 panic("%s: could not determine module-revision", __func__); 359 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 360 prop = 33000000; 361 362 if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 363 XMS_PCI_CTRL_X_MODE) != 0) { 364 if (sc->sc_mrev < 1) 365 panic("PCI-X mode unsupported"); 366 sc->sc_flags |= SCHIZO_FLAGS_XMODE; 367 } 368 369 device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 370 if (mode == SCHIZO_MODE_XMS) 371 printf("module-revision %d, ", sc->sc_mrev); 372 printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 373 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 374 "-X" : "", prop / 1000 / 1000); 375 376 /* Set up the PCI interrupt retry timer. */ 377 SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 378 379 /* Set up the PCI control register. */ 380 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 381 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 382 STX_PCI_CTRL_ARB_MASK); 383 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 384 STX_PCI_CTRL_ERR_IEN; 385 if (OF_getproplen(node, "no-bus-parking") < 0) 386 reg |= STX_PCI_CTRL_ARB_PARK; 387 if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 388 reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 389 else 390 reg |= STX_PCI_CTRL_ARB_MASK; 391 if (mode == SCHIZO_MODE_TOM) { 392 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 393 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 394 reg |= TOM_PCI_CTRL_DTO_IEN; 395 else 396 reg |= STX_PCI_CTRL_PTO; 397 } else if (mode == SCHIZO_MODE_XMS) { 398 SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 399 SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 400 reg |= XMS_PCI_CTRL_X_ERRINT_EN; 401 } 402 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 403 404 /* Set up the PCI diagnostic register. */ 405 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 406 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 407 STX_PCI_DIAG_INTRSYNC_DIS); 408 SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 409 410 /* 411 * Enable DMA write parity error interrupts of version >= 7 (i.e. 412 * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 413 * no effect though). 414 */ 415 if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 416 mode == SCHIZO_MODE_XMS) { 417 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 418 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 419 SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 420 } 421 422 /* 423 * On Tomatillo clear the I/O prefetch lengths (workaround for a 424 * Jalapeno bug). 425 */ 426 if (mode == SCHIZO_MODE_TOM) 427 SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 428 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 429 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 430 431 /* 432 * Hunt through all the interrupt mapping regs and register 433 * the interrupt controller for our interrupt vectors. We do 434 * this early in order to be able to catch stray interrupts. 435 * This is complicated by the fact that a pair of Schizo PBMs 436 * shares one IGN. 437 */ 438 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 439 sizeof(prop_array)); 440 if (i != -1) 441 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 442 else { 443 /* 444 * If the ino-bitmap property is missing, just provide the 445 * default set of interrupts for this controller and let 446 * schizo_setup_intr() take care of child interrupts. 447 */ 448 if (sc->sc_half == 0) 449 ino_bitmap = (1ULL << STX_UE_INO) | 450 (1ULL << STX_CE_INO) | 451 (1ULL << STX_PCIERR_A_INO) | 452 (1ULL << STX_BUS_INO); 453 else 454 ino_bitmap = 1ULL << STX_PCIERR_B_INO; 455 } 456 for (i = 0; i <= STX_MAX_INO; i++) { 457 if ((ino_bitmap & (1ULL << i)) == 0) 458 continue; 459 if (i == STX_FB0_INO || i == STX_FB1_INO) 460 /* Leave for upa(4). */ 461 continue; 462 j = schizo_intr_register(sc, i); 463 if (j != 0) 464 device_printf(dev, "could not register interrupt " 465 "controller for INO %d (%d)\n", i, j); 466 } 467 468 /* 469 * Setup Safari/JBus performance counter 0 in bus cycle counting 470 * mode as timecounter. Unfortunately, this is broken with at 471 * least the version 4 Tomatillos found in Fire V120 and Blade 472 * 1500, which apparently actually count some different event at 473 * ~0.5 and 3MHz respectively instead (also when running in full 474 * power mode). Besides, one counter seems to be shared by a 475 * "pair" of Tomatillos, too. 476 */ 477 if (sc->sc_half == 0) { 478 SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 479 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 480 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 481 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 482 if (tc == NULL) 483 panic("%s: could not malloc timecounter", __func__); 484 tc->tc_get_timecount = schizo_get_timecount; 485 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 486 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 487 sizeof(prop)) == -1) 488 panic("%s: could not determine clock frequency", 489 __func__); 490 tc->tc_frequency = prop; 491 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 492 if (mode == SCHIZO_MODE_SCZ) 493 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 494 else 495 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 496 tc->tc_priv = sc; 497 tc_init(tc); 498 } 499 500 /* 501 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 502 * one per PBM. Schizo and XMITS additionally have a streaming 503 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 504 * affected by several errata though. However, except for context 505 * flushes, taking advantage of it should be okay even with those. 506 */ 507 memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 508 sizeof(sc->sc_dma_methods)); 509 sc->sc_is.sis_sc = sc; 510 sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 511 sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 512 sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 513 if (OF_getproplen(node, "no-streaming-cache") < 0) 514 sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 515 516#define TSBCASE(x) \ 517 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 518 tsbsize = (x); \ 519 break; \ 520 521 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 522 sizeof(prop_array)); 523 if (i == -1 || i != sizeof(prop_array)) 524 schizo_iommu_init(sc, 7, -1); 525 else { 526 switch (prop_array[1]) { 527 TSBCASE(1); 528 TSBCASE(2); 529 TSBCASE(3); 530 TSBCASE(4); 531 TSBCASE(5); 532 TSBCASE(6); 533 TSBCASE(7); 534 TSBCASE(8); 535 default: 536 panic("%s: unsupported DVMA size 0x%x", 537 __func__, prop_array[1]); 538 /* NOTREACHED */ 539 } 540 schizo_iommu_init(sc, tsbsize, prop_array[0]); 541 } 542 543#undef TSBCASE 544 545 /* Initialize memory and I/O rmans. */ 546 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 547 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 548 if (rman_init(&sc->sc_pci_io_rman) != 0 || 549 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 550 panic("%s: failed to set up I/O rman", __func__); 551 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 552 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 553 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 554 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 555 panic("%s: failed to set up memory rman", __func__); 556 557 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 558 /* 559 * Make sure that the expected ranges are present. The 560 * OFW_PCI_CS_MEM64 one is not currently used though. 561 */ 562 if (i != STX_NRANGE) 563 panic("%s: unsupported number of ranges", __func__); 564 /* 565 * Find the addresses of the various bus spaces. 566 * There should not be multiple ones of one kind. 567 * The physical start addresses of the ranges are the configuration, 568 * memory and I/O handles. 569 */ 570 for (i = 0; i < STX_NRANGE; i++) { 571 j = OFW_PCI_RANGE_CS(&range[i]); 572 if (sc->sc_pci_bh[j] != 0) 573 panic("%s: duplicate range for space %d", 574 __func__, j); 575 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 576 } 577 free(range, M_OFWPROP); 578 579 /* Register the softc, this is needed for paired Schizos. */ 580 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 581 582 /* Allocate our tags. */ 583 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 584 sc->sc_mem_res[STX_PCI]), PCI_IO_BUS_SPACE, NULL); 585 if (sc->sc_pci_iot == NULL) 586 panic("%s: could not allocate PCI I/O tag", __func__); 587 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 588 sc->sc_mem_res[STX_PCI]), PCI_CONFIG_BUS_SPACE, NULL); 589 if (sc->sc_pci_cfgt == NULL) 590 panic("%s: could not allocate PCI configuration space tag", 591 __func__); 592 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 593 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 594 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 595 &sc->sc_pci_dmat) != 0) 596 panic("%s: could not create PCI DMA tag", __func__); 597 /* Customize the tag. */ 598 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 599 sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods; 600 601 /* 602 * Get the bus range from the firmware. 603 * NB: Tomatillos don't support PCI bus reenumeration. 604 */ 605 i = OF_getprop(node, "bus-range", (void *)prop_array, 606 sizeof(prop_array)); 607 if (i == -1) 608 panic("%s: could not get bus-range", __func__); 609 if (i != sizeof(prop_array)) 610 panic("%s: broken bus-range (%d)", __func__, i); 611 sc->sc_pci_secbus = prop_array[0]; 612 sc->sc_pci_subbus = prop_array[1]; 613 if (bootverbose) 614 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 615 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 616 617 /* Clear any pending PCI error bits. */ 618 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 619 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 620 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 621 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 622 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 623 624 /* 625 * Establish handlers for interesting interrupts... 626 * Someone at Sun clearly was smoking crack; with Schizos PCI 627 * bus error interrupts for one PBM can be routed to the other 628 * PBM though we obviously need to use the softc of the former 629 * as the argument for the interrupt handler and the softc of 630 * the latter as the argument for the interrupt controller. 631 */ 632 if (sc->sc_half == 0) { 633 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 634 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 635 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 636 sica_sc == osc)) 637 /* 638 * We are the driver for PBM A and either also 639 * registered the interrupt controller for us or 640 * the driver for PBM B has probed first and 641 * registered it for us. 642 */ 643 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 644 schizo_pci_bus); 645 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 646 osc != NULL) 647 /* 648 * We are the driver for PBM A but registered 649 * the interrupt controller for PBM B, i.e. the 650 * driver for PBM B attached first but couldn't 651 * set up a handler for PBM B. 652 */ 653 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 654 schizo_pci_bus); 655 } else { 656 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 657 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 658 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 659 sica_sc == osc)) 660 /* 661 * We are the driver for PBM B and either also 662 * registered the interrupt controller for us or 663 * the driver for PBM A has probed first and 664 * registered it for us. 665 */ 666 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 667 schizo_pci_bus); 668 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 669 osc != NULL) 670 /* 671 * We are the driver for PBM B but registered 672 * the interrupt controller for PBM A, i.e. the 673 * driver for PBM A attached first but couldn't 674 * set up a handler for PBM A. 675 */ 676 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 677 schizo_pci_bus); 678 } 679 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 680 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 681 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 682 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 683 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 684 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 685 686 /* 687 * According to the Schizo Errata I-13, consistent DMA flushing/ 688 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 689 * so we can't use it and need to live with the consequences. With 690 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 691 * the workaround described in Schizo Errata I-23. With Tomatillo 692 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 693 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 694 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 695 */ 696 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 697 sc->sc_mode == SCHIZO_MODE_TOM || 698 sc->sc_mode == SCHIZO_MODE_XMS) { 699 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 700 sc->sc_dma_methods.dm_dmamap_sync = 701 schizo_dmamap_sync; 702 sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 703 /* 704 * Some firmware versions include the CDMA interrupt 705 * at RID 4 but most don't. With the latter we add 706 * it ourselves at the spare RID 5. 707 */ 708 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 709 4)); 710 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 711 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 712 (void)schizo_get_intrmap(sc, i, 713 &sc->sc_cdma_map, &sc->sc_cdma_clr); 714 schizo_set_intr(sc, 4, i, schizo_cdma); 715 } else { 716 i = STX_CDMA_A_INO + sc->sc_half; 717 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 718 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 719 sc->sc_cdma_vec, 1) != 0) 720 panic("%s: failed to add CDMA " 721 "interrupt", __func__); 722 j = schizo_intr_register(sc, i); 723 if (j != 0) 724 panic("%s: could not register " 725 "interrupt controller for CDMA " 726 "(%d)", __func__, j); 727 (void)schizo_get_intrmap(sc, i, 728 &sc->sc_cdma_map, &sc->sc_cdma_clr); 729 schizo_set_intr(sc, 5, i, schizo_cdma); 730 } 731 } else { 732 if (sc->sc_mode == SCHIZO_MODE_XMS) 733 mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 734 NULL, MTX_SPIN); 735 sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 736 sc->sc_half); 737 sc->sc_dma_methods.dm_dmamap_sync = 738 ichip_dmamap_sync; 739 } 740 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 741 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 742 } 743 744 /* 745 * Set the latency timer register as this isn't always done by the 746 * firmware. 747 */ 748 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 749 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 750 751 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 752 753#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 754 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 755 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 756 (name), CTLFLAG_RD, (arg), 0, (desc)) 757 758 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 759 "DMA correctable errors"); 760 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 761 "PCI bus non-fatal errors"); 762 763#undef SCHIZO_SYSCTL_ADD_UINT 764 765 device_add_child(dev, "pci", -1); 766 return (bus_generic_attach(dev)); 767} 768 769static void 770schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 771 driver_filter_t handler) 772{ 773 u_long vec; 774 int rid; 775 776 rid = index; 777 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 778 SYS_RES_IRQ, &rid, RF_ACTIVE); 779 if (sc->sc_irq_res[index] == NULL || 780 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 781 INTIGN(vec) != sc->sc_ign || 782 intr_vectors[vec].iv_ic != &schizo_ic || 783 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 784 INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 785 &sc->sc_ihand[index]) != 0) 786 panic("%s: failed to set up interrupt %d", __func__, index); 787} 788 789static int 790schizo_intr_register(struct schizo_softc *sc, u_int ino) 791{ 792 struct schizo_icarg *sica; 793 bus_addr_t intrclr, intrmap; 794 int error; 795 796 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 797 return (ENXIO); 798 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 799 if (sica == NULL) 800 return (ENOMEM); 801 sica->sica_sc = sc; 802 sica->sica_map = intrmap; 803 sica->sica_clr = intrclr; 804#ifdef SCHIZO_DEBUG 805 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 806 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 807 (u_long)intrclr); 808#endif 809 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 810 &schizo_ic, sica)); 811 if (error != 0) 812 free(sica, M_DEVBUF); 813 return (error); 814} 815 816static int 817schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 818 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 819{ 820 bus_addr_t intrclr, intrmap; 821 uint64_t mr; 822 823 /* 824 * XXX we only look for INOs rather than INRs since the firmware 825 * may not provide the IGN and the IGN is constant for all devices 826 * on that PCI controller. 827 */ 828 829 if (ino > STX_MAX_INO) { 830 device_printf(sc->sc_dev, "out of range INO %d requested\n", 831 ino); 832 return (0); 833 } 834 835 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 836 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 837 mr = SCHIZO_PCI_READ_8(sc, intrmap); 838 if (INTINO(mr) != ino) { 839 device_printf(sc->sc_dev, 840 "interrupt map entry does not match INO (%d != %d)\n", 841 (int)INTINO(mr), ino); 842 return (0); 843 } 844 845 if (intrmapptr != NULL) 846 *intrmapptr = intrmap; 847 if (intrclrptr != NULL) 848 *intrclrptr = intrclr; 849 return (1); 850} 851 852/* 853 * Interrupt handlers 854 */ 855static int 856schizo_pci_bus(void *arg) 857{ 858 struct schizo_softc *sc = arg; 859 uint64_t afar, afsr, csr, iommu, xstat; 860 uint32_t status; 861 u_int fatal; 862 863 fatal = 0; 864 865 mtx_lock_spin(sc->sc_mtx); 866 867 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 868 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 869 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 870 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 871 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 872 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 873 else 874 xstat = 0; 875 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 876 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 877 878 /* 879 * IOMMU errors are only fatal on Tomatillo and there also only if 880 * target abort was not signaled. 881 */ 882 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 883 (iommu & TOM_PCI_IOMMU_ERR) != 0 && 884 ((status & PCIM_STATUS_STABORT) == 0 || 885 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 886 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 887 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 888 fatal = 1; 889 else if ((status & PCIM_STATUS_STABORT) != 0) 890 fatal = 1; 891 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 892 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 893 PCIM_STATUS_MDPERR)) != 0 || 894 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 895 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 896 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 897 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 898 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 899 STX_PCI_AFSR_P_UNUS)) != 0) 900 fatal = 1; 901 if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 902 XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 903 XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 904 XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 905 fatal = 1; 906 if (fatal == 0) 907 sc->sc_stats_pci_non_fatal++; 908 909 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 910 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 911 'A' + sc->sc_half, (unsigned long long)afar, 912 (unsigned long long)afsr, (unsigned long long)csr, 913 (unsigned long long)iommu, (unsigned long long)xstat, status); 914 915 /* Clear the error bits that we caught. */ 916 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 917 STX_CS_FUNC, PCIR_STATUS, status, 2); 918 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 919 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 920 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 921 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 922 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 923 924 mtx_unlock_spin(sc->sc_mtx); 925 926 if (fatal != 0) 927 panic("%s: fatal PCI bus error", 928 device_get_nameunit(sc->sc_dev)); 929 return (FILTER_HANDLED); 930} 931 932static int 933schizo_ue(void *arg) 934{ 935 struct schizo_softc *sc = arg; 936 uint64_t afar, afsr; 937 int i; 938 939 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 940 for (i = 0; i < 1000; i++) 941 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 942 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 943 break; 944 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 945 device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 946 (unsigned long long)afsr); 947 return (FILTER_HANDLED); 948} 949 950static int 951schizo_ce(void *arg) 952{ 953 struct schizo_softc *sc = arg; 954 uint64_t afar, afsr; 955 int i; 956 957 mtx_lock_spin(sc->sc_mtx); 958 959 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 960 for (i = 0; i < 1000; i++) 961 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 962 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 963 break; 964 sc->sc_stats_dma_ce++; 965 device_printf(sc->sc_dev, 966 "correctable DMA error AFAR %#llx AFSR %#llx\n", 967 (unsigned long long)afar, (unsigned long long)afsr); 968 969 /* Clear the error bits that we caught. */ 970 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 971 972 mtx_unlock_spin(sc->sc_mtx); 973 974 return (FILTER_HANDLED); 975} 976 977static int 978schizo_host_bus(void *arg) 979{ 980 struct schizo_softc *sc = arg; 981 uint64_t errlog; 982 983 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 984 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 985 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 986 (unsigned long long)errlog); 987 return (FILTER_HANDLED); 988} 989 990static int 991schizo_cdma(void *arg) 992{ 993 struct schizo_softc *sc = arg; 994 995 atomic_cmpset_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_PENDING, 996 SCHIZO_CDMA_STATE_RECEIVED); 997 return (FILTER_HANDLED); 998} 999 1000static void 1001schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 1002{ 1003 1004 /* Punch in our copies. */ 1005 sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1006 sc->sc_is.sis_is.is_bushandle = 1007 rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 1008 sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 1009 sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 1010 sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 1011 sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 1012 sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 1013 sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 1014 1015 iommu_init(device_get_nameunit(sc->sc_dev), 1016 (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 1017} 1018 1019static int 1020schizo_maxslots(device_t dev) 1021{ 1022 struct schizo_softc *sc; 1023 1024 sc = device_get_softc(dev); 1025 if (sc->sc_mode == SCHIZO_MODE_SCZ) 1026 return (sc->sc_half == 0 ? 4 : 6); 1027 1028 /* XXX: is this correct? */ 1029 return (PCI_SLOTMAX); 1030} 1031 1032static uint32_t 1033schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1034 int width) 1035{ 1036 struct schizo_softc *sc; 1037 bus_space_handle_t bh; 1038 u_long offset = 0; 1039 uint32_t r, wrd; 1040 int i; 1041 uint16_t shrt; 1042 uint8_t byte; 1043 1044 sc = device_get_softc(dev); 1045 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1046 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1047 return (-1); 1048 1049 /* 1050 * The Schizo bridges contain a dupe of their header at 0x80. 1051 */ 1052 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1053 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1054 reg + width > 0x80) 1055 return (0); 1056 1057 offset = STX_CONF_OFF(bus, slot, func, reg); 1058 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1059 switch (width) { 1060 case 1: 1061 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1062 r = byte; 1063 break; 1064 case 2: 1065 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1066 r = shrt; 1067 break; 1068 case 4: 1069 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1070 r = wrd; 1071 break; 1072 default: 1073 panic("%s: bad width", __func__); 1074 /* NOTREACHED */ 1075 } 1076 1077 if (i) { 1078#ifdef SCHIZO_DEBUG 1079 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1080 __func__, bus, slot, func, reg); 1081#endif 1082 r = -1; 1083 } 1084 return (r); 1085} 1086 1087static void 1088schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1089 u_int reg, uint32_t val, int width) 1090{ 1091 struct schizo_softc *sc; 1092 bus_space_handle_t bh; 1093 u_long offset = 0; 1094 1095 sc = device_get_softc(dev); 1096 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1097 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1098 return; 1099 1100 offset = STX_CONF_OFF(bus, slot, func, reg); 1101 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1102 switch (width) { 1103 case 1: 1104 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1105 break; 1106 case 2: 1107 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1108 break; 1109 case 4: 1110 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1111 break; 1112 default: 1113 panic("%s: bad width", __func__); 1114 /* NOTREACHED */ 1115 } 1116} 1117 1118static int 1119schizo_route_interrupt(device_t bridge, device_t dev, int pin) 1120{ 1121 struct schizo_softc *sc; 1122 struct ofw_pci_register reg; 1123 ofw_pci_intr_t pintr, mintr; 1124 1125 sc = device_get_softc(bridge); 1126 pintr = pin; 1127 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1128 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1129 NULL)) 1130 return (mintr); 1131 1132 device_printf(bridge, "could not route pin %d for device %d.%d\n", 1133 pin, pci_get_slot(dev), pci_get_function(dev)); 1134 return (PCI_INVALID_IRQ); 1135} 1136 1137static int 1138schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1139{ 1140 struct schizo_softc *sc; 1141 1142 sc = device_get_softc(dev); 1143 switch (which) { 1144 case PCIB_IVAR_DOMAIN: 1145 *result = device_get_unit(dev); 1146 return (0); 1147 case PCIB_IVAR_BUS: 1148 *result = sc->sc_pci_secbus; 1149 return (0); 1150 } 1151 return (ENOENT); 1152} 1153 1154static void 1155schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1156{ 1157 struct timeval cur, end; 1158 struct schizo_iommu_state *sis = dt->dt_cookie; 1159 struct schizo_softc *sc = sis->sis_sc; 1160 int i, res; 1161#ifdef INVARIANTS 1162 register_t pil; 1163#endif 1164 1165 if ((map->dm_flags & DMF_STREAMED) != 0) { 1166 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1167 return; 1168 } 1169 1170 if ((map->dm_flags & DMF_LOADED) == 0) 1171 return; 1172 1173 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1174 /* 1175 * Note that in order to allow this function to be called from 1176 * filters we would need to use a spin mutex for serialization 1177 * but given that these disable interrupts we have to emulate 1178 * one. 1179 */ 1180 critical_enter(); 1181 KASSERT((rdpr(pstate) & PSTATE_IE) != 0, 1182 ("%s: interrupts disabled", __func__)); 1183 KASSERT((pil = rdpr(pil)) <= PIL_BRIDGE, 1184 ("%s: PIL too low (%ld)", __func__, pil)); 1185 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1186 SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1187 ; 1188 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_map, 1189 INTMAP_ENABLE(sc->sc_cdma_vec, PCPU_GET(mid))); 1190 for (i = 0; i < SCHIZO_CDMA_TRIES; i++) { 1191 if (i > 0) 1192 printf("%s: try %d\n", __func__, i); 1193 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1194 INTCLR_RECEIVED); 1195 microuptime(&cur); 1196 end.tv_sec = SCHIZO_CDMA_TIMEOUT; 1197 end.tv_usec = 0; 1198 timevaladd(&end, &cur); 1199 for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1200 SCHIZO_CDMA_STATE_RECEIVED, 1201 SCHIZO_CDMA_STATE_IDLE)) == 0 && 1202 timevalcmp(&cur, &end, <=);) 1203 microuptime(&cur); 1204 if (res != 0) 1205 break; 1206 } 1207 if (res == 0) 1208 panic("%s: DMA does not sync", __func__); 1209 critical_exit(); 1210 } 1211 1212 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1213 membar(Sync); 1214} 1215 1216static void 1217ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1218{ 1219 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1220 struct timeval cur, end; 1221 struct schizo_iommu_state *sis = dt->dt_cookie; 1222 struct schizo_softc *sc = sis->sis_sc; 1223 register_t reg, s; 1224 1225 if ((map->dm_flags & DMF_STREAMED) != 0) { 1226 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1227 return; 1228 } 1229 1230 if ((map->dm_flags & DMF_LOADED) == 0) 1231 return; 1232 1233 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1234 if (sc->sc_mode == SCHIZO_MODE_XMS) 1235 mtx_lock_spin(&sc->sc_sync_mtx); 1236 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1237 sc->sc_sync_val); 1238 microuptime(&cur); 1239 end.tv_sec = 1; 1240 end.tv_usec = 0; 1241 timevaladd(&end, &cur); 1242 for (; ((reg = SCHIZO_PCI_READ_8(sc, 1243 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1244 timevalcmp(&cur, &end, <=);) 1245 microuptime(&cur); 1246 if ((reg & sc->sc_sync_val) != 0) 1247 panic("%s: DMA does not sync", __func__); 1248 if (sc->sc_mode == SCHIZO_MODE_XMS) 1249 mtx_unlock_spin(&sc->sc_sync_mtx); 1250 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1251 s = intr_disable(); 1252 reg = rd(fprs); 1253 wr(fprs, reg | FPRS_FEF, 0); 1254 __asm __volatile("stda %%f0, [%0] %1" 1255 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1256 membar(Sync); 1257 wr(fprs, reg, 0); 1258 intr_restore(s); 1259 return; 1260 } 1261 } 1262 1263 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1264 membar(Sync); 1265} 1266 1267static void 1268schizo_intr_enable(void *arg) 1269{ 1270 struct intr_vector *iv = arg; 1271 struct schizo_icarg *sica = iv->iv_icarg; 1272 1273 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1274 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1275} 1276 1277static void 1278schizo_intr_disable(void *arg) 1279{ 1280 struct intr_vector *iv = arg; 1281 struct schizo_icarg *sica = iv->iv_icarg; 1282 1283 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1284} 1285 1286static void 1287schizo_intr_assign(void *arg) 1288{ 1289 struct intr_vector *iv = arg; 1290 struct schizo_icarg *sica = iv->iv_icarg; 1291 1292 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1293 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1294} 1295 1296static void 1297schizo_intr_clear(void *arg) 1298{ 1299 struct intr_vector *iv = arg; 1300 struct schizo_icarg *sica = iv->iv_icarg; 1301 1302 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1303} 1304 1305static int 1306schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1307 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1308 void **cookiep) 1309{ 1310 struct schizo_softc *sc; 1311 u_long vec; 1312 int error; 1313 1314 sc = device_get_softc(dev); 1315 /* 1316 * Make sure the vector is fully specified. 1317 */ 1318 vec = rman_get_start(ires); 1319 if (INTIGN(vec) != sc->sc_ign) { 1320 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1321 return (EINVAL); 1322 } 1323 1324 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1325 /* 1326 * Ensure we use the right softc in case the interrupt 1327 * is routed to our companion PBM for some odd reason. 1328 */ 1329 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1330 sica_sc; 1331 } else if (intr_vectors[vec].iv_ic == NULL) { 1332 /* 1333 * Work around broken firmware which misses entries in 1334 * the ino-bitmap. 1335 */ 1336 error = schizo_intr_register(sc, INTINO(vec)); 1337 if (error != 0) { 1338 device_printf(dev, "could not register interrupt " 1339 "controller for vector 0x%lx (%d)\n", vec, error); 1340 return (error); 1341 } 1342 if (bootverbose) 1343 device_printf(dev, "belatedly registered as " 1344 "interrupt controller for vector 0x%lx\n", vec); 1345 } else { 1346 device_printf(dev, 1347 "invalid interrupt controller for vector 0x%lx\n", vec); 1348 return (EINVAL); 1349 } 1350 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1351 arg, cookiep)); 1352} 1353 1354static struct resource * 1355schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1356 u_long start, u_long end, u_long count, u_int flags) 1357{ 1358 struct schizo_softc *sc; 1359 struct resource *rv; 1360 struct rman *rm; 1361 1362 sc = device_get_softc(bus); 1363 switch (type) { 1364 case SYS_RES_IRQ: 1365 /* 1366 * XXX: Don't accept blank ranges for now, only single 1367 * interrupts. The other case should not happen with 1368 * the MI PCI code... 1369 * XXX: This may return a resource that is out of the 1370 * range that was specified. Is this correct...? 1371 */ 1372 if (start != end) 1373 panic("%s: XXX: interrupt range", __func__); 1374 start = end = INTMAP_VEC(sc->sc_ign, end); 1375 return (bus_generic_alloc_resource(bus, child, type, rid, 1376 start, end, count, flags)); 1377 case SYS_RES_MEMORY: 1378 rm = &sc->sc_pci_mem_rman; 1379 break; 1380 case SYS_RES_IOPORT: 1381 rm = &sc->sc_pci_io_rman; 1382 break; 1383 default: 1384 return (NULL); 1385 } 1386 1387 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 1388 child); 1389 if (rv == NULL) 1390 return (NULL); 1391 rman_set_rid(rv, *rid); 1392 1393 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type, 1394 *rid, rv) != 0) { 1395 rman_release_resource(rv); 1396 return (NULL); 1397 } 1398 return (rv); 1399} 1400 1401static int 1402schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1403 struct resource *r) 1404{ 1405 struct schizo_softc *sc; 1406 struct bus_space_tag *tag; 1407 1408 sc = device_get_softc(bus); 1409 switch (type) { 1410 case SYS_RES_IRQ: 1411 return (bus_generic_activate_resource(bus, child, type, rid, 1412 r)); 1413 case SYS_RES_MEMORY: 1414 tag = sparc64_alloc_bus_tag(r, rman_get_bustag( 1415 sc->sc_mem_res[STX_PCI]), PCI_MEMORY_BUS_SPACE, NULL); 1416 if (tag == NULL) 1417 return (ENOMEM); 1418 rman_set_bustag(r, tag); 1419 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] + 1420 rman_get_start(r)); 1421 break; 1422 case SYS_RES_IOPORT: 1423 rman_set_bustag(r, sc->sc_pci_iot); 1424 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] + 1425 rman_get_start(r)); 1426 break; 1427 } 1428 return (rman_activate_resource(r)); 1429} 1430 1431static int 1432schizo_adjust_resource(device_t bus, device_t child, int type, 1433 struct resource *r, u_long start, u_long end) 1434{ 1435 struct schizo_softc *sc; 1436 struct rman *rm; 1437 1438 sc = device_get_softc(bus); 1439 switch (type) { 1440 case SYS_RES_IRQ: 1441 return (bus_generic_adjust_resource(bus, child, type, r, 1442 start, end)); 1443 case SYS_RES_MEMORY: 1444 rm = &sc->sc_pci_mem_rman; 1445 break; 1446 case SYS_RES_IOPORT: 1447 rm = &sc->sc_pci_io_rman; 1448 break; 1449 default: 1450 return (EINVAL); 1451 } 1452 if (rman_is_region_manager(r, rm) == 0) 1453 return (EINVAL); 1454 return (rman_adjust_resource(r, start, end)); 1455} 1456 1457static bus_dma_tag_t 1458schizo_get_dma_tag(device_t bus, device_t child __unused) 1459{ 1460 struct schizo_softc *sc; 1461 1462 sc = device_get_softc(bus); 1463 return (sc->sc_pci_dmat); 1464} 1465 1466static phandle_t 1467schizo_get_node(device_t bus, device_t child __unused) 1468{ 1469 struct schizo_softc *sc; 1470 1471 sc = device_get_softc(bus); 1472 /* We only have one child, the PCI bus, which needs our own node. */ 1473 return (sc->sc_node); 1474} 1475 1476static void 1477schizo_setup_device(device_t bus, device_t child) 1478{ 1479 struct schizo_softc *sc; 1480 uint64_t reg; 1481 int capreg; 1482 1483 sc = device_get_softc(bus); 1484 /* 1485 * Disable bus parking in order to work around a bus hang caused by 1486 * Casinni/Skyhawk combinations. 1487 */ 1488 if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1489 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1490 STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1491 1492 if (sc->sc_mode == SCHIZO_MODE_XMS) { 1493 /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1494 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1495 (pci_read_config(child, PCIR_HDRTYPE, 1) & 1496 PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1497 pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1498 pci_write_config(child, capreg + PCIXR_COMMAND, 1499 pci_read_config(child, capreg + PCIXR_COMMAND, 1500 2) & 0x7c, 2); 1501 /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1502 if (sc->sc_mrev >= 4) { 1503 reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1504 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1505 if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1506 XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1507 SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1508 } 1509 } 1510} 1511 1512static u_int 1513schizo_get_timecount(struct timecounter *tc) 1514{ 1515 struct schizo_softc *sc; 1516 1517 sc = tc->tc_priv; 1518 return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1519 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1520 STX_CTRL_PERF_CNT_CNT0_SHIFT); 1521} 1522