pcib_private.h revision 280970
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: stable/10/sys/dev/pci/pcib_private.h 280970 2015-04-01 21:48:54Z jhb $ 31 */ 32 33#ifndef __PCIB_PRIVATE_H__ 34#define __PCIB_PRIVATE_H__ 35 36#ifdef NEW_PCIB 37/* 38 * Data structure and routines that Host to PCI bridge drivers can use 39 * to restrict allocations for child devices to ranges decoded by the 40 * bridge. 41 */ 42struct pcib_host_resources { 43 device_t hr_pcib; 44 struct resource_list hr_rl; 45}; 46 47int pcib_host_res_init(device_t pcib, 48 struct pcib_host_resources *hr); 49int pcib_host_res_free(device_t pcib, 50 struct pcib_host_resources *hr); 51int pcib_host_res_decodes(struct pcib_host_resources *hr, int type, 52 u_long start, u_long end, u_int flags); 53struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr, 54 device_t dev, int type, int *rid, u_long start, u_long end, 55 u_long count, u_int flags); 56int pcib_host_res_adjust(struct pcib_host_resources *hr, 57 device_t dev, int type, struct resource *r, u_long start, 58 u_long end); 59#endif 60 61/* 62 * Export portions of generic PCI:PCI bridge support so that it can be 63 * used by subclasses. 64 */ 65DECLARE_CLASS(pcib_driver); 66 67#ifdef NEW_PCIB 68#define WIN_IO 0x1 69#define WIN_MEM 0x2 70#define WIN_PMEM 0x4 71 72struct pcib_window { 73 pci_addr_t base; /* base address */ 74 pci_addr_t limit; /* topmost address */ 75 struct rman rman; 76 struct resource **res; 77 int count; /* size of 'res' array */ 78 int reg; /* resource id from parent */ 79 int valid; 80 int mask; /* WIN_* bitmask of this window */ 81 int step; /* log_2 of window granularity */ 82 const char *name; 83}; 84#endif 85 86struct pcib_secbus { 87 u_int sec; 88 u_int sub; 89#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 90 device_t dev; 91 struct rman rman; 92 struct resource *res; 93 const char *name; 94 int sub_reg; 95#endif 96}; 97 98/* 99 * Bridge-specific data. 100 */ 101struct pcib_softc 102{ 103 device_t dev; 104 uint32_t flags; /* flags */ 105#define PCIB_SUBTRACTIVE 0x1 106#define PCIB_DISABLE_MSI 0x2 107#define PCIB_DISABLE_MSIX 0x4 108#define PCIB_ENABLE_ARI 0x8 109 uint16_t command; /* command register */ 110 u_int domain; /* domain number */ 111 u_int pribus; /* primary bus number */ 112 struct pcib_secbus bus; /* secondary bus numbers */ 113#ifdef NEW_PCIB 114 struct pcib_window io; /* I/O port window */ 115 struct pcib_window mem; /* memory window */ 116 struct pcib_window pmem; /* prefetchable memory window */ 117#else 118 pci_addr_t pmembase; /* base address of prefetchable memory */ 119 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 120 pci_addr_t membase; /* base address of memory window */ 121 pci_addr_t memlimit; /* topmost address of memory window */ 122 uint32_t iobase; /* base address of port window */ 123 uint32_t iolimit; /* topmost address of port window */ 124#endif 125 uint16_t secstat; /* secondary bus status register */ 126 uint16_t bridgectl; /* bridge control register */ 127 uint8_t seclat; /* secondary bus latency timer */ 128}; 129 130#define PCIB_SUPPORTED_ARI_VER 1 131 132typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width); 133 134int host_pcib_get_busno(pci_read_config_fn read_config, int bus, 135 int slot, int func, uint8_t *busnum); 136#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 137struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid, 138 u_long start, u_long end, u_long count, u_int flags); 139int pci_domain_adjust_bus(int domain, device_t dev, 140 struct resource *r, u_long start, u_long end); 141int pci_domain_release_bus(int domain, device_t dev, int rid, 142 struct resource *r); 143struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, 144 int *rid, u_long start, u_long end, u_long count, 145 u_int flags); 146void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, 147 int min_count); 148#endif 149int pcib_attach(device_t dev); 150void pcib_attach_common(device_t dev); 151#ifdef NEW_PCIB 152const char *pcib_child_name(device_t child); 153#endif 154int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 155int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 156struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 157 u_long start, u_long end, u_long count, u_int flags); 158#ifdef NEW_PCIB 159int pcib_adjust_resource(device_t bus, device_t child, int type, 160 struct resource *r, u_long start, u_long end); 161int pcib_release_resource(device_t dev, device_t child, int type, int rid, 162 struct resource *r); 163#endif 164int pcib_maxslots(device_t dev); 165int pcib_maxfuncs(device_t dev); 166int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 167int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs); 168int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs); 169int pcib_alloc_msix(device_t pcib, device_t dev, int *irq); 170int pcib_release_msix(device_t pcib, device_t dev, int irq); 171int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data); 172uint16_t pcib_get_rid(device_t pcib, device_t dev); 173 174#endif 175