trap_subr64.S revision 266020
1/* $FreeBSD: stable/10/sys/powerpc/aim/trap_subr64.S 266020 2014-05-14 14:17:51Z ian $ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45 46/* 47 * Restore SRs for a pmap 48 * 49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache 50 */ 51 52/* 53 * User SRs are loaded through a pointer to the current pmap. 54 */ 55restore_usersrs: 56 GET_CPUINFO(%r28) 57 ld %r28,PC_USERSLB(%r28) 58 li %r29, 0 /* Set the counter to zero */ 59 60 slbia 61 slbmfee %r31,%r29 62 clrrdi %r31,%r31,28 63 slbie %r31 641: ld %r31, 0(%r28) /* Load SLB entry pointer */ 65 cmpli 0, %r31, 0 /* If NULL, stop */ 66 beqlr 67 68 ld %r30, 0(%r31) /* Load SLBV */ 69 ld %r31, 8(%r31) /* Load SLBE */ 70 or %r31, %r31, %r29 /* Set SLBE slot */ 71 slbmte %r30, %r31 /* Install SLB entry */ 72 73 addi %r28, %r28, 8 /* Advance pointer */ 74 addi %r29, %r29, 1 75 b 1b /* Repeat */ 76 77/* 78 * Kernel SRs are loaded directly from the PCPU fields 79 */ 80restore_kernsrs: 81 GET_CPUINFO(%r28) 82 addi %r28,%r28,PC_KERNSLB 83 li %r29, 0 /* Set the counter to zero */ 84 85 slbia 86 slbmfee %r31,%r29 87 clrrdi %r31,%r31,28 88 slbie %r31 891: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */ 90 beq- 2f 91 92 ld %r31, 8(%r28) /* Load SLBE */ 93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */ 94 beqlr 95 ld %r30, 0(%r28) /* Load SLBV */ 96 slbmte %r30, %r31 /* Install SLB entry */ 97 982: addi %r28, %r28, 16 /* Advance pointer */ 99 addi %r29, %r29, 1 100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */ 101 blt 1b 102 blr 103 104/* 105 * FRAME_SETUP assumes: 106 * SPRG1 SP (1) 107 * SPRG3 trap type 108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 109 * r28 LR 110 * r29 CR 111 * r30 scratch 112 * r31 scratch 113 * r1 kernel stack 114 * SRR0/1 as at start of trap 115 * 116 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse 117 * in any real-mode fault handler, including those handling double faults. 118 */ 119#define FRAME_SETUP(savearea) \ 120/* Have to enable translation to allow access of kernel stack: */ \ 121 GET_CPUINFO(%r31); \ 122 mfsrr0 %r30; \ 123 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 124 mfsrr1 %r30; \ 125 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 126 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \ 127 mfmsr %r30; \ 128 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 129 mtmsr %r30; /* stack can now be accessed */ \ 130 isync; \ 131 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \ 132 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \ 133 std %r31,FRAME_1+48(%r1); /* save SP " " */ \ 134 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \ 135 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \ 136 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \ 137 GET_CPUINFO(%r2); \ 138 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \ 139 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 140 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 141 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 142 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 143 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \ 144 std %r4, FRAME_4+48(%r1); \ 145 std %r5, FRAME_5+48(%r1); \ 146 std %r6, FRAME_6+48(%r1); \ 147 std %r7, FRAME_7+48(%r1); \ 148 std %r8, FRAME_8+48(%r1); \ 149 std %r9, FRAME_9+48(%r1); \ 150 std %r10, FRAME_10+48(%r1); \ 151 std %r11, FRAME_11+48(%r1); \ 152 std %r12, FRAME_12+48(%r1); \ 153 std %r13, FRAME_13+48(%r1); \ 154 std %r14, FRAME_14+48(%r1); \ 155 std %r15, FRAME_15+48(%r1); \ 156 std %r16, FRAME_16+48(%r1); \ 157 std %r17, FRAME_17+48(%r1); \ 158 std %r18, FRAME_18+48(%r1); \ 159 std %r19, FRAME_19+48(%r1); \ 160 std %r20, FRAME_20+48(%r1); \ 161 std %r21, FRAME_21+48(%r1); \ 162 std %r22, FRAME_22+48(%r1); \ 163 std %r23, FRAME_23+48(%r1); \ 164 std %r24, FRAME_24+48(%r1); \ 165 std %r25, FRAME_25+48(%r1); \ 166 std %r26, FRAME_26+48(%r1); \ 167 std %r27, FRAME_27+48(%r1); \ 168 std %r28, FRAME_28+48(%r1); \ 169 std %r29, FRAME_29+48(%r1); \ 170 std %r30, FRAME_30+48(%r1); \ 171 std %r31, FRAME_31+48(%r1); \ 172 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 173 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 174 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 175 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 176 mfxer %r3; \ 177 mfctr %r4; \ 178 mfsprg3 %r5; \ 179 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \ 180 std %r4, FRAME_CTR+48(1); \ 181 std %r5, FRAME_EXC+48(1); \ 182 std %r28,FRAME_AIM_DAR+48(1); \ 183 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \ 184 std %r30,FRAME_SRR0+48(1); \ 185 std %r31,FRAME_SRR1+48(1); \ 186 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */ 187 188#define FRAME_LEAVE(savearea) \ 189/* Disable exceptions: */ \ 190 mfmsr %r2; \ 191 andi. %r2,%r2,~PSL_EE@l; \ 192 mtmsr %r2; \ 193 isync; \ 194/* Now restore regs: */ \ 195 ld %r2,FRAME_SRR0+48(%r1); \ 196 ld %r3,FRAME_SRR1+48(%r1); \ 197 ld %r4,FRAME_CTR+48(%r1); \ 198 ld %r5,FRAME_XER+48(%r1); \ 199 ld %r6,FRAME_LR+48(%r1); \ 200 GET_CPUINFO(%r7); \ 201 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 202 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 203 ld %r7,FRAME_CR+48(%r1); \ 204 mtctr %r4; \ 205 mtxer %r5; \ 206 mtlr %r6; \ 207 mtsprg2 %r7; /* save cr */ \ 208 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \ 209 ld %r30,FRAME_30+48(%r1); \ 210 ld %r29,FRAME_29+48(%r1); \ 211 ld %r28,FRAME_28+48(%r1); \ 212 ld %r27,FRAME_27+48(%r1); \ 213 ld %r26,FRAME_26+48(%r1); \ 214 ld %r25,FRAME_25+48(%r1); \ 215 ld %r24,FRAME_24+48(%r1); \ 216 ld %r23,FRAME_23+48(%r1); \ 217 ld %r22,FRAME_22+48(%r1); \ 218 ld %r21,FRAME_21+48(%r1); \ 219 ld %r20,FRAME_20+48(%r1); \ 220 ld %r19,FRAME_19+48(%r1); \ 221 ld %r18,FRAME_18+48(%r1); \ 222 ld %r17,FRAME_17+48(%r1); \ 223 ld %r16,FRAME_16+48(%r1); \ 224 ld %r15,FRAME_15+48(%r1); \ 225 ld %r14,FRAME_14+48(%r1); \ 226 ld %r13,FRAME_13+48(%r1); \ 227 ld %r12,FRAME_12+48(%r1); \ 228 ld %r11,FRAME_11+48(%r1); \ 229 ld %r10,FRAME_10+48(%r1); \ 230 ld %r9, FRAME_9+48(%r1); \ 231 ld %r8, FRAME_8+48(%r1); \ 232 ld %r7, FRAME_7+48(%r1); \ 233 ld %r6, FRAME_6+48(%r1); \ 234 ld %r5, FRAME_5+48(%r1); \ 235 ld %r4, FRAME_4+48(%r1); \ 236 ld %r3, FRAME_3+48(%r1); \ 237 ld %r2, FRAME_2+48(%r1); \ 238 ld %r0, FRAME_0+48(%r1); \ 239 ld %r1, FRAME_1+48(%r1); \ 240/* Can't touch %r1 from here on */ \ 241 mtsprg3 %r3; /* save r3 */ \ 242/* Disable translation, machine check and recoverability: */ \ 243 mfmsr %r3; \ 244 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 245 mtmsr %r3; \ 246 isync; \ 247/* Decide whether we return to user mode: */ \ 248 GET_CPUINFO(%r3); \ 249 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \ 250 mtcr %r3; \ 251 bf 17,1f; /* branch if PSL_PR is false */ \ 252/* Restore user SRs */ \ 253 GET_CPUINFO(%r3); \ 254 std %r27,(savearea+CPUSAVE_R27)(%r3); \ 255 std %r28,(savearea+CPUSAVE_R28)(%r3); \ 256 std %r29,(savearea+CPUSAVE_R29)(%r3); \ 257 std %r30,(savearea+CPUSAVE_R30)(%r3); \ 258 std %r31,(savearea+CPUSAVE_R31)(%r3); \ 259 mflr %r27; /* preserve LR */ \ 260 bl restore_usersrs; /* uses r28-r31 */ \ 261 mtlr %r27; \ 262 ld %r31,(savearea+CPUSAVE_R31)(%r3); \ 263 ld %r30,(savearea+CPUSAVE_R30)(%r3); \ 264 ld %r29,(savearea+CPUSAVE_R29)(%r3); \ 265 ld %r28,(savearea+CPUSAVE_R28)(%r3); \ 266 ld %r27,(savearea+CPUSAVE_R27)(%r3); \ 2671: mfsprg2 %r3; /* restore cr */ \ 268 mtcr %r3; \ 269 GET_CPUINFO(%r3); \ 270 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \ 271 mtsrr0 %r3; \ 272 GET_CPUINFO(%r3); \ 273 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \ 274 mtsrr1 %r3; \ 275 mfsprg3 %r3 /* restore r3 */ 276 277#ifdef KDTRACE_HOOKS 278 .data 279 .globl dtrace_invop_calltrap_addr 280 .align 8 281 .type dtrace_invop_calltrap_addr, @object 282 .size dtrace_invop_calltrap_addr, 8 283dtrace_invop_calltrap_addr: 284 .word 0 285 .word 0 286 287 .text 288#endif 289 290/* 291 * Processor reset exception handler. These are typically 292 * the first instructions the processor executes after a 293 * software reset. We do this in two bits so that we are 294 * not still hanging around in the trap handling region 295 * once the MMU is turned on. 296 */ 297 .globl CNAME(rstcode), CNAME(rstsize) 298CNAME(rstcode): 299 /* Explicitly set MSR[SF] */ 300 mfmsr %r9 301 li %r8,1 302 insrdi %r9,%r8,1,0 303 mtmsrd %r9 304 isync 305 306 ba cpu_reset 307CNAME(rstsize) = . - CNAME(rstcode) 308 309cpu_reset: 310 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 311 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 312 313 lis %r3,tocbase@ha 314 ld %r2,tocbase@l(%r3) 315 lis %r3,1@l 316 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */ 317 nop 318 lis %r3,1@l 319 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */ 320 nop 321 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */ 322 nop 323 mr %r1,%r3 /* Use new stack */ 324 bl CNAME(cpudep_ap_setup) 325 nop 326 GET_CPUINFO(%r5) 327 ld %r3,(PC_RESTORE)(%r5) 328 cmpldi %cr0,%r3,0 329 beq %cr0,2f 330 nop 331 li %r4,1 332 b CNAME(longjmp) 333 nop 3342: 335#ifdef SMP 336 bl CNAME(machdep_ap_bootstrap) /* And away! */ 337 nop 338#endif 339 340 /* Should not be reached */ 3419: 342 b 9b 343 344/* 345 * This code gets copied to all the trap vectors 346 * (except ISI/DSI, ALI, and the interrupts) 347 */ 348 349 .globl CNAME(trapcode),CNAME(trapsize) 350CNAME(trapcode): 351 mtsprg1 %r1 /* save SP */ 352 mflr %r1 /* Save the old LR in r1 */ 353 mtsprg2 %r1 /* And then in SPRG2 */ 354 li %r1, 0xA0 /* How to get the vector from LR */ 355 bla generictrap /* LR & SPRG3 is exception # */ 356CNAME(trapsize) = .-CNAME(trapcode) 357 358/* 359 * For SLB misses: do special things for the kernel 360 * 361 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is 362 * the only time this can be called. 363 */ 364 .globl CNAME(slbtrap),CNAME(slbtrapsize) 365CNAME(slbtrap): 366 mtsprg1 %r1 /* save SP */ 367 GET_CPUINFO(%r1) 368 std %r2,(PC_SLBSAVE+16)(%r1) 369 mfcr %r2 /* save CR */ 370 std %r2,(PC_SLBSAVE+104)(%r1) 371 mfsrr1 %r2 /* test kernel mode */ 372 mtcr %r2 373 bf 17,1f /* branch if PSL_PR is false */ 374 /* User mode */ 375 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 376 mtcr %r2 377 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */ 378 mflr %r1 /* Save the old LR in r1 */ 379 mtsprg2 %r1 /* And then in SPRG2 */ 380 li %r1, 0x80 /* How to get the vector from LR */ 381 bla generictrap /* LR & SPRG3 is exception # */ 3821: mflr %r2 /* Save the old LR in r2 */ 383 bla kern_slbtrap 384CNAME(slbtrapsize) = .-CNAME(slbtrap) 385 386kern_slbtrap: 387 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */ 388 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */ 389 390 /* Check if this needs to be handled as a regular trap (userseg miss) */ 391 mflr %r2 392 andi. %r2,%r2,0xff80 393 cmpwi %r2,0x380 394 bne 1f 395 mfdar %r2 396 b 2f 3971: mfsrr0 %r2 3982: /* r2 now contains the fault address */ 399 lis %r3,SEGMENT_MASK@highesta 400 ori %r3,%r3,SEGMENT_MASK@highera 401 sldi %r3,%r3,32 402 oris %r3,%r3,SEGMENT_MASK@ha 403 ori %r3,%r3,SEGMENT_MASK@l 404 and %r2,%r2,%r3 /* R2 = segment base address */ 405 lis %r3,USER_ADDR@highesta 406 ori %r3,%r3,USER_ADDR@highera 407 sldi %r3,%r3,32 408 oris %r3,%r3,USER_ADDR@ha 409 ori %r3,%r3,USER_ADDR@l 410 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */ 411 bne 3f 412 413 /* User seg miss, handle as a regular trap */ 414 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 415 mtcr %r2 416 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */ 417 ld %r3,(PC_SLBSAVE+24)(%r1) 418 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */ 419 mtsprg2 %r1 /* And then in SPRG2 */ 420 li %r1, 0x80 /* How to get the vector from LR */ 421 b generictrap /* Retain old LR using b */ 422 4233: /* Real kernel SLB miss */ 424 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */ 425 mfsprg1 %r2 /* Old R1 */ 426 std %r2,(PC_SLBSAVE+8)(%r1) 427 /* R2,R3 already saved */ 428 std %r4,(PC_SLBSAVE+32)(%r1) 429 std %r5,(PC_SLBSAVE+40)(%r1) 430 std %r6,(PC_SLBSAVE+48)(%r1) 431 std %r7,(PC_SLBSAVE+56)(%r1) 432 std %r8,(PC_SLBSAVE+64)(%r1) 433 std %r9,(PC_SLBSAVE+72)(%r1) 434 std %r10,(PC_SLBSAVE+80)(%r1) 435 std %r11,(PC_SLBSAVE+88)(%r1) 436 std %r12,(PC_SLBSAVE+96)(%r1) 437 /* CR already saved */ 438 mfxer %r2 /* save XER */ 439 std %r2,(PC_SLBSAVE+112)(%r1) 440 mflr %r2 /* save LR (SP already saved) */ 441 std %r2,(PC_SLBSAVE+120)(%r1) 442 mfctr %r2 /* save CTR */ 443 std %r2,(PC_SLBSAVE+128)(%r1) 444 445 /* Call handler */ 446 addi %r1,%r1,PC_SLBSTACK-48+1024 447 li %r2,~15 448 and %r1,%r1,%r2 449 lis %r3,tocbase@ha 450 ld %r2,tocbase@l(%r3) 451 mflr %r3 452 andi. %r3,%r3,0xff80 453 mfdar %r4 454 mfsrr0 %r5 455 bl handle_kernel_slb_spill 456 nop 457 458 /* Save r28-31, restore r4-r12 */ 459 GET_CPUINFO(%r1) 460 ld %r4,(PC_SLBSAVE+32)(%r1) 461 ld %r5,(PC_SLBSAVE+40)(%r1) 462 ld %r6,(PC_SLBSAVE+48)(%r1) 463 ld %r7,(PC_SLBSAVE+56)(%r1) 464 ld %r8,(PC_SLBSAVE+64)(%r1) 465 ld %r9,(PC_SLBSAVE+72)(%r1) 466 ld %r10,(PC_SLBSAVE+80)(%r1) 467 ld %r11,(PC_SLBSAVE+88)(%r1) 468 ld %r12,(PC_SLBSAVE+96)(%r1) 469 std %r28,(PC_SLBSAVE+64)(%r1) 470 std %r29,(PC_SLBSAVE+72)(%r1) 471 std %r30,(PC_SLBSAVE+80)(%r1) 472 std %r31,(PC_SLBSAVE+88)(%r1) 473 474 /* Restore kernel mapping */ 475 bl restore_kernsrs 476 477 /* Restore remaining registers */ 478 ld %r28,(PC_SLBSAVE+64)(%r1) 479 ld %r29,(PC_SLBSAVE+72)(%r1) 480 ld %r30,(PC_SLBSAVE+80)(%r1) 481 ld %r31,(PC_SLBSAVE+88)(%r1) 482 483 ld %r2,(PC_SLBSAVE+104)(%r1) 484 mtcr %r2 485 ld %r2,(PC_SLBSAVE+112)(%r1) 486 mtxer %r2 487 ld %r2,(PC_SLBSAVE+120)(%r1) 488 mtlr %r2 489 ld %r2,(PC_SLBSAVE+128)(%r1) 490 mtctr %r2 491 ld %r2,(PC_SLBSAVE+136)(%r1) 492 mtlr %r2 493 494 /* Restore r0-r3 */ 495 ld %r0,(PC_SLBSAVE+0)(%r1) 496 ld %r2,(PC_SLBSAVE+16)(%r1) 497 ld %r3,(PC_SLBSAVE+24)(%r1) 498 mfsprg1 %r1 499 500 /* Back to whatever we were doing */ 501 rfid 502 503/* 504 * For ALI: has to save DSISR and DAR 505 */ 506 .globl CNAME(alitrap),CNAME(alisize) 507CNAME(alitrap): 508 mtsprg1 %r1 /* save SP */ 509 GET_CPUINFO(%r1) 510 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 511 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 512 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 513 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 514 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 515 mfdar %r30 516 mfdsisr %r31 517 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 518 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 519 mfsprg1 %r1 /* restore SP, in case of branch */ 520 mflr %r28 /* save LR */ 521 mfcr %r29 /* save CR */ 522 523 /* Put our exception vector in SPRG3 */ 524 li %r31, EXC_ALI 525 mtsprg3 %r31 526 527 /* Test whether we already had PR set */ 528 mfsrr1 %r31 529 mtcr %r31 530 bla s_trap 531CNAME(alisize) = .-CNAME(alitrap) 532 533/* 534 * Similar to the above for DSI 535 * Has to handle BAT spills 536 * and standard pagetable spills 537 */ 538 .globl CNAME(dsitrap),CNAME(dsisize) 539CNAME(dsitrap): 540 mtsprg1 %r1 /* save SP */ 541 GET_CPUINFO(%r1) 542 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 543 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) 544 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 545 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 546 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 547 mfsprg1 %r1 /* restore SP */ 548 mfcr %r29 /* save CR */ 549 mfxer %r30 /* save XER */ 550 mtsprg2 %r30 /* in SPRG2 */ 551 mfsrr1 %r31 /* test kernel mode */ 552 mtcr %r31 553 mflr %r28 /* save LR (SP already saved) */ 554 bla disitrap 555CNAME(dsisize) = .-CNAME(dsitrap) 556 557/* 558 * Preamble code for DSI/ISI traps 559 */ 560disitrap: 561 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 562 mflr %r1 563 andi. %r1,%r1,0xff00 564 mtsprg3 %r1 565 566 GET_CPUINFO(%r1) 567 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) 568 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 569 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 570 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 571 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 572 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 573 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 574 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 575 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 576 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 577 mfdar %r30 578 mfdsisr %r31 579 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 580 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 581 582#ifdef KDB 583 /* Try to detect a kernel stack overflow */ 584 mfsrr1 %r31 585 mtcr %r31 586 bt 17,realtrap /* branch is user mode */ 587 mfsprg1 %r31 /* get old SP */ 588 clrrdi %r31,%r31,11 /* Round SP down to nearest page */ 589 sub. %r30,%r31,%r30 /* SP - DAR */ 590 bge 1f 591 neg %r30,%r30 /* modulo value */ 5921: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */ 593 bge %cr0,realtrap /* no, too far away. */ 594 595 /* Now convert this DSI into a DDB trap. */ 596 GET_CPUINFO(%r1) 597 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 598 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 599 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 600 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 601 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */ 602 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */ 603 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 604 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 605 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 606 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 607 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 608 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 609 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 610 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 611 b dbtrap 612#endif 613 614 /* XXX need stack probe here */ 615realtrap: 616/* Test whether we already had PR set */ 617 mfsrr1 %r1 618 mtcr %r1 619 mfsprg1 %r1 /* restore SP (might have been 620 overwritten) */ 621 bf 17,k_trap /* branch if PSL_PR is false */ 622 GET_CPUINFO(%r1) 623 ld %r1,PC_CURPCB(%r1) 624 mr %r27,%r28 /* Save LR, r29 */ 625 mtsprg2 %r29 626 bl restore_kernsrs /* enable kernel mapping */ 627 mfsprg2 %r29 628 mr %r28,%r27 629 ba s_trap 630 631/* 632 * generictrap does some standard setup for trap handling to minimize 633 * the code that need be installed in the actual vectors. It expects 634 * the following conditions. 635 * 636 * R1 - Trap vector = LR & (0xff00 | R1) 637 * SPRG1 - Original R1 contents 638 * SPRG2 - Original LR 639 */ 640 641generictrap: 642 /* Save R1 for computing the exception vector */ 643 mtsprg3 %r1 644 645 /* Save interesting registers */ 646 GET_CPUINFO(%r1) 647 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 648 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 649 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 650 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 651 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 652 mfdar %r30 653 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 654 mfsprg1 %r1 /* restore SP, in case of branch */ 655 mfsprg2 %r28 /* save LR */ 656 mfcr %r29 /* save CR */ 657 658 /* Compute the exception vector from the link register */ 659 mfsprg3 %r31 660 ori %r31,%r31,0xff00 661 mflr %r30 662 and %r30,%r30,%r31 663 mtsprg3 %r30 664 665 /* Test whether we already had PR set */ 666 mfsrr1 %r31 667 mtcr %r31 668 669s_trap: 670 bf 17,k_trap /* branch if PSL_PR is false */ 671 GET_CPUINFO(%r1) 672u_trap: 673 ld %r1,PC_CURPCB(%r1) 674 mr %r27,%r28 /* Save LR, r29 */ 675 mtsprg2 %r29 676 bl restore_kernsrs /* enable kernel mapping */ 677 mfsprg2 %r29 678 mr %r28,%r27 679 680/* 681 * Now the common trap catching code. 682 */ 683k_trap: 684 FRAME_SETUP(PC_TEMPSAVE) 685/* Call C interrupt dispatcher: */ 686trapagain: 687 lis %r3,tocbase@ha 688 ld %r2,tocbase@l(%r3) 689 addi %r3,%r1,48 690 bl CNAME(powerpc_interrupt) 691 nop 692 693 .globl CNAME(trapexit) /* backtrace code sentinel */ 694CNAME(trapexit): 695/* Disable interrupts: */ 696 mfmsr %r3 697 andi. %r3,%r3,~PSL_EE@l 698 mtmsr %r3 699 isync 700/* Test AST pending: */ 701 ld %r5,FRAME_SRR1+48(%r1) 702 mtcr %r5 703 bf 17,1f /* branch if PSL_PR is false */ 704 705 GET_CPUINFO(%r3) /* get per-CPU pointer */ 706 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */ 707 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 708 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 709 and. %r4,%r4,%r5 710 beq 1f 711 mfmsr %r3 /* re-enable interrupts */ 712 ori %r3,%r3,PSL_EE@l 713 mtmsr %r3 714 isync 715 lis %r3,tocbase@ha 716 ld %r2,tocbase@l(%r3) 717 addi %r3,%r1,48 718 bl CNAME(ast) 719 nop 720 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 721CNAME(asttrapexit): 722 b trapexit /* test ast ret value ? */ 7231: 724 FRAME_LEAVE(PC_TEMPSAVE) 725 rfid 726 727#if defined(KDB) 728/* 729 * Deliberate entry to dbtrap 730 */ 731ASENTRY_NOPROF(breakpoint) 732 mtsprg1 %r1 733 mfmsr %r3 734 mtsrr1 %r3 735 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 736 mtmsr %r3 /* disable interrupts */ 737 isync 738 GET_CPUINFO(%r3) 739 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3) 740 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 741 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 742 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 743 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 744 mflr %r28 745 li %r29,EXC_BPT 746 mtlr %r29 747 mfcr %r29 748 mtsrr0 %r28 749 750/* 751 * Now the kdb trap catching code. 752 */ 753dbtrap: 754 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 755 mflr %r1 756 andi. %r1,%r1,0xff00 757 mtsprg3 %r1 758 759 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 760 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 761 762 FRAME_SETUP(PC_DBSAVE) 763/* Call C trap code: */ 764 lis %r3,tocbase@ha 765 ld %r2,tocbase@l(%r3) 766 addi %r3,%r1,48 767 bl CNAME(db_trap_glue) 768 nop 769 or. %r3,%r3,%r3 770 bne dbleave 771/* This wasn't for KDB, so switch to real trap: */ 772 ld %r3,FRAME_EXC+48(%r1) /* save exception */ 773 GET_CPUINFO(%r4) 774 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 775 FRAME_LEAVE(PC_DBSAVE) 776 mtsprg1 %r1 /* prepare for entrance to realtrap */ 777 GET_CPUINFO(%r1) 778 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 779 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 780 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 781 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 782 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 783 mflr %r28 784 mfcr %r29 785 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 786 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 787 mfsprg1 %r1 788 b realtrap 789dbleave: 790 FRAME_LEAVE(PC_DBSAVE) 791 rfid 792 793/* 794 * In case of KDB we want a separate trap catcher for it 795 */ 796 .globl CNAME(dblow),CNAME(dbsize) 797CNAME(dblow): 798 mtsprg1 %r1 /* save SP */ 799 mtsprg2 %r29 /* save r29 */ 800 mfcr %r29 /* save CR in r29 */ 801 mfsrr1 %r1 802 mtcr %r1 803 bf 17,2f /* branch if privileged */ 804 8051: 806 /* Unprivileged case */ 807 mtcr %r29 /* put the condition register back */ 808 mfsprg2 %r29 /* ... and r29 */ 809 mflr %r1 /* save LR */ 810 mtsprg2 %r1 /* And then in SPRG2 */ 811 li %r1, 0 /* How to get the vector from LR */ 812 813 bla generictrap /* and we look like a generic trap */ 8142: 815#ifdef KDTRACE_HOOKS 816 /* Privileged, so drop to KDB */ 817 mfsrr0 %r1 818 mtsprg3 %r3 819 lwz %r1,0(%r1) 820 /* Check if it's a DTrace trap. */ 821 li %r3,0x0808 822 addis %r3,%r3,0x7c81 823 cmplw %cr0,%r3,%r1 824 mfsprg3 %r3 825 beq %cr0,1b 826#endif 827 GET_CPUINFO(%r1) 828 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ 829 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 830 mfsprg2 %r28 /* r29 holds cr... */ 831 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 832 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 833 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 834 mflr %r28 /* save LR */ 835 bla dbtrap 836CNAME(dbsize) = .-CNAME(dblow) 837#endif /* KDB */ 838