#
268972 |
|
22-Jul-2014 |
jhb |
MFC 266125: Implement a PCI interrupt router to route PCI legacy INTx interrupts to the legacy 8259A PICs.
|
#
268887 |
|
19-Jul-2014 |
jhb |
MFC 261904,261905,262143,262184,264921,265211,267169,267292,267294: Various PCI fixes: - Allow PCI devices to be configured on all valid bus numbers from 0 to 255. - Tweak the handling of PCI capabilities in emulated devices to remove the non-standard zero capability list terminator. - Add a check to validate that memory BARs of passthru devices are 4KB aligned. - Respect and track the enable bit in the PCI configuration address word. - Handle quad-word access to 32-bit register pairs.
|
#
267393 |
|
12-Jun-2014 |
jhb |
MFC 260239,261268,265058: Expand the support for PCI INTx interrupts including providing interrupt routing information for INTx interrupts to I/O APIC pins and enabling INTx interrupts in the virtio and AHCI backends.
|
#
262350 |
|
22-Feb-2014 |
jhb |
MFC 258859,259081,259085,259205,259213,259275,259482,259537,259702,259779: Several changes to the local APIC support in bhyve: - Rename 'vm_interrupt_hostcpu()' to 'vcpu_notify_event()'. - If a vcpu disables its local apic and then executes a 'HLT' then spin down the vcpu and destroy its thread context. Also modify the 'HLT' processing to ignore pending interrupts in the IRR if interrupts have been disabled by the guest. The interrupt cannot be injected into the guest in any case so resuming it is futile. - Use callout(9) to drive the vlapic timer instead of clocking it on each VM exit. - When the guest is bringing up the APs in the x2APIC mode a write to the ICR register will now trigger a return to userspace with an exitcode of VM_EXITCODE_SPINUP_AP. - Change the vlapic timer lock to be a spinlock because the vlapic can be accessed from within a critical section (vm run loop) when guest is using x2apic mode. - Fix the vlapic version register. - Add a command to bhyvectl to inject an NMI on a specific vcpu. - Add an API to deliver message signalled interrupts to vcpus. This allows callers to treat the MSI 'addr' and 'data' fields as opaque and also lets bhyve implement multiple destination modes: physical, flat and clustered. - Rename the ambiguously named 'vm_setup_msi()' and 'vm_setup_msix()' to 'vm_setup_pptdev_msi()' and 'vm_setup_pptdev_msix()' respectively. - Consolidate the virtual apic initialization in a single function: vlapic_reset() - Add a generic routine to trigger an LVT interrupt that supports both fixed and NMI delivery modes. - Add an ioctl and bhyvectl command to trigger local interrupts inside a guest. In particular, a global NMI similar to that raised by SERR# or PERR# can be simulated by asserting LINT1 on all vCPUs. - Extend the LVT table in the vCPU local APIC to support CMCI. - Flesh out the local APIC error reporting a bit to cache errors and report them via ESR when ESR is written to. Add support for asserting the error LVT when an error occurs. Raise illegal vector errors when attempting to signal an invalid vector for an interrupt or when sending an IPI. - Export table entries in the MADT and MP Table advertising the stock x86 config of LINT0 set to ExtInt and LINT1 wired to NMI.
|
#
261090 |
|
23-Jan-2014 |
jhb |
MFC 259826,259997,259998: Support soft power-off via the ACPI S5 state for bhyve guests and wire up a virtual power button to SIGTERM: - Implement the PM1_EVT and PM1_CTL registers required by ACPI. - Emulate the Reset Control register at I/O port 0xcf9. - Advertise an _S5 package. - Implement an SMI_CMD register with commands to enable and disable ACPI. Currently the only change when ACPI is enabled is to enable the virtual power button via SIGTERM. - Implement a fixed-feature power button when ACPI is enabled by asserting PWRBTN_STS in PM1_EVT when SIGTERM is received. - Add support for EVFILT_SIGNAL events to mevent. - Implement support for the ACPI system command interrupt (SCI) and assert it when needed based on the values in PM1_EVT. Mark the SCI as active-low and level triggered in the MADT and MP Table.
|
#
261088 |
|
23-Jan-2014 |
jhb |
MFC 257422,257661,258075,258476,258494,258579,258609,258699: Several enhancements to the I/O APIC support in bhyve including: - Move the I/O APIC device model from userspace into vmm.ko and add ioctls to assert and deassert I/O APIC pins. - Add HPET device emulation including a single timer block with 8 timers. - Remove the 'vdev' abstraction.
Approved by: neel
|
#
259837 |
|
24-Dec-2013 |
jhb |
MFC 259013: Fix the processor table entry structure to use a fixed-width type for 32-bit fields so it is the correct size on amd64. Remove a workaround for the broken structure from bhyve(8).
|
#
259301 |
|
13-Dec-2013 |
grehan |
MFC r256657,r257018,r257347,r257423,r257729,r257767, r257933,r258609,r258614,r258668,r258673,r258855
Pull in some minor bugfixes and functionality enhancements from CURRENT. These are candidates to be moved to 10.0-release.
r258855 mdoc: quote string properly.
r258673 Don't create an initial value for the host filesystem of "/".
r258668 Allow bhyve and bhyveload to attach to tty devices.
r258614 The 22-bit Data Byte Count (DBC) field of a Physical Region Descriptor was being read as a 32-bit quantity by the bhyve AHCI driver.
r258609 Fix discrepancy between the IOAPIC ID advertised by firmware tables and the actual value read by the guest.
r257933 Route the legacy timer interrupt (IRQ0) to pin 2 of the IOAPIC.
r257767 Fix an off-by-one error when iterating over the emulated PCI BARs.
r257729 Add the VM name to the process name with setproctitle().
r257423 Make the virtual ioapic available unconditionally in a bhyve virtual machine.
r257347 Update copyright to include the author of the LPC bridge emulation code.
hand-merge r257018 Tidy usage messages for bhyve and bhyveload.
r256657 Add an option to bhyveload(8) that allows setting a loader environment variable from the command line.
Discussed with: neel
|
#
256755 |
|
18-Oct-2013 |
grehan |
MFC r256709:
Eliminate unconditional debug printfs.
Linux writes to these nominally read-only registers, so avoid having bhyve write warning messages to stdout when the reg writes can be safely ignored. Change the WPRINTF to DPRINTF which is conditional.
Approved by: re (delphij)
|
#
268972 |
|
22-Jul-2014 |
jhb |
MFC 266125: Implement a PCI interrupt router to route PCI legacy INTx interrupts to the legacy 8259A PICs.
|
#
268887 |
|
19-Jul-2014 |
jhb |
MFC 261904,261905,262143,262184,264921,265211,267169,267292,267294: Various PCI fixes: - Allow PCI devices to be configured on all valid bus numbers from 0 to 255. - Tweak the handling of PCI capabilities in emulated devices to remove the non-standard zero capability list terminator. - Add a check to validate that memory BARs of passthru devices are 4KB aligned. - Respect and track the enable bit in the PCI configuration address word. - Handle quad-word access to 32-bit register pairs.
|
#
267393 |
|
12-Jun-2014 |
jhb |
MFC 260239,261268,265058: Expand the support for PCI INTx interrupts including providing interrupt routing information for INTx interrupts to I/O APIC pins and enabling INTx interrupts in the virtio and AHCI backends.
|
#
262350 |
|
22-Feb-2014 |
jhb |
MFC 258859,259081,259085,259205,259213,259275,259482,259537,259702,259779: Several changes to the local APIC support in bhyve: - Rename 'vm_interrupt_hostcpu()' to 'vcpu_notify_event()'. - If a vcpu disables its local apic and then executes a 'HLT' then spin down the vcpu and destroy its thread context. Also modify the 'HLT' processing to ignore pending interrupts in the IRR if interrupts have been disabled by the guest. The interrupt cannot be injected into the guest in any case so resuming it is futile. - Use callout(9) to drive the vlapic timer instead of clocking it on each VM exit. - When the guest is bringing up the APs in the x2APIC mode a write to the ICR register will now trigger a return to userspace with an exitcode of VM_EXITCODE_SPINUP_AP. - Change the vlapic timer lock to be a spinlock because the vlapic can be accessed from within a critical section (vm run loop) when guest is using x2apic mode. - Fix the vlapic version register. - Add a command to bhyvectl to inject an NMI on a specific vcpu. - Add an API to deliver message signalled interrupts to vcpus. This allows callers to treat the MSI 'addr' and 'data' fields as opaque and also lets bhyve implement multiple destination modes: physical, flat and clustered. - Rename the ambiguously named 'vm_setup_msi()' and 'vm_setup_msix()' to 'vm_setup_pptdev_msi()' and 'vm_setup_pptdev_msix()' respectively. - Consolidate the virtual apic initialization in a single function: vlapic_reset() - Add a generic routine to trigger an LVT interrupt that supports both fixed and NMI delivery modes. - Add an ioctl and bhyvectl command to trigger local interrupts inside a guest. In particular, a global NMI similar to that raised by SERR# or PERR# can be simulated by asserting LINT1 on all vCPUs. - Extend the LVT table in the vCPU local APIC to support CMCI. - Flesh out the local APIC error reporting a bit to cache errors and report them via ESR when ESR is written to. Add support for asserting the error LVT when an error occurs. Raise illegal vector errors when attempting to signal an invalid vector for an interrupt or when sending an IPI. - Export table entries in the MADT and MP Table advertising the stock x86 config of LINT0 set to ExtInt and LINT1 wired to NMI.
|
#
261090 |
|
23-Jan-2014 |
jhb |
MFC 259826,259997,259998: Support soft power-off via the ACPI S5 state for bhyve guests and wire up a virtual power button to SIGTERM: - Implement the PM1_EVT and PM1_CTL registers required by ACPI. - Emulate the Reset Control register at I/O port 0xcf9. - Advertise an _S5 package. - Implement an SMI_CMD register with commands to enable and disable ACPI. Currently the only change when ACPI is enabled is to enable the virtual power button via SIGTERM. - Implement a fixed-feature power button when ACPI is enabled by asserting PWRBTN_STS in PM1_EVT when SIGTERM is received. - Add support for EVFILT_SIGNAL events to mevent. - Implement support for the ACPI system command interrupt (SCI) and assert it when needed based on the values in PM1_EVT. Mark the SCI as active-low and level triggered in the MADT and MP Table.
|
#
261088 |
|
23-Jan-2014 |
jhb |
MFC 257422,257661,258075,258476,258494,258579,258609,258699: Several enhancements to the I/O APIC support in bhyve including: - Move the I/O APIC device model from userspace into vmm.ko and add ioctls to assert and deassert I/O APIC pins. - Add HPET device emulation including a single timer block with 8 timers. - Remove the 'vdev' abstraction.
Approved by: neel
|
#
259837 |
|
24-Dec-2013 |
jhb |
MFC 259013: Fix the processor table entry structure to use a fixed-width type for 32-bit fields so it is the correct size on amd64. Remove a workaround for the broken structure from bhyve(8).
|
#
259301 |
|
13-Dec-2013 |
grehan |
MFC r256657,r257018,r257347,r257423,r257729,r257767, r257933,r258609,r258614,r258668,r258673,r258855
Pull in some minor bugfixes and functionality enhancements from CURRENT. These are candidates to be moved to 10.0-release.
r258855 mdoc: quote string properly.
r258673 Don't create an initial value for the host filesystem of "/".
r258668 Allow bhyve and bhyveload to attach to tty devices.
r258614 The 22-bit Data Byte Count (DBC) field of a Physical Region Descriptor was being read as a 32-bit quantity by the bhyve AHCI driver.
r258609 Fix discrepancy between the IOAPIC ID advertised by firmware tables and the actual value read by the guest.
r257933 Route the legacy timer interrupt (IRQ0) to pin 2 of the IOAPIC.
r257767 Fix an off-by-one error when iterating over the emulated PCI BARs.
r257729 Add the VM name to the process name with setproctitle().
r257423 Make the virtual ioapic available unconditionally in a bhyve virtual machine.
r257347 Update copyright to include the author of the LPC bridge emulation code.
hand-merge r257018 Tidy usage messages for bhyve and bhyveload.
r256657 Add an option to bhyveload(8) that allows setting a loader environment variable from the command line.
Discussed with: neel
|
#
256755 |
|
18-Oct-2013 |
grehan |
MFC r256709:
Eliminate unconditional debug printfs.
Linux writes to these nominally read-only registers, so avoid having bhyve write warning messages to stdout when the reg writes can be safely ignored. Change the WPRINTF to DPRINTF which is conditional.
Approved by: re (delphij)
|