mptbl.c revision 261090 
1/*-
2 * Copyright (c) 2012 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/usr.sbin/bhyve/mptbl.c 261090 2014-01-23 20:35:32Z jhb $
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/mptbl.c 261090 2014-01-23 20:35:32Z jhb $");
31
32#include <sys/types.h>
33#include <sys/errno.h>
34#include <x86/mptable.h>
35
36#include <stdio.h>
37#include <string.h>
38
39#include "acpi.h"
40#include "bhyverun.h"
41#include "mptbl.h"
42
43#define MPTABLE_BASE		0xF0000
44
45/* floating pointer length + maximum length of configuration table */
46#define	MPTABLE_MAX_LENGTH	(65536 + 16)
47
48#define LAPIC_PADDR		0xFEE00000
49#define LAPIC_VERSION 		16
50
51#define IOAPIC_PADDR		0xFEC00000
52#define IOAPIC_VERSION		0x11
53
54#define MP_SPECREV		4
55#define MPFP_SIG		"_MP_"
56
57/* Configuration header defines */
58#define MPCH_SIG		"PCMP"
59#define MPCH_OEMID		"BHyVe   "
60#define MPCH_OEMID_LEN          8
61#define MPCH_PRODID             "Hypervisor  "
62#define MPCH_PRODID_LEN         12
63
64/* Processor entry defines */
65#define MPEP_SIG_FAMILY		6	/* XXX bhyve should supply this */
66#define MPEP_SIG_MODEL		26
67#define MPEP_SIG_STEPPING	5
68#define MPEP_SIG		\
69	((MPEP_SIG_FAMILY << 8) | \
70	 (MPEP_SIG_MODEL << 4)	| \
71	 (MPEP_SIG_STEPPING))
72
73#define MPEP_FEATURES           (0xBFEBFBFF) /* XXX Intel i7 */
74
75/* Number of i/o intr entries */
76#define	MPEII_MAX_IRQ		24
77
78/* Bus entry defines */
79#define MPE_NUM_BUSES		2
80#define MPE_BUSNAME_LEN		6
81#define MPE_BUSNAME_ISA		"ISA   "
82#define MPE_BUSNAME_PCI		"PCI   "
83
84static void *oem_tbl_start;
85static int oem_tbl_size;
86
87static uint8_t
88mpt_compute_checksum(void *base, size_t len)
89{
90	uint8_t	*bytes;
91	uint8_t	sum;
92
93	for(bytes = base, sum = 0; len > 0; len--) {
94		sum += *bytes++;
95	}
96
97	return (256 - sum);
98}
99
100static void
101mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa)
102{
103
104	memset(mpfp, 0, sizeof(*mpfp));
105	memcpy(mpfp->signature, MPFP_SIG, 4);
106	mpfp->pap = gpa + sizeof(*mpfp);
107	mpfp->length = 1;
108	mpfp->spec_rev = MP_SPECREV;
109	mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp));
110}
111
112static void
113mpt_build_mpch(mpcth_t mpch)
114{
115
116	memset(mpch, 0, sizeof(*mpch));
117	memcpy(mpch->signature, MPCH_SIG, 4);
118	mpch->spec_rev = MP_SPECREV;
119	memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN);
120	memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN);
121	mpch->apic_address = LAPIC_PADDR;
122}
123
124static void
125mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu)
126{
127	int i;
128
129	for (i = 0; i < ncpu; i++) {
130		memset(mpep, 0, sizeof(*mpep));
131		mpep->type = MPCT_ENTRY_PROCESSOR;
132		mpep->apic_id = i; // XXX
133		mpep->apic_version = LAPIC_VERSION;
134		mpep->cpu_flags = PROCENTRY_FLAG_EN;
135		if (i == 0)
136			mpep->cpu_flags |= PROCENTRY_FLAG_BP;
137		mpep->cpu_signature = MPEP_SIG;
138		mpep->feature_flags = MPEP_FEATURES;
139		mpep++;
140	}
141}
142
143static void
144mpt_build_bus_entries(bus_entry_ptr mpeb)
145{
146
147	memset(mpeb, 0, sizeof(*mpeb));
148	mpeb->type = MPCT_ENTRY_BUS;
149	mpeb->bus_id = 0;
150	memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN);
151	mpeb++;
152
153	memset(mpeb, 0, sizeof(*mpeb));
154	mpeb->type = MPCT_ENTRY_BUS;
155	mpeb->bus_id = 1;
156	memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
157}
158
159static void
160mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
161{
162
163	memset(mpei, 0, sizeof(*mpei));
164	mpei->type = MPCT_ENTRY_IOAPIC;
165	mpei->apic_id = id;
166	mpei->apic_version = IOAPIC_VERSION;
167	mpei->apic_flags = IOAPICENTRY_FLAG_EN;
168	mpei->apic_address = IOAPIC_PADDR;
169}
170
171static void
172mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
173{
174	int pin;
175
176	/*
177	 * The following config is taken from kernel mptable.c
178	 * mptable_parse_default_config_ints(...), for now
179	 * just use the default config, tweek later if needed.
180	 */
181
182	/* Run through all 16 pins. */
183	for (pin = 0; pin < num_pins; pin++) {
184		memset(mpie, 0, sizeof(*mpie));
185		mpie->type = MPCT_ENTRY_INT;
186		mpie->src_bus_id = 1;
187		mpie->dst_apic_id = id;
188
189		/*
190		 * All default configs route IRQs from bus 0 to the first 16
191		 * pins of the first I/O APIC with an APIC ID of 2.
192		 */
193		mpie->dst_apic_int = pin;
194		switch (pin) {
195		case 0:
196			/* Pin 0 is an ExtINT pin. */
197			mpie->int_type = INTENTRY_TYPE_EXTINT;
198			break;
199		case 2:
200			/* IRQ 0 is routed to pin 2. */
201			mpie->int_type = INTENTRY_TYPE_INT;
202			mpie->src_bus_irq = 0;
203			break;
204		case SCI_INT:
205			/* ACPI SCI is level triggered and active-lo. */
206			mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
207			    INTENTRY_FLAGS_TRIGGER_LEVEL;
208			mpie->int_type = INTENTRY_TYPE_INT;
209			mpie->src_bus_irq = SCI_INT;
210			break;
211		case 5:
212		case 10:
213		case 11:
214			/*
215			 * PCI Irqs set to level triggered and active-lo.
216			 */
217			mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
218			    INTENTRY_FLAGS_TRIGGER_LEVEL;
219			mpie->src_bus_id = 0;
220			/* fall through.. */
221		default:
222			/* All other pins are identity mapped. */
223			mpie->int_type = INTENTRY_TYPE_INT;
224			mpie->src_bus_irq = pin;
225			break;
226		}
227		mpie++;
228	}
229
230}
231
232void
233mptable_add_oemtbl(void *tbl, int tblsz)
234{
235
236	oem_tbl_start = tbl;
237	oem_tbl_size = tblsz;
238}
239
240int
241mptable_build(struct vmctx *ctx, int ncpu)
242{
243	mpcth_t			mpch;
244	bus_entry_ptr		mpeb;
245	io_apic_entry_ptr	mpei;
246	proc_entry_ptr		mpep;
247	mpfps_t			mpfp;
248	int_entry_ptr		mpie;
249	char 			*curraddr;
250	char 			*startaddr;
251
252	startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH);
253	if (startaddr == NULL) {
254		printf("mptable requires mapped mem\n");
255		return (ENOMEM);
256	}
257
258	curraddr = startaddr;
259	mpfp = (mpfps_t)curraddr;
260	mpt_build_mpfp(mpfp, MPTABLE_BASE);
261	curraddr += sizeof(*mpfp);
262
263	mpch = (mpcth_t)curraddr;
264	mpt_build_mpch(mpch);
265	curraddr += sizeof(*mpch);
266
267	mpep = (proc_entry_ptr)curraddr;
268	mpt_build_proc_entries(mpep, ncpu);
269	curraddr += sizeof(*mpep) * ncpu;
270	mpch->entry_count += ncpu;
271
272	mpeb = (bus_entry_ptr) curraddr;
273	mpt_build_bus_entries(mpeb);
274	curraddr += sizeof(*mpeb) * MPE_NUM_BUSES;
275	mpch->entry_count += MPE_NUM_BUSES;
276
277	mpei = (io_apic_entry_ptr)curraddr;
278	mpt_build_ioapic_entries(mpei, 0);
279	curraddr += sizeof(*mpei);
280	mpch->entry_count++;
281
282	mpie = (int_entry_ptr) curraddr;
283	mpt_build_ioint_entries(mpie, MPEII_MAX_IRQ, 0);
284	curraddr += sizeof(*mpie) * MPEII_MAX_IRQ;
285	mpch->entry_count += MPEII_MAX_IRQ;
286
287	if (oem_tbl_start) {
288		mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE;
289		mpch->oem_table_size = oem_tbl_size;
290		memcpy(curraddr, oem_tbl_start, oem_tbl_size);
291	}
292
293	mpch->base_table_length = curraddr - (char *)mpch;
294	mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);
295
296	return (0);
297}
298