mptbl.c revision 262350 
1/*-
2 * Copyright (c) 2012 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/usr.sbin/bhyve/mptbl.c 262350 2014-02-23 00:46:05Z jhb $
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/mptbl.c 262350 2014-02-23 00:46:05Z jhb $");
31
32#include <sys/types.h>
33#include <sys/errno.h>
34#include <x86/mptable.h>
35
36#include <stdio.h>
37#include <string.h>
38
39#include "acpi.h"
40#include "bhyverun.h"
41#include "mptbl.h"
42
43#define MPTABLE_BASE		0xF0000
44
45/* floating pointer length + maximum length of configuration table */
46#define	MPTABLE_MAX_LENGTH	(65536 + 16)
47
48#define LAPIC_PADDR		0xFEE00000
49#define LAPIC_VERSION 		16
50
51#define IOAPIC_PADDR		0xFEC00000
52#define IOAPIC_VERSION		0x11
53
54#define MP_SPECREV		4
55#define MPFP_SIG		"_MP_"
56
57/* Configuration header defines */
58#define MPCH_SIG		"PCMP"
59#define MPCH_OEMID		"BHyVe   "
60#define MPCH_OEMID_LEN          8
61#define MPCH_PRODID             "Hypervisor  "
62#define MPCH_PRODID_LEN         12
63
64/* Processor entry defines */
65#define MPEP_SIG_FAMILY		6	/* XXX bhyve should supply this */
66#define MPEP_SIG_MODEL		26
67#define MPEP_SIG_STEPPING	5
68#define MPEP_SIG		\
69	((MPEP_SIG_FAMILY << 8) | \
70	 (MPEP_SIG_MODEL << 4)	| \
71	 (MPEP_SIG_STEPPING))
72
73#define MPEP_FEATURES           (0xBFEBFBFF) /* XXX Intel i7 */
74
75/* Number of local intr entries */
76#define	MPEII_NUM_LOCAL_IRQ	2
77
78/* Number of i/o intr entries */
79#define	MPEII_MAX_IRQ		24
80
81/* Bus entry defines */
82#define MPE_NUM_BUSES		2
83#define MPE_BUSNAME_LEN		6
84#define MPE_BUSNAME_ISA		"ISA   "
85#define MPE_BUSNAME_PCI		"PCI   "
86
87static void *oem_tbl_start;
88static int oem_tbl_size;
89
90static uint8_t
91mpt_compute_checksum(void *base, size_t len)
92{
93	uint8_t	*bytes;
94	uint8_t	sum;
95
96	for(bytes = base, sum = 0; len > 0; len--) {
97		sum += *bytes++;
98	}
99
100	return (256 - sum);
101}
102
103static void
104mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa)
105{
106
107	memset(mpfp, 0, sizeof(*mpfp));
108	memcpy(mpfp->signature, MPFP_SIG, 4);
109	mpfp->pap = gpa + sizeof(*mpfp);
110	mpfp->length = 1;
111	mpfp->spec_rev = MP_SPECREV;
112	mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp));
113}
114
115static void
116mpt_build_mpch(mpcth_t mpch)
117{
118
119	memset(mpch, 0, sizeof(*mpch));
120	memcpy(mpch->signature, MPCH_SIG, 4);
121	mpch->spec_rev = MP_SPECREV;
122	memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN);
123	memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN);
124	mpch->apic_address = LAPIC_PADDR;
125}
126
127static void
128mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu)
129{
130	int i;
131
132	for (i = 0; i < ncpu; i++) {
133		memset(mpep, 0, sizeof(*mpep));
134		mpep->type = MPCT_ENTRY_PROCESSOR;
135		mpep->apic_id = i; // XXX
136		mpep->apic_version = LAPIC_VERSION;
137		mpep->cpu_flags = PROCENTRY_FLAG_EN;
138		if (i == 0)
139			mpep->cpu_flags |= PROCENTRY_FLAG_BP;
140		mpep->cpu_signature = MPEP_SIG;
141		mpep->feature_flags = MPEP_FEATURES;
142		mpep++;
143	}
144}
145
146static void
147mpt_build_localint_entries(int_entry_ptr mpie)
148{
149
150	/* Hardcode LINT0 as ExtINT on all CPUs. */
151	memset(mpie, 0, sizeof(*mpie));
152	mpie->type = MPCT_ENTRY_LOCAL_INT;
153	mpie->int_type = INTENTRY_TYPE_EXTINT;
154	mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
155	    INTENTRY_FLAGS_TRIGGER_CONFORM;
156	mpie->dst_apic_id = 0xff;
157	mpie->dst_apic_int = 0;
158	mpie++;
159
160	/* Hardcode LINT1 as NMI on all CPUs. */
161	memset(mpie, 0, sizeof(*mpie));
162	mpie->type = MPCT_ENTRY_LOCAL_INT;
163	mpie->int_type = INTENTRY_TYPE_NMI;
164	mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
165	    INTENTRY_FLAGS_TRIGGER_CONFORM;
166	mpie->dst_apic_id = 0xff;
167	mpie->dst_apic_int = 1;
168}
169
170static void
171mpt_build_bus_entries(bus_entry_ptr mpeb)
172{
173
174	memset(mpeb, 0, sizeof(*mpeb));
175	mpeb->type = MPCT_ENTRY_BUS;
176	mpeb->bus_id = 0;
177	memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN);
178	mpeb++;
179
180	memset(mpeb, 0, sizeof(*mpeb));
181	mpeb->type = MPCT_ENTRY_BUS;
182	mpeb->bus_id = 1;
183	memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
184}
185
186static void
187mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
188{
189
190	memset(mpei, 0, sizeof(*mpei));
191	mpei->type = MPCT_ENTRY_IOAPIC;
192	mpei->apic_id = id;
193	mpei->apic_version = IOAPIC_VERSION;
194	mpei->apic_flags = IOAPICENTRY_FLAG_EN;
195	mpei->apic_address = IOAPIC_PADDR;
196}
197
198static void
199mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
200{
201	int pin;
202
203	/*
204	 * The following config is taken from kernel mptable.c
205	 * mptable_parse_default_config_ints(...), for now
206	 * just use the default config, tweek later if needed.
207	 */
208
209	/* Run through all 16 pins. */
210	for (pin = 0; pin < num_pins; pin++) {
211		memset(mpie, 0, sizeof(*mpie));
212		mpie->type = MPCT_ENTRY_INT;
213		mpie->src_bus_id = 1;
214		mpie->dst_apic_id = id;
215
216		/*
217		 * All default configs route IRQs from bus 0 to the first 16
218		 * pins of the first I/O APIC with an APIC ID of 2.
219		 */
220		mpie->dst_apic_int = pin;
221		switch (pin) {
222		case 0:
223			/* Pin 0 is an ExtINT pin. */
224			mpie->int_type = INTENTRY_TYPE_EXTINT;
225			break;
226		case 2:
227			/* IRQ 0 is routed to pin 2. */
228			mpie->int_type = INTENTRY_TYPE_INT;
229			mpie->src_bus_irq = 0;
230			break;
231		case SCI_INT:
232			/* ACPI SCI is level triggered and active-lo. */
233			mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
234			    INTENTRY_FLAGS_TRIGGER_LEVEL;
235			mpie->int_type = INTENTRY_TYPE_INT;
236			mpie->src_bus_irq = SCI_INT;
237			break;
238		case 5:
239		case 10:
240		case 11:
241			/*
242			 * PCI Irqs set to level triggered and active-lo.
243			 */
244			mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
245			    INTENTRY_FLAGS_TRIGGER_LEVEL;
246			mpie->src_bus_id = 0;
247			/* fall through.. */
248		default:
249			/* All other pins are identity mapped. */
250			mpie->int_type = INTENTRY_TYPE_INT;
251			mpie->src_bus_irq = pin;
252			break;
253		}
254		mpie++;
255	}
256
257}
258
259void
260mptable_add_oemtbl(void *tbl, int tblsz)
261{
262
263	oem_tbl_start = tbl;
264	oem_tbl_size = tblsz;
265}
266
267int
268mptable_build(struct vmctx *ctx, int ncpu)
269{
270	mpcth_t			mpch;
271	bus_entry_ptr		mpeb;
272	io_apic_entry_ptr	mpei;
273	proc_entry_ptr		mpep;
274	mpfps_t			mpfp;
275	int_entry_ptr		mpie;
276	char 			*curraddr;
277	char 			*startaddr;
278
279	startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH);
280	if (startaddr == NULL) {
281		printf("mptable requires mapped mem\n");
282		return (ENOMEM);
283	}
284
285	curraddr = startaddr;
286	mpfp = (mpfps_t)curraddr;
287	mpt_build_mpfp(mpfp, MPTABLE_BASE);
288	curraddr += sizeof(*mpfp);
289
290	mpch = (mpcth_t)curraddr;
291	mpt_build_mpch(mpch);
292	curraddr += sizeof(*mpch);
293
294	mpep = (proc_entry_ptr)curraddr;
295	mpt_build_proc_entries(mpep, ncpu);
296	curraddr += sizeof(*mpep) * ncpu;
297	mpch->entry_count += ncpu;
298
299	mpeb = (bus_entry_ptr) curraddr;
300	mpt_build_bus_entries(mpeb);
301	curraddr += sizeof(*mpeb) * MPE_NUM_BUSES;
302	mpch->entry_count += MPE_NUM_BUSES;
303
304	mpei = (io_apic_entry_ptr)curraddr;
305	mpt_build_ioapic_entries(mpei, 0);
306	curraddr += sizeof(*mpei);
307	mpch->entry_count++;
308
309	mpie = (int_entry_ptr) curraddr;
310	mpt_build_ioint_entries(mpie, MPEII_MAX_IRQ, 0);
311	curraddr += sizeof(*mpie) * MPEII_MAX_IRQ;
312	mpch->entry_count += MPEII_MAX_IRQ;
313
314	mpie = (int_entry_ptr)curraddr;
315	mpt_build_localint_entries(mpie);
316	curraddr += sizeof(*mpie) * MPEII_NUM_LOCAL_IRQ;
317	mpch->entry_count += MPEII_NUM_LOCAL_IRQ;
318
319	if (oem_tbl_start) {
320		mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE;
321		mpch->oem_table_size = oem_tbl_size;
322		memcpy(curraddr, oem_tbl_start, oem_tbl_size);
323	}
324
325	mpch->base_table_length = curraddr - (char *)mpch;
326	mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);
327
328	return (0);
329}
330