1/*-
2 * Copyright (c) 2012 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include <sys/types.h>
33#include <sys/errno.h>
34#include <x86/mptable.h>
35
36#include <stdio.h>
37#include <string.h>
38
39#include "acpi.h"
40#include "bhyverun.h"
41#include "mptbl.h"
42#include "pci_emul.h"
43
44#define MPTABLE_BASE		0xF0000
45
46/* floating pointer length + maximum length of configuration table */
47#define	MPTABLE_MAX_LENGTH	(65536 + 16)
48
49#define LAPIC_PADDR		0xFEE00000
50#define LAPIC_VERSION 		16
51
52#define IOAPIC_PADDR		0xFEC00000
53#define IOAPIC_VERSION		0x11
54
55#define MP_SPECREV		4
56#define MPFP_SIG		"_MP_"
57
58/* Configuration header defines */
59#define MPCH_SIG		"PCMP"
60#define MPCH_OEMID		"BHyVe   "
61#define MPCH_OEMID_LEN          8
62#define MPCH_PRODID             "Hypervisor  "
63#define MPCH_PRODID_LEN         12
64
65/* Processor entry defines */
66#define MPEP_SIG_FAMILY		6	/* XXX bhyve should supply this */
67#define MPEP_SIG_MODEL		26
68#define MPEP_SIG_STEPPING	5
69#define MPEP_SIG		\
70	((MPEP_SIG_FAMILY << 8) | \
71	 (MPEP_SIG_MODEL << 4)	| \
72	 (MPEP_SIG_STEPPING))
73
74#define MPEP_FEATURES           (0xBFEBFBFF) /* XXX Intel i7 */
75
76/* Number of local intr entries */
77#define	MPEII_NUM_LOCAL_IRQ	2
78
79/* Bus entry defines */
80#define MPE_NUM_BUSES		2
81#define MPE_BUSNAME_LEN		6
82#define MPE_BUSNAME_ISA		"ISA   "
83#define MPE_BUSNAME_PCI		"PCI   "
84
85static void *oem_tbl_start;
86static int oem_tbl_size;
87
88static uint8_t
89mpt_compute_checksum(void *base, size_t len)
90{
91	uint8_t	*bytes;
92	uint8_t	sum;
93
94	for(bytes = base, sum = 0; len > 0; len--) {
95		sum += *bytes++;
96	}
97
98	return (256 - sum);
99}
100
101static void
102mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa)
103{
104
105	memset(mpfp, 0, sizeof(*mpfp));
106	memcpy(mpfp->signature, MPFP_SIG, 4);
107	mpfp->pap = gpa + sizeof(*mpfp);
108	mpfp->length = 1;
109	mpfp->spec_rev = MP_SPECREV;
110	mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp));
111}
112
113static void
114mpt_build_mpch(mpcth_t mpch)
115{
116
117	memset(mpch, 0, sizeof(*mpch));
118	memcpy(mpch->signature, MPCH_SIG, 4);
119	mpch->spec_rev = MP_SPECREV;
120	memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN);
121	memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN);
122	mpch->apic_address = LAPIC_PADDR;
123}
124
125static void
126mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu)
127{
128	int i;
129
130	for (i = 0; i < ncpu; i++) {
131		memset(mpep, 0, sizeof(*mpep));
132		mpep->type = MPCT_ENTRY_PROCESSOR;
133		mpep->apic_id = i; // XXX
134		mpep->apic_version = LAPIC_VERSION;
135		mpep->cpu_flags = PROCENTRY_FLAG_EN;
136		if (i == 0)
137			mpep->cpu_flags |= PROCENTRY_FLAG_BP;
138		mpep->cpu_signature = MPEP_SIG;
139		mpep->feature_flags = MPEP_FEATURES;
140		mpep++;
141	}
142}
143
144static void
145mpt_build_localint_entries(int_entry_ptr mpie)
146{
147
148	/* Hardcode LINT0 as ExtINT on all CPUs. */
149	memset(mpie, 0, sizeof(*mpie));
150	mpie->type = MPCT_ENTRY_LOCAL_INT;
151	mpie->int_type = INTENTRY_TYPE_EXTINT;
152	mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
153	    INTENTRY_FLAGS_TRIGGER_CONFORM;
154	mpie->dst_apic_id = 0xff;
155	mpie->dst_apic_int = 0;
156	mpie++;
157
158	/* Hardcode LINT1 as NMI on all CPUs. */
159	memset(mpie, 0, sizeof(*mpie));
160	mpie->type = MPCT_ENTRY_LOCAL_INT;
161	mpie->int_type = INTENTRY_TYPE_NMI;
162	mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
163	    INTENTRY_FLAGS_TRIGGER_CONFORM;
164	mpie->dst_apic_id = 0xff;
165	mpie->dst_apic_int = 1;
166}
167
168static void
169mpt_build_bus_entries(bus_entry_ptr mpeb)
170{
171
172	memset(mpeb, 0, sizeof(*mpeb));
173	mpeb->type = MPCT_ENTRY_BUS;
174	mpeb->bus_id = 0;
175	memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN);
176	mpeb++;
177
178	memset(mpeb, 0, sizeof(*mpeb));
179	mpeb->type = MPCT_ENTRY_BUS;
180	mpeb->bus_id = 1;
181	memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
182}
183
184static void
185mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
186{
187
188	memset(mpei, 0, sizeof(*mpei));
189	mpei->type = MPCT_ENTRY_IOAPIC;
190	mpei->apic_id = id;
191	mpei->apic_version = IOAPIC_VERSION;
192	mpei->apic_flags = IOAPICENTRY_FLAG_EN;
193	mpei->apic_address = IOAPIC_PADDR;
194}
195
196static int
197mpt_count_ioint_entries(void)
198{
199	int bus, count;
200
201	count = 0;
202	for (bus = 0; bus <= PCI_BUSMAX; bus++)
203		count += pci_count_lintr(bus);
204
205	/*
206	 * Always include entries for the first 16 pins along with a entry
207	 * for each active PCI INTx pin.
208	 */
209	return (16 + count);
210}
211
212static void
213mpt_generate_pci_int(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
214    void *arg)
215{
216	int_entry_ptr *mpiep, mpie;
217
218	mpiep = arg;
219	mpie = *mpiep;
220	memset(mpie, 0, sizeof(*mpie));
221
222	/*
223	 * This is always after another I/O interrupt entry, so cheat
224	 * and fetch the I/O APIC ID from the prior entry.
225	 */
226	mpie->type = MPCT_ENTRY_INT;
227	mpie->int_type = INTENTRY_TYPE_INT;
228	mpie->src_bus_id = bus;
229	mpie->src_bus_irq = slot << 2 | (pin - 1);
230	mpie->dst_apic_id = mpie[-1].dst_apic_id;
231	mpie->dst_apic_int = ioapic_irq;
232
233	*mpiep = mpie + 1;
234}
235
236static void
237mpt_build_ioint_entries(int_entry_ptr mpie, int id)
238{
239	int pin, bus;
240
241	/*
242	 * The following config is taken from kernel mptable.c
243	 * mptable_parse_default_config_ints(...), for now
244	 * just use the default config, tweek later if needed.
245	 */
246
247	/* First, generate the first 16 pins. */
248	for (pin = 0; pin < 16; pin++) {
249		memset(mpie, 0, sizeof(*mpie));
250		mpie->type = MPCT_ENTRY_INT;
251		mpie->src_bus_id = 1;
252		mpie->dst_apic_id = id;
253
254		/*
255		 * All default configs route IRQs from bus 0 to the first 16
256		 * pins of the first I/O APIC with an APIC ID of 2.
257		 */
258		mpie->dst_apic_int = pin;
259		switch (pin) {
260		case 0:
261			/* Pin 0 is an ExtINT pin. */
262			mpie->int_type = INTENTRY_TYPE_EXTINT;
263			break;
264		case 2:
265			/* IRQ 0 is routed to pin 2. */
266			mpie->int_type = INTENTRY_TYPE_INT;
267			mpie->src_bus_irq = 0;
268			break;
269		case SCI_INT:
270			/* ACPI SCI is level triggered and active-lo. */
271			mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
272			    INTENTRY_FLAGS_TRIGGER_LEVEL;
273			mpie->int_type = INTENTRY_TYPE_INT;
274			mpie->src_bus_irq = SCI_INT;
275			break;
276		default:
277			/* All other pins are identity mapped. */
278			mpie->int_type = INTENTRY_TYPE_INT;
279			mpie->src_bus_irq = pin;
280			break;
281		}
282		mpie++;
283	}
284
285	/* Next, generate entries for any PCI INTx interrupts. */
286	for (bus = 0; bus <= PCI_BUSMAX; bus++)
287		pci_walk_lintr(bus, mpt_generate_pci_int, &mpie);
288}
289
290void
291mptable_add_oemtbl(void *tbl, int tblsz)
292{
293
294	oem_tbl_start = tbl;
295	oem_tbl_size = tblsz;
296}
297
298int
299mptable_build(struct vmctx *ctx, int ncpu)
300{
301	mpcth_t			mpch;
302	bus_entry_ptr		mpeb;
303	io_apic_entry_ptr	mpei;
304	proc_entry_ptr		mpep;
305	mpfps_t			mpfp;
306	int_entry_ptr		mpie;
307	int			ioints, bus;
308	char 			*curraddr;
309	char 			*startaddr;
310
311	startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH);
312	if (startaddr == NULL) {
313		fprintf(stderr, "mptable requires mapped mem\n");
314		return (ENOMEM);
315	}
316
317	/*
318	 * There is no way to advertise multiple PCI hierarchies via MPtable
319	 * so require that there is no PCI hierarchy with a non-zero bus
320	 * number.
321	 */
322	for (bus = 1; bus <= PCI_BUSMAX; bus++) {
323		if (pci_bus_configured(bus)) {
324			fprintf(stderr, "MPtable is incompatible with "
325			    "multiple PCI hierarchies.\r\n");
326			fprintf(stderr, "MPtable generation can be disabled "
327			    "by passing the -Y option to bhyve(8).\r\n");
328			return (EINVAL);
329		}
330	}
331
332	curraddr = startaddr;
333	mpfp = (mpfps_t)curraddr;
334	mpt_build_mpfp(mpfp, MPTABLE_BASE);
335	curraddr += sizeof(*mpfp);
336
337	mpch = (mpcth_t)curraddr;
338	mpt_build_mpch(mpch);
339	curraddr += sizeof(*mpch);
340
341	mpep = (proc_entry_ptr)curraddr;
342	mpt_build_proc_entries(mpep, ncpu);
343	curraddr += sizeof(*mpep) * ncpu;
344	mpch->entry_count += ncpu;
345
346	mpeb = (bus_entry_ptr) curraddr;
347	mpt_build_bus_entries(mpeb);
348	curraddr += sizeof(*mpeb) * MPE_NUM_BUSES;
349	mpch->entry_count += MPE_NUM_BUSES;
350
351	mpei = (io_apic_entry_ptr)curraddr;
352	mpt_build_ioapic_entries(mpei, 0);
353	curraddr += sizeof(*mpei);
354	mpch->entry_count++;
355
356	mpie = (int_entry_ptr) curraddr;
357	ioints = mpt_count_ioint_entries();
358	mpt_build_ioint_entries(mpie, 0);
359	curraddr += sizeof(*mpie) * ioints;
360	mpch->entry_count += ioints;
361
362	mpie = (int_entry_ptr)curraddr;
363	mpt_build_localint_entries(mpie);
364	curraddr += sizeof(*mpie) * MPEII_NUM_LOCAL_IRQ;
365	mpch->entry_count += MPEII_NUM_LOCAL_IRQ;
366
367	if (oem_tbl_start) {
368		mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE;
369		mpch->oem_table_size = oem_tbl_size;
370		memcpy(curraddr, oem_tbl_start, oem_tbl_size);
371	}
372
373	mpch->base_table_length = curraddr - (char *)mpch;
374	mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);
375
376	return (0);
377}
378