Searched refs:Undef (Results 1 - 17 of 17) sorted by relevance

/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h35 Undef = 0x20, enumerator in enum:llvm::RegState::__anon1918
39 DefineNoRead = Define | Undef,
73 flags & RegState::Undef,
351 return B ? RegState::Undef : 0;
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUStructurizeCFG.cpp523 Value *Undef = UndefValue::get(Phi.getType()); local
524 Phi.addIncoming(Undef, From);
547 Value *Undef = UndefValue::get(Phi->getType()); local
549 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef);
550 Updater.AddAvailableValue(To, Undef);
562 Updater.AddAvailableValue(Dominator.getResult(), Undef);
849 Value *Undef = UndefValue::get(II->getType()); local
851 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef);
/freebsd-10.0-release/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp786 Value *Undef = UndefValue::get(FirstPhi.getType()); local
788 ReplaceInstUsesWith(*PHIsToSlice[i], Undef);
789 return ReplaceInstUsesWith(FirstPhi, Undef);
H A DInstCombineSimplifyDemanded.cpp857 return 0; // Undef.
945 Constant *Undef = UndefValue::get(EltTy); local
950 Elts.push_back(Undef);
959 Elts.push_back(Undef);
/freebsd-10.0-release/contrib/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp805 Constant *Undef = UndefValue::get(I->getType()); local
807 Undef, Undef, "", I);
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/CodeGen/
H A DCodeGenFunction.cpp519 llvm::Value *Undef = llvm::UndefValue::get(Int32Ty); local
520 AllocaInsertPt = new llvm::BitCastInst(Undef, Int32Ty, "", EntryBB);
H A DItaniumCXXABI.cpp886 RValue Undef = RValue::get(llvm::UndefValue::get(T)); local
887 return ItaniumCXXABI::EmitReturnFromThunk(CGF, Undef, ResultType);
/freebsd-10.0-release/contrib/llvm/include/llvm/IR/
H A DIRBuilder.h1411 Value *Undef = UndefValue::get(VectorType::get(V->getType(), NumElts)); local
1412 V = CreateInsertElement(Undef, V, ConstantInt::get(I32Ty, 0),
1417 return CreateShuffleVector(V, Undef, Zeros, Name + ".splat");
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp4454 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4455 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
4465 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4466 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
4517 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4518 SDValue Ops[] = { Chain, Val, Ptr, Undef };
4585 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4586 SDValue Ops[] = { Chain, Val, Ptr, Undef };
H A DDAGCombiner.cpp2524 // Undef bits can contribute to a possible optimisation if set, so
5704 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
7370 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); local
7374 Undef.getNode()->dump(&DAG);
7377 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); local
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp463 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
465 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; enumerator in enum:OpcTypes
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp3535 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3854 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3860 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
H A DX86ISelLowering.cpp5776 // of the result come from the same quadword of one of the two inputs. Undef
8396 SDValue Undef = DAG.getUNDEF(InVT); local
8398 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8399 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8481 SDValue Undef = DAG.getUNDEF(VT); local
8482 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8483 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8534 SDValue Undef = DAG.getUNDEF(MVT::v16i8); local
8535 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8536 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask
9742 SDValue Undef = DAG.getUNDEF(InVT); local
13350 unsigned Undef = MRI.createVirtualRegister(RC32); local
[all...]
H A DX86ISelDAGToDAG.cpp1768 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, local
1780 SDValue RetVals[] = { Undef, Ret };
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1937 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); local
1947 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
1953 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DIfConversion.cpp1004 MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3896 .addReg(DReg, RegState::Undef)

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