Searched refs:SHL (Results 1 - 25 of 44) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h26 case ISD::SHL: return ARM_AM::lsl;
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp179 { ISD::SHL, MVT::v4i32, 1 },
182 { ISD::SHL, MVT::v8i32, 1 },
185 { ISD::SHL, MVT::v2i64, 1 },
187 { ISD::SHL, MVT::v4i64, 1 },
190 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
191 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
213 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
214 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
215 { ISD::SHL, MVT::v4i32, 1 }, // pslld
216 { ISD::SHL, MV
[all...]
H A DX86ISelDAGToDAG.cpp791 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
817 if (Shift.getOpcode() != ISD::SHL ||
836 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
943 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
1017 case ISD::SHL:
1240 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
2099 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
H A DX86ISelLowering.cpp805 setOperationAction(ISD::SHL, VT, Expand);
1060 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1061 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1071 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1072 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1137 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1138 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1216 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1217 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1323 setTargetDAGCombine(ISD::SHL);
11585 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, local
11629 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, local
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/freebsd-10.0-release/usr.bin/xlint/lint1/
H A Dop.h79 SHL, enumerator in enum:__anon11527
H A Dscan.l128 "<<" return (operator(T_SHFTOP, SHL));
H A Dtree.c131 { SHL, { 1,0,1,0,0,1,1,0,0,0,0,0,1,0,0,1,1,
594 if (mp->m_balance || (tflag && (op == SHL || op == SHR)))
626 case SHL:
787 if (op == SHL || op == SHR || op == SHLASS || op == SHRASS) {
942 case SHL:
948 * width of the right operand. For SHL this may result in
2389 * Create a node for operators SHL and SHR.
2707 case SHL:
3502 case SHL:
3833 case SHL
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h318 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
382 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon2425
H A DMSP430ISelLowering.cpp96 setOperationAction(ISD::SHL, MVT::i8, Custom);
99 setOperationAction(ISD::SHL, MVT::i16, Custom);
189 case ISD::SHL: // FALLTHROUGH
634 case ISD::SHL:
635 return DAG.getNode(MSP430ISD::SHL, dl,
660 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
1032 case MSP430ISD::SHL: return "MSP430ISD::SHL";
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
537 return DAG.getNode(ISD::SHL, N->getDebugLoc(), Res.getValueType(), Res, Amt);
729 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
795 case ISD::SHL:
900 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1150 case ISD::SHL:
1267 if (N->getOpcode() == ISD::SHL) {
1272 Hi = DAG.getNode(ISD::SHL, DL,
1287 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1289 DAG.getNode(ISD::SHL, D
[all...]
H A DLegalizeVectorOps.cpp208 case ISD::SHL:
465 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
484 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
635 // Make sure that the SRA and SHL instructions are available.
637 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
648 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
711 // Notice that we can also use SHL+SHR, but using a constant is slightly
H A DDAGCombiner.cpp1121 case ISD::SHL: return visitSHL(N);
1204 case ISD::SHL:
1364 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1366 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1489 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1493 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1499 if (N1.getOpcode() == ISD::SHL &&
1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1508 if (N0.getOpcode() == ISD::SHL &&
1514 DAG.getNode(ISD::SHL,
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H A DTargetLowering.cpp579 case ISD::SHL:
595 unsigned Opc = ISD::SHL;
621 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
626 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
655 if (InOp.getOpcode() == ISD::SHL &&
663 Opc = ISD::SHL;
748 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
954 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
955 // place. We expect the SHL to be eliminated by other optimizations.
962 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, d
[all...]
H A DLegalizeDAG.cpp557 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
1003 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1033 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1273 case ISD::SHL:
1539 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
2504 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2508 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2509 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2518 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2519 Tmp7 = DAG.getNode(ISD::SHL, d
[all...]
H A DFastISel.cpp995 return SelectBinaryOp(I, ISD::SHL);
1158 Opcode = ISD::SHL;
1168 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
H A DSelectionDAGBuilder.h489 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
H A DSelectionDAGDumper.cpp171 case ISD::SHL: return "shl";
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp368 if (Opcode == ISD::SHL) {
419 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
421 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
428 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
429 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
441 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
444 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
448 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
451 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
1182 case ISD::SHL
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H A DPPCISelLowering.h100 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
/freebsd-10.0-release/crypto/openssl/crypto/sha/asm/
H A Dsha512-ppc.pl46 $SHL="sldi";
54 $SHL="slwi";
187 $SHL $num,$num,`log(16*$SZ)/log(2)`
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp633 if (Shl.getOpcode() != ISD::SHL)
1637 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1640 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1684 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1694 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1725 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1750 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1853 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1855 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1887 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, D
[all...]
H A DMipsSEISelLowering.cpp56 setTargetDAGCombine(ISD::SHL);
435 case ISD::SHL:
/freebsd-10.0-release/crypto/openssl/crypto/bn/asm/
H A Dppc.pl120 $SHL= "slw"; # shift left
144 $SHL= "sld"; # shift left
1648 $SHL r3,r3,r7 # h = (h<< i)
1650 $SHL r5,r5,r7 # d<<=i
1652 $SHL r4,r4,r7 # l <<=i
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp282 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
1047 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1502 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1510 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));

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