1//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a pattern matching instruction selector for PowerPC, 11// converting from a legalized dag to a PPC dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "ppc-codegen" 16#include "PPC.h" 17#include "MCTargetDesc/PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/IR/Constants.h" 25#include "llvm/IR/Function.h" 26#include "llvm/IR/GlobalAlias.h" 27#include "llvm/IR/GlobalValue.h" 28#include "llvm/IR/GlobalVariable.h" 29#include "llvm/IR/Intrinsics.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetOptions.h" 35using namespace llvm; 36 37namespace llvm { 38 void initializePPCDAGToDAGISelPass(PassRegistry&); 39} 40 41namespace { 42 //===--------------------------------------------------------------------===// 43 /// PPCDAGToDAGISel - PPC specific code to select PPC machine 44 /// instructions for SelectionDAG operations. 45 /// 46 class PPCDAGToDAGISel : public SelectionDAGISel { 47 const PPCTargetMachine &TM; 48 const PPCTargetLowering &PPCLowering; 49 const PPCSubtarget &PPCSubTarget; 50 unsigned GlobalBaseReg; 51 public: 52 explicit PPCDAGToDAGISel(PPCTargetMachine &tm) 53 : SelectionDAGISel(tm), TM(tm), 54 PPCLowering(*TM.getTargetLowering()), 55 PPCSubTarget(*TM.getSubtargetImpl()) { 56 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry()); 57 } 58 59 virtual bool runOnMachineFunction(MachineFunction &MF) { 60 // Make sure we re-emit a set of the global base reg if necessary 61 GlobalBaseReg = 0; 62 SelectionDAGISel::runOnMachineFunction(MF); 63 64 if (!PPCSubTarget.isSVR4ABI()) 65 InsertVRSaveCode(MF); 66 67 return true; 68 } 69 70 virtual void PostprocessISelDAG(); 71 72 /// getI32Imm - Return a target constant with the specified value, of type 73 /// i32. 74 inline SDValue getI32Imm(unsigned Imm) { 75 return CurDAG->getTargetConstant(Imm, MVT::i32); 76 } 77 78 /// getI64Imm - Return a target constant with the specified value, of type 79 /// i64. 80 inline SDValue getI64Imm(uint64_t Imm) { 81 return CurDAG->getTargetConstant(Imm, MVT::i64); 82 } 83 84 /// getSmallIPtrImm - Return a target constant of pointer type. 85 inline SDValue getSmallIPtrImm(unsigned Imm) { 86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 87 } 88 89 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s 90 /// with any number of 0s on either side. The 1s are allowed to wrap from 91 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 92 /// 0x0F0F0000 is not, since all 1s are not contiguous. 93 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); 94 95 96 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 97 /// rotate and mask opcode and mask operation. 98 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask, 99 unsigned &SH, unsigned &MB, unsigned &ME); 100 101 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 102 /// base register. Return the virtual register that holds this value. 103 SDNode *getGlobalBaseReg(); 104 105 // Select - Convert the specified operand from a target-independent to a 106 // target-specific node if it hasn't already been changed. 107 SDNode *Select(SDNode *N); 108 109 SDNode *SelectBitfieldInsert(SDNode *N); 110 111 /// SelectCC - Select a comparison of the specified values with the 112 /// specified condition code, returning the CR# of the expression. 113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); 114 115 /// SelectAddrImm - Returns true if the address N can be represented by 116 /// a base register plus a signed 16-bit displacement [r+imm]. 117 bool SelectAddrImm(SDValue N, SDValue &Disp, 118 SDValue &Base) { 119 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); 120 } 121 122 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc 123 /// immediate field. Note that the operand at this point is already the 124 /// result of a prior SelectAddressRegImm call. 125 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { 126 if (N.getOpcode() == ISD::TargetConstant || 127 N.getOpcode() == ISD::TargetGlobalAddress) { 128 Out = N; 129 return true; 130 } 131 132 return false; 133 } 134 135 /// SelectAddrIdx - Given the specified addressed, check to see if it can be 136 /// represented as an indexed [r+r] operation. Returns false if it can 137 /// be represented by [r+imm], which are preferred. 138 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) { 139 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); 140 } 141 142 /// SelectAddrIdxOnly - Given the specified addressed, force it to be 143 /// represented as an indexed [r+r] operation. 144 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { 145 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); 146 } 147 148 /// SelectAddrImmShift - Returns true if the address N can be represented by 149 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable 150 /// for use by STD and friends. 151 bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) { 152 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG); 153 } 154 155 // Select an address into a single register. 156 bool SelectAddr(SDValue N, SDValue &Base) { 157 Base = N; 158 return true; 159 } 160 161 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 162 /// inline asm expressions. It is always correct to compute the value into 163 /// a register. The case of adding a (possibly relocatable) constant to a 164 /// register can be improved, but it is wrong to substitute Reg+Reg for 165 /// Reg in an asm, because the load or store opcode would have to change. 166 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 167 char ConstraintCode, 168 std::vector<SDValue> &OutOps) { 169 OutOps.push_back(Op); 170 return false; 171 } 172 173 void InsertVRSaveCode(MachineFunction &MF); 174 175 virtual const char *getPassName() const { 176 return "PowerPC DAG->DAG Pattern Instruction Selection"; 177 } 178 179// Include the pieces autogenerated from the target description. 180#include "PPCGenDAGISel.inc" 181 182private: 183 SDNode *SelectSETCC(SDNode *N); 184 }; 185} 186 187/// InsertVRSaveCode - Once the entire function has been instruction selected, 188/// all virtual registers are created and all machine instructions are built, 189/// check to see if we need to save/restore VRSAVE. If so, do it. 190void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { 191 // Check to see if this function uses vector registers, which means we have to 192 // save and restore the VRSAVE register and update it with the regs we use. 193 // 194 // In this case, there will be virtual registers of vector type created 195 // by the scheduler. Detect them now. 196 bool HasVectorVReg = false; 197 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { 198 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 199 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 200 HasVectorVReg = true; 201 break; 202 } 203 } 204 if (!HasVectorVReg) return; // nothing to do. 205 206 // If we have a vector register, we want to emit code into the entry and exit 207 // blocks to save and restore the VRSAVE register. We do this here (instead 208 // of marking all vector instructions as clobbering VRSAVE) for two reasons: 209 // 210 // 1. This (trivially) reduces the load on the register allocator, by not 211 // having to represent the live range of the VRSAVE register. 212 // 2. This (more significantly) allows us to create a temporary virtual 213 // register to hold the saved VRSAVE value, allowing this temporary to be 214 // register allocated, instead of forcing it to be spilled to the stack. 215 216 // Create two vregs - one to hold the VRSAVE register that is live-in to the 217 // function and one for the value after having bits or'd into it. 218 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 219 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 220 221 const TargetInstrInfo &TII = *TM.getInstrInfo(); 222 MachineBasicBlock &EntryBB = *Fn.begin(); 223 DebugLoc dl; 224 // Emit the following code into the entry block: 225 // InVRSAVE = MFVRSAVE 226 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE 227 // MTVRSAVE UpdatedVRSAVE 228 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point 229 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 230 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 231 UpdatedVRSAVE).addReg(InVRSAVE); 232 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 233 234 // Find all return blocks, outputting a restore in each epilog. 235 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 236 if (!BB->empty() && BB->back().isReturn()) { 237 IP = BB->end(); --IP; 238 239 // Skip over all terminator instructions, which are part of the return 240 // sequence. 241 MachineBasicBlock::iterator I2 = IP; 242 while (I2 != BB->begin() && (--I2)->isTerminator()) 243 IP = I2; 244 245 // Emit: MTVRSAVE InVRSave 246 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 247 } 248 } 249} 250 251 252/// getGlobalBaseReg - Output the instructions required to put the 253/// base address to use for accessing globals into a register. 254/// 255SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { 256 if (!GlobalBaseReg) { 257 const TargetInstrInfo &TII = *TM.getInstrInfo(); 258 // Insert the set of GlobalBaseReg into the first MBB of the function 259 MachineBasicBlock &FirstMBB = MF->front(); 260 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 261 DebugLoc dl; 262 263 if (PPCLowering.getPointerTy() == MVT::i32) { 264 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 265 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 266 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 267 } else { 268 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass); 269 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); 270 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); 271 } 272 } 273 return CurDAG->getRegister(GlobalBaseReg, 274 PPCLowering.getPointerTy()).getNode(); 275} 276 277/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 278/// or 64-bit immediate, and if the value can be accurately represented as a 279/// sign extension from a 16-bit value. If so, this returns true and the 280/// immediate. 281static bool isIntS16Immediate(SDNode *N, short &Imm) { 282 if (N->getOpcode() != ISD::Constant) 283 return false; 284 285 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 286 if (N->getValueType(0) == MVT::i32) 287 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 288 else 289 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 290} 291 292static bool isIntS16Immediate(SDValue Op, short &Imm) { 293 return isIntS16Immediate(Op.getNode(), Imm); 294} 295 296 297/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 298/// operand. If so Imm will receive the 32-bit value. 299static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 301 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 302 return true; 303 } 304 return false; 305} 306 307/// isInt64Immediate - This method tests to see if the node is a 64-bit constant 308/// operand. If so Imm will receive the 64-bit value. 309static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { 310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 311 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 312 return true; 313 } 314 return false; 315} 316 317// isInt32Immediate - This method tests to see if a constant operand. 318// If so Imm will receive the 32 bit value. 319static bool isInt32Immediate(SDValue N, unsigned &Imm) { 320 return isInt32Immediate(N.getNode(), Imm); 321} 322 323 324// isOpcWithIntImmediate - This method tests to see if the node is a specific 325// opcode and that it has a immediate integer right operand. 326// If so Imm will receive the 32 bit value. 327static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 328 return N->getOpcode() == Opc 329 && isInt32Immediate(N->getOperand(1).getNode(), Imm); 330} 331 332bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 333 if (isShiftedMask_32(Val)) { 334 // look for the first non-zero bit 335 MB = CountLeadingZeros_32(Val); 336 // look for the first zero bit after the run of ones 337 ME = CountLeadingZeros_32((Val - 1) ^ Val); 338 return true; 339 } else { 340 Val = ~Val; // invert mask 341 if (isShiftedMask_32(Val)) { 342 // effectively look for the first zero bit 343 ME = CountLeadingZeros_32(Val) - 1; 344 // effectively look for the first one bit after the run of zeros 345 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1; 346 return true; 347 } 348 } 349 // no run present 350 return false; 351} 352 353bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, 354 bool isShiftMask, unsigned &SH, 355 unsigned &MB, unsigned &ME) { 356 // Don't even go down this path for i64, since different logic will be 357 // necessary for rldicl/rldicr/rldimi. 358 if (N->getValueType(0) != MVT::i32) 359 return false; 360 361 unsigned Shift = 32; 362 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 363 unsigned Opcode = N->getOpcode(); 364 if (N->getNumOperands() != 2 || 365 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) 366 return false; 367 368 if (Opcode == ISD::SHL) { 369 // apply shift left to mask if it comes first 370 if (isShiftMask) Mask = Mask << Shift; 371 // determine which bits are made indeterminant by shift 372 Indeterminant = ~(0xFFFFFFFFu << Shift); 373 } else if (Opcode == ISD::SRL) { 374 // apply shift right to mask if it comes first 375 if (isShiftMask) Mask = Mask >> Shift; 376 // determine which bits are made indeterminant by shift 377 Indeterminant = ~(0xFFFFFFFFu >> Shift); 378 // adjust for the left rotate 379 Shift = 32 - Shift; 380 } else if (Opcode == ISD::ROTL) { 381 Indeterminant = 0; 382 } else { 383 return false; 384 } 385 386 // if the mask doesn't intersect any Indeterminant bits 387 if (Mask && !(Mask & Indeterminant)) { 388 SH = Shift & 31; 389 // make sure the mask is still a mask (wrap arounds may not be) 390 return isRunOfOnes(Mask, MB, ME); 391 } 392 return false; 393} 394 395/// SelectBitfieldInsert - turn an or of two masked values into 396/// the rotate left word immediate then mask insert (rlwimi) instruction. 397SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { 398 SDValue Op0 = N->getOperand(0); 399 SDValue Op1 = N->getOperand(1); 400 DebugLoc dl = N->getDebugLoc(); 401 402 APInt LKZ, LKO, RKZ, RKO; 403 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); 404 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); 405 406 unsigned TargetMask = LKZ.getZExtValue(); 407 unsigned InsertMask = RKZ.getZExtValue(); 408 409 if ((TargetMask | InsertMask) == 0xFFFFFFFF) { 410 unsigned Op0Opc = Op0.getOpcode(); 411 unsigned Op1Opc = Op1.getOpcode(); 412 unsigned Value, SH = 0; 413 TargetMask = ~TargetMask; 414 InsertMask = ~InsertMask; 415 416 // If the LHS has a foldable shift and the RHS does not, then swap it to the 417 // RHS so that we can fold the shift into the insert. 418 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 419 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 420 Op0.getOperand(0).getOpcode() == ISD::SRL) { 421 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 422 Op1.getOperand(0).getOpcode() != ISD::SRL) { 423 std::swap(Op0, Op1); 424 std::swap(Op0Opc, Op1Opc); 425 std::swap(TargetMask, InsertMask); 426 } 427 } 428 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 429 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 430 Op1.getOperand(0).getOpcode() != ISD::SRL) { 431 std::swap(Op0, Op1); 432 std::swap(Op0Opc, Op1Opc); 433 std::swap(TargetMask, InsertMask); 434 } 435 } 436 437 unsigned MB, ME; 438 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { 439 SDValue Tmp1, Tmp2; 440 441 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 442 isInt32Immediate(Op1.getOperand(1), Value)) { 443 Op1 = Op1.getOperand(0); 444 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 445 } 446 if (Op1Opc == ISD::AND) { 447 unsigned SHOpc = Op1.getOperand(0).getOpcode(); 448 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 449 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { 450 Op1 = Op1.getOperand(0).getOperand(0); 451 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 452 } else { 453 Op1 = Op1.getOperand(0); 454 } 455 } 456 457 SH &= 31; 458 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), 459 getI32Imm(ME) }; 460 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 461 } 462 } 463 return 0; 464} 465 466/// SelectCC - Select a comparison of the specified values with the specified 467/// condition code, returning the CR# of the expression. 468SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, 469 ISD::CondCode CC, DebugLoc dl) { 470 // Always select the LHS. 471 unsigned Opc; 472 473 if (LHS.getValueType() == MVT::i32) { 474 unsigned Imm; 475 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 476 if (isInt32Immediate(RHS, Imm)) { 477 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 478 if (isUInt<16>(Imm)) 479 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 480 getI32Imm(Imm & 0xFFFF)), 0); 481 // If this is a 16-bit signed immediate, fold it. 482 if (isInt<16>((int)Imm)) 483 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 484 getI32Imm(Imm & 0xFFFF)), 0); 485 486 // For non-equality comparisons, the default code would materialize the 487 // constant, then compare against it, like this: 488 // lis r2, 4660 489 // ori r2, r2, 22136 490 // cmpw cr0, r3, r2 491 // Since we are just comparing for equality, we can emit this instead: 492 // xoris r0,r3,0x1234 493 // cmplwi cr0,r0,0x5678 494 // beq cr0,L6 495 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, 496 getI32Imm(Imm >> 16)), 0); 497 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, 498 getI32Imm(Imm & 0xFFFF)), 0); 499 } 500 Opc = PPC::CMPLW; 501 } else if (ISD::isUnsignedIntSetCC(CC)) { 502 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) 503 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 504 getI32Imm(Imm & 0xFFFF)), 0); 505 Opc = PPC::CMPLW; 506 } else { 507 short SImm; 508 if (isIntS16Immediate(RHS, SImm)) 509 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 510 getI32Imm((int)SImm & 0xFFFF)), 511 0); 512 Opc = PPC::CMPW; 513 } 514 } else if (LHS.getValueType() == MVT::i64) { 515 uint64_t Imm; 516 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 517 if (isInt64Immediate(RHS.getNode(), Imm)) { 518 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 519 if (isUInt<16>(Imm)) 520 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 521 getI32Imm(Imm & 0xFFFF)), 0); 522 // If this is a 16-bit signed immediate, fold it. 523 if (isInt<16>(Imm)) 524 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 525 getI32Imm(Imm & 0xFFFF)), 0); 526 527 // For non-equality comparisons, the default code would materialize the 528 // constant, then compare against it, like this: 529 // lis r2, 4660 530 // ori r2, r2, 22136 531 // cmpd cr0, r3, r2 532 // Since we are just comparing for equality, we can emit this instead: 533 // xoris r0,r3,0x1234 534 // cmpldi cr0,r0,0x5678 535 // beq cr0,L6 536 if (isUInt<32>(Imm)) { 537 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, 538 getI64Imm(Imm >> 16)), 0); 539 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, 540 getI64Imm(Imm & 0xFFFF)), 0); 541 } 542 } 543 Opc = PPC::CMPLD; 544 } else if (ISD::isUnsignedIntSetCC(CC)) { 545 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) 546 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 547 getI64Imm(Imm & 0xFFFF)), 0); 548 Opc = PPC::CMPLD; 549 } else { 550 short SImm; 551 if (isIntS16Immediate(RHS, SImm)) 552 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 553 getI64Imm(SImm & 0xFFFF)), 554 0); 555 Opc = PPC::CMPD; 556 } 557 } else if (LHS.getValueType() == MVT::f32) { 558 Opc = PPC::FCMPUS; 559 } else { 560 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); 561 Opc = PPC::FCMPUD; 562 } 563 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); 564} 565 566static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 567 switch (CC) { 568 case ISD::SETUEQ: 569 case ISD::SETONE: 570 case ISD::SETOLE: 571 case ISD::SETOGE: 572 llvm_unreachable("Should be lowered by legalize!"); 573 default: llvm_unreachable("Unknown condition!"); 574 case ISD::SETOEQ: 575 case ISD::SETEQ: return PPC::PRED_EQ; 576 case ISD::SETUNE: 577 case ISD::SETNE: return PPC::PRED_NE; 578 case ISD::SETOLT: 579 case ISD::SETLT: return PPC::PRED_LT; 580 case ISD::SETULE: 581 case ISD::SETLE: return PPC::PRED_LE; 582 case ISD::SETOGT: 583 case ISD::SETGT: return PPC::PRED_GT; 584 case ISD::SETUGE: 585 case ISD::SETGE: return PPC::PRED_GE; 586 case ISD::SETO: return PPC::PRED_NU; 587 case ISD::SETUO: return PPC::PRED_UN; 588 // These two are invalid for floating point. Assume we have int. 589 case ISD::SETULT: return PPC::PRED_LT; 590 case ISD::SETUGT: return PPC::PRED_GT; 591 } 592} 593 594/// getCRIdxForSetCC - Return the index of the condition register field 595/// associated with the SetCC condition, and whether or not the field is 596/// treated as inverted. That is, lt = 0; ge = 0 inverted. 597/// 598/// If this returns with Other != -1, then the returned comparison is an or of 599/// two simpler comparisons. In this case, Invert is guaranteed to be false. 600static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { 601 Invert = false; 602 Other = -1; 603 switch (CC) { 604 default: llvm_unreachable("Unknown condition!"); 605 case ISD::SETOLT: 606 case ISD::SETLT: return 0; // Bit #0 = SETOLT 607 case ISD::SETOGT: 608 case ISD::SETGT: return 1; // Bit #1 = SETOGT 609 case ISD::SETOEQ: 610 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 611 case ISD::SETUO: return 3; // Bit #3 = SETUO 612 case ISD::SETUGE: 613 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE 614 case ISD::SETULE: 615 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE 616 case ISD::SETUNE: 617 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE 618 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO 619 case ISD::SETUEQ: 620 case ISD::SETOGE: 621 case ISD::SETOLE: 622 case ISD::SETONE: 623 llvm_unreachable("Invalid branch code: should be expanded by legalize"); 624 // These are invalid for floating point. Assume integer. 625 case ISD::SETULT: return 0; 626 case ISD::SETUGT: return 1; 627 } 628} 629 630// getVCmpInst: return the vector compare instruction for the specified 631// vector type and condition code. Since this is for altivec specific code, 632// only support the altivec types (v16i8, v8i16, v4i32, and v4f32). 633static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { 634 switch (CC) { 635 case ISD::SETEQ: 636 case ISD::SETUEQ: 637 case ISD::SETNE: 638 case ISD::SETUNE: 639 if (VecVT == MVT::v16i8) 640 return PPC::VCMPEQUB; 641 else if (VecVT == MVT::v8i16) 642 return PPC::VCMPEQUH; 643 else if (VecVT == MVT::v4i32) 644 return PPC::VCMPEQUW; 645 // v4f32 != v4f32 could be translate to unordered not equal 646 else if (VecVT == MVT::v4f32) 647 return PPC::VCMPEQFP; 648 break; 649 case ISD::SETLT: 650 case ISD::SETGT: 651 case ISD::SETLE: 652 case ISD::SETGE: 653 if (VecVT == MVT::v16i8) 654 return PPC::VCMPGTSB; 655 else if (VecVT == MVT::v8i16) 656 return PPC::VCMPGTSH; 657 else if (VecVT == MVT::v4i32) 658 return PPC::VCMPGTSW; 659 else if (VecVT == MVT::v4f32) 660 return PPC::VCMPGTFP; 661 break; 662 case ISD::SETULT: 663 case ISD::SETUGT: 664 case ISD::SETUGE: 665 case ISD::SETULE: 666 if (VecVT == MVT::v16i8) 667 return PPC::VCMPGTUB; 668 else if (VecVT == MVT::v8i16) 669 return PPC::VCMPGTUH; 670 else if (VecVT == MVT::v4i32) 671 return PPC::VCMPGTUW; 672 break; 673 case ISD::SETOEQ: 674 if (VecVT == MVT::v4f32) 675 return PPC::VCMPEQFP; 676 break; 677 case ISD::SETOLT: 678 case ISD::SETOGT: 679 case ISD::SETOLE: 680 if (VecVT == MVT::v4f32) 681 return PPC::VCMPGTFP; 682 break; 683 case ISD::SETOGE: 684 if (VecVT == MVT::v4f32) 685 return PPC::VCMPGEFP; 686 break; 687 default: 688 break; 689 } 690 llvm_unreachable("Invalid integer vector compare condition"); 691} 692 693// getVCmpEQInst: return the equal compare instruction for the specified vector 694// type. Since this is for altivec specific code, only support the altivec 695// types (v16i8, v8i16, v4i32, and v4f32). 696static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) { 697 switch (VecVT) { 698 case MVT::v16i8: 699 return PPC::VCMPEQUB; 700 case MVT::v8i16: 701 return PPC::VCMPEQUH; 702 case MVT::v4i32: 703 return PPC::VCMPEQUW; 704 case MVT::v4f32: 705 return PPC::VCMPEQFP; 706 default: 707 llvm_unreachable("Invalid integer vector compare condition"); 708 } 709} 710 711 712SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) { 713 DebugLoc dl = N->getDebugLoc(); 714 unsigned Imm; 715 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 716 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 717 bool isPPC64 = (PtrVT == MVT::i64); 718 719 if (isInt32Immediate(N->getOperand(1), Imm)) { 720 // We can codegen setcc op, imm very efficiently compared to a brcond. 721 // Check for those cases here. 722 // setcc op, 0 723 if (Imm == 0) { 724 SDValue Op = N->getOperand(0); 725 switch (CC) { 726 default: break; 727 case ISD::SETEQ: { 728 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); 729 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; 730 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 731 } 732 case ISD::SETNE: { 733 if (isPPC64) break; 734 SDValue AD = 735 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 736 Op, getI32Imm(~0U)), 0); 737 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 738 AD.getValue(1)); 739 } 740 case ISD::SETLT: { 741 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 742 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 743 } 744 case ISD::SETGT: { 745 SDValue T = 746 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); 747 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); 748 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 749 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 750 } 751 } 752 } else if (Imm == ~0U) { // setcc op, -1 753 SDValue Op = N->getOperand(0); 754 switch (CC) { 755 default: break; 756 case ISD::SETEQ: 757 if (isPPC64) break; 758 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 759 Op, getI32Imm(1)), 0); 760 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 761 SDValue(CurDAG->getMachineNode(PPC::LI, dl, 762 MVT::i32, 763 getI32Imm(0)), 0), 764 Op.getValue(1)); 765 case ISD::SETNE: { 766 if (isPPC64) break; 767 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); 768 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 769 Op, getI32Imm(~0U)); 770 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), 771 Op, SDValue(AD, 1)); 772 } 773 case ISD::SETLT: { 774 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, 775 getI32Imm(1)), 0); 776 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, 777 Op), 0); 778 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 779 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 780 } 781 case ISD::SETGT: { 782 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 783 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 784 0); 785 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 786 getI32Imm(1)); 787 } 788 } 789 } 790 } 791 792 SDValue LHS = N->getOperand(0); 793 SDValue RHS = N->getOperand(1); 794 795 // Altivec Vector compare instructions do not set any CR register by default and 796 // vector compare operations return the same type as the operands. 797 if (LHS.getValueType().isVector()) { 798 EVT VecVT = LHS.getValueType(); 799 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy; 800 unsigned int VCmpInst = getVCmpInst(VT, CC); 801 802 switch (CC) { 803 case ISD::SETEQ: 804 case ISD::SETOEQ: 805 case ISD::SETUEQ: 806 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 807 case ISD::SETNE: 808 case ISD::SETONE: 809 case ISD::SETUNE: { 810 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 811 return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp); 812 } 813 case ISD::SETLT: 814 case ISD::SETOLT: 815 case ISD::SETULT: 816 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS); 817 case ISD::SETGT: 818 case ISD::SETOGT: 819 case ISD::SETUGT: 820 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 821 case ISD::SETGE: 822 case ISD::SETOGE: 823 case ISD::SETUGE: { 824 // Small optimization: Altivec provides a 'Vector Compare Greater Than 825 // or Equal To' instruction (vcmpgefp), so in this case there is no 826 // need for extra logic for the equal compare. 827 if (VecVT.getSimpleVT().isFloatingPoint()) { 828 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); 829 } else { 830 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); 831 unsigned int VCmpEQInst = getVCmpEQInst(VT); 832 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 833 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ); 834 } 835 } 836 case ISD::SETLE: 837 case ISD::SETOLE: 838 case ISD::SETULE: { 839 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0); 840 unsigned int VCmpEQInst = getVCmpEQInst(VT); 841 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); 842 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ); 843 } 844 default: 845 llvm_unreachable("Invalid vector compare type: should be expanded by legalize"); 846 } 847 } 848 849 bool Inv; 850 int OtherCondIdx; 851 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); 852 SDValue CCReg = SelectCC(LHS, RHS, CC, dl); 853 SDValue IntCR; 854 855 // Force the ccreg into CR7. 856 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 857 858 SDValue InFlag(0, 0); // Null incoming flag value. 859 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, 860 InFlag).getValue(1); 861 862 if (PPCSubTarget.hasMFOCRF() && OtherCondIdx == -1) 863 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, 864 CCReg), 0); 865 else 866 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32, 867 CR7Reg, CCReg), 0); 868 869 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), 870 getI32Imm(31), getI32Imm(31) }; 871 if (OtherCondIdx == -1 && !Inv) 872 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 873 874 // Get the specified bit. 875 SDValue Tmp = 876 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); 877 if (Inv) { 878 assert(OtherCondIdx == -1 && "Can't have split plus negation"); 879 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 880 } 881 882 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT. 883 // We already got the bit for the first part of the comparison (e.g. SETULE). 884 885 // Get the other bit of the comparison. 886 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); 887 SDValue OtherCond = 888 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); 889 890 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); 891} 892 893 894// Select - Convert the specified operand from a target-independent to a 895// target-specific node if it hasn't already been changed. 896SDNode *PPCDAGToDAGISel::Select(SDNode *N) { 897 DebugLoc dl = N->getDebugLoc(); 898 if (N->isMachineOpcode()) { 899 N->setNodeId(-1); 900 return NULL; // Already selected. 901 } 902 903 switch (N->getOpcode()) { 904 default: break; 905 906 case ISD::Constant: { 907 if (N->getValueType(0) == MVT::i64) { 908 // Get 64 bit value. 909 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); 910 // Assume no remaining bits. 911 unsigned Remainder = 0; 912 // Assume no shift required. 913 unsigned Shift = 0; 914 915 // If it can't be represented as a 32 bit value. 916 if (!isInt<32>(Imm)) { 917 Shift = CountTrailingZeros_64(Imm); 918 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 919 920 // If the shifted value fits 32 bits. 921 if (isInt<32>(ImmSh)) { 922 // Go with the shifted value. 923 Imm = ImmSh; 924 } else { 925 // Still stuck with a 64 bit value. 926 Remainder = Imm; 927 Shift = 32; 928 Imm >>= 32; 929 } 930 } 931 932 // Intermediate operand. 933 SDNode *Result; 934 935 // Handle first 32 bits. 936 unsigned Lo = Imm & 0xFFFF; 937 unsigned Hi = (Imm >> 16) & 0xFFFF; 938 939 // Simple value. 940 if (isInt<16>(Imm)) { 941 // Just the Lo bits. 942 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 943 } else if (Lo) { 944 // Handle the Hi bits. 945 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; 946 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); 947 // And Lo bits. 948 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 949 SDValue(Result, 0), getI32Imm(Lo)); 950 } else { 951 // Just the Hi bits. 952 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); 953 } 954 955 // If no shift, we're done. 956 if (!Shift) return Result; 957 958 // Shift for next step if the upper 32-bits were not zero. 959 if (Imm) { 960 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, 961 SDValue(Result, 0), 962 getI32Imm(Shift), 963 getI32Imm(63 - Shift)); 964 } 965 966 // Add in the last bits as required. 967 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 968 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, 969 SDValue(Result, 0), getI32Imm(Hi)); 970 } 971 if ((Lo = Remainder & 0xFFFF)) { 972 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 973 SDValue(Result, 0), getI32Imm(Lo)); 974 } 975 976 return Result; 977 } 978 break; 979 } 980 981 case ISD::SETCC: 982 return SelectSETCC(N); 983 case PPCISD::GlobalBaseReg: 984 return getGlobalBaseReg(); 985 986 case ISD::FrameIndex: { 987 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 988 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0)); 989 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; 990 if (N->hasOneUse()) 991 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI, 992 getSmallIPtrImm(0)); 993 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, 994 getSmallIPtrImm(0)); 995 } 996 997 case PPCISD::MFCR: { 998 SDValue InFlag = N->getOperand(1); 999 // Use MFOCRF if supported. 1000 if (PPCSubTarget.hasMFOCRF()) 1001 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, 1002 N->getOperand(0), InFlag); 1003 else 1004 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32, 1005 N->getOperand(0), InFlag); 1006 } 1007 1008 case ISD::SDIV: { 1009 // FIXME: since this depends on the setting of the carry flag from the srawi 1010 // we should really be making notes about that for the scheduler. 1011 // FIXME: It sure would be nice if we could cheaply recognize the 1012 // srl/add/sra pattern the dag combiner will generate for this as 1013 // sra/addze rather than having to handle sdiv ourselves. oh well. 1014 unsigned Imm; 1015 if (isInt32Immediate(N->getOperand(1), Imm)) { 1016 SDValue N0 = N->getOperand(0); 1017 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 1018 SDNode *Op = 1019 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 1020 N0, getI32Imm(Log2_32(Imm))); 1021 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 1022 SDValue(Op, 0), SDValue(Op, 1)); 1023 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 1024 SDNode *Op = 1025 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 1026 N0, getI32Imm(Log2_32(-Imm))); 1027 SDValue PT = 1028 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, 1029 SDValue(Op, 0), SDValue(Op, 1)), 1030 0); 1031 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 1032 } 1033 } 1034 1035 // Other cases are autogenerated. 1036 break; 1037 } 1038 1039 case ISD::LOAD: { 1040 // Handle preincrement loads. 1041 LoadSDNode *LD = cast<LoadSDNode>(N); 1042 EVT LoadedVT = LD->getMemoryVT(); 1043 1044 // Normal loads are handled by code generated from the .td file. 1045 if (LD->getAddressingMode() != ISD::PRE_INC) 1046 break; 1047 1048 SDValue Offset = LD->getOffset(); 1049 if (Offset.getOpcode() == ISD::TargetConstant || 1050 Offset.getOpcode() == ISD::TargetGlobalAddress) { 1051 1052 unsigned Opcode; 1053 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1054 if (LD->getValueType(0) != MVT::i64) { 1055 // Handle PPC32 integer and normal FP loads. 1056 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1057 switch (LoadedVT.getSimpleVT().SimpleTy) { 1058 default: llvm_unreachable("Invalid PPC load type!"); 1059 case MVT::f64: Opcode = PPC::LFDU; break; 1060 case MVT::f32: Opcode = PPC::LFSU; break; 1061 case MVT::i32: Opcode = PPC::LWZU; break; 1062 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 1063 case MVT::i1: 1064 case MVT::i8: Opcode = PPC::LBZU; break; 1065 } 1066 } else { 1067 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1068 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1069 switch (LoadedVT.getSimpleVT().SimpleTy) { 1070 default: llvm_unreachable("Invalid PPC load type!"); 1071 case MVT::i64: Opcode = PPC::LDU; break; 1072 case MVT::i32: Opcode = PPC::LWZU8; break; 1073 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 1074 case MVT::i1: 1075 case MVT::i8: Opcode = PPC::LBZU8; break; 1076 } 1077 } 1078 1079 SDValue Chain = LD->getChain(); 1080 SDValue Base = LD->getBasePtr(); 1081 SDValue Ops[] = { Offset, Base, Chain }; 1082 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1083 PPCLowering.getPointerTy(), 1084 MVT::Other, Ops); 1085 } else { 1086 unsigned Opcode; 1087 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 1088 if (LD->getValueType(0) != MVT::i64) { 1089 // Handle PPC32 integer and normal FP loads. 1090 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1091 switch (LoadedVT.getSimpleVT().SimpleTy) { 1092 default: llvm_unreachable("Invalid PPC load type!"); 1093 case MVT::f64: Opcode = PPC::LFDUX; break; 1094 case MVT::f32: Opcode = PPC::LFSUX; break; 1095 case MVT::i32: Opcode = PPC::LWZUX; break; 1096 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; 1097 case MVT::i1: 1098 case MVT::i8: Opcode = PPC::LBZUX; break; 1099 } 1100 } else { 1101 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 1102 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && 1103 "Invalid sext update load"); 1104 switch (LoadedVT.getSimpleVT().SimpleTy) { 1105 default: llvm_unreachable("Invalid PPC load type!"); 1106 case MVT::i64: Opcode = PPC::LDUX; break; 1107 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; 1108 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break; 1109 case MVT::i1: 1110 case MVT::i8: Opcode = PPC::LBZUX8; break; 1111 } 1112 } 1113 1114 SDValue Chain = LD->getChain(); 1115 SDValue Base = LD->getBasePtr(); 1116 SDValue Ops[] = { Base, Offset, Chain }; 1117 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 1118 PPCLowering.getPointerTy(), 1119 MVT::Other, Ops); 1120 } 1121 } 1122 1123 case ISD::AND: { 1124 unsigned Imm, Imm2, SH, MB, ME; 1125 uint64_t Imm64; 1126 1127 // If this is an and of a value rotated between 0 and 31 bits and then and'd 1128 // with a mask, emit rlwinm 1129 if (isInt32Immediate(N->getOperand(1), Imm) && 1130 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { 1131 SDValue Val = N->getOperand(0).getOperand(0); 1132 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1133 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1134 } 1135 // If this is just a masked value where the input is not handled above, and 1136 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm 1137 if (isInt32Immediate(N->getOperand(1), Imm) && 1138 isRunOfOnes(Imm, MB, ME) && 1139 N->getOperand(0).getOpcode() != ISD::ROTL) { 1140 SDValue Val = N->getOperand(0); 1141 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; 1142 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1143 } 1144 // If this is a 64-bit zero-extension mask, emit rldicl. 1145 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) && 1146 isMask_64(Imm64)) { 1147 SDValue Val = N->getOperand(0); 1148 MB = 64 - CountTrailingOnes_64(Imm64); 1149 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) }; 1150 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3); 1151 } 1152 // AND X, 0 -> 0, not "rlwinm 32". 1153 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { 1154 ReplaceUses(SDValue(N, 0), N->getOperand(1)); 1155 return NULL; 1156 } 1157 // ISD::OR doesn't get all the bitfield insertion fun. 1158 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert 1159 if (isInt32Immediate(N->getOperand(1), Imm) && 1160 N->getOperand(0).getOpcode() == ISD::OR && 1161 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { 1162 unsigned MB, ME; 1163 Imm = ~(Imm^Imm2); 1164 if (isRunOfOnes(Imm, MB, ME)) { 1165 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1166 N->getOperand(0).getOperand(1), 1167 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; 1168 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 1169 } 1170 } 1171 1172 // Other cases are autogenerated. 1173 break; 1174 } 1175 case ISD::OR: 1176 if (N->getValueType(0) == MVT::i32) 1177 if (SDNode *I = SelectBitfieldInsert(N)) 1178 return I; 1179 1180 // Other cases are autogenerated. 1181 break; 1182 case ISD::SHL: { 1183 unsigned Imm, SH, MB, ME; 1184 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1185 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1186 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1187 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1188 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1189 } 1190 1191 // Other cases are autogenerated. 1192 break; 1193 } 1194 case ISD::SRL: { 1195 unsigned Imm, SH, MB, ME; 1196 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1197 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1198 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1199 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1200 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1201 } 1202 1203 // Other cases are autogenerated. 1204 break; 1205 } 1206 case ISD::SELECT_CC: { 1207 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1208 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 1209 bool isPPC64 = (PtrVT == MVT::i64); 1210 1211 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1212 if (!isPPC64) 1213 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1214 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1215 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1216 if (N1C->isNullValue() && N3C->isNullValue() && 1217 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && 1218 // FIXME: Implement this optzn for PPC64. 1219 N->getValueType(0) == MVT::i32) { 1220 SDNode *Tmp = 1221 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 1222 N->getOperand(0), getI32Imm(~0U)); 1223 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, 1224 SDValue(Tmp, 0), N->getOperand(0), 1225 SDValue(Tmp, 1)); 1226 } 1227 1228 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 1229 unsigned BROpc = getPredicateForSetCC(CC); 1230 1231 unsigned SelectCCOp; 1232 if (N->getValueType(0) == MVT::i32) 1233 SelectCCOp = PPC::SELECT_CC_I4; 1234 else if (N->getValueType(0) == MVT::i64) 1235 SelectCCOp = PPC::SELECT_CC_I8; 1236 else if (N->getValueType(0) == MVT::f32) 1237 SelectCCOp = PPC::SELECT_CC_F4; 1238 else if (N->getValueType(0) == MVT::f64) 1239 SelectCCOp = PPC::SELECT_CC_F8; 1240 else 1241 SelectCCOp = PPC::SELECT_CC_VRRC; 1242 1243 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), 1244 getI32Imm(BROpc) }; 1245 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); 1246 } 1247 case PPCISD::COND_BRANCH: { 1248 // Op #0 is the Chain. 1249 // Op #1 is the PPC::PRED_* number. 1250 // Op #2 is the CR# 1251 // Op #3 is the Dest MBB 1252 // Op #4 is the Flag. 1253 // Prevent PPC::PRED_* from being selected into LI. 1254 SDValue Pred = 1255 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()); 1256 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), 1257 N->getOperand(0), N->getOperand(4) }; 1258 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); 1259 } 1260 case ISD::BR_CC: { 1261 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1262 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); 1263 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, 1264 N->getOperand(4), N->getOperand(0) }; 1265 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); 1266 } 1267 case ISD::BRIND: { 1268 // FIXME: Should custom lower this. 1269 SDValue Chain = N->getOperand(0); 1270 SDValue Target = N->getOperand(1); 1271 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; 1272 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; 1273 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target, 1274 Chain), 0); 1275 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); 1276 } 1277 case PPCISD::TOC_ENTRY: { 1278 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI"); 1279 1280 // For medium and large code model, we generate two instructions as 1281 // described below. Otherwise we allow SelectCodeCommon to handle this, 1282 // selecting one of LDtoc, LDtocJTI, and LDtocCPT. 1283 CodeModel::Model CModel = TM.getCodeModel(); 1284 if (CModel != CodeModel::Medium && CModel != CodeModel::Large) 1285 break; 1286 1287 // The first source operand is a TargetGlobalAddress or a 1288 // TargetJumpTable. If it is an externally defined symbol, a symbol 1289 // with common linkage, a function address, or a jump table address, 1290 // or if we are generating code for large code model, we generate: 1291 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>)) 1292 // Otherwise we generate: 1293 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>) 1294 SDValue GA = N->getOperand(0); 1295 SDValue TOCbase = N->getOperand(1); 1296 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64, 1297 TOCbase, GA); 1298 1299 if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large) 1300 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1301 SDValue(Tmp, 0)); 1302 1303 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) { 1304 const GlobalValue *GValue = G->getGlobal(); 1305 const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue); 1306 const GlobalValue *RealGValue = GAlias ? 1307 GAlias->resolveAliasedGlobal(false) : GValue; 1308 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue); 1309 assert((GVar || isa<Function>(RealGValue)) && 1310 "Unexpected global value subclass!"); 1311 1312 // An external variable is one without an initializer. For these, 1313 // for variables with common linkage, and for Functions, generate 1314 // the LDtocL form. 1315 if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() || 1316 RealGValue->hasAvailableExternallyLinkage()) 1317 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, 1318 SDValue(Tmp, 0)); 1319 } 1320 1321 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64, 1322 SDValue(Tmp, 0), GA); 1323 } 1324 case PPCISD::VADD_SPLAT: { 1325 // This expands into one of three sequences, depending on whether 1326 // the first operand is odd or even, positive or negative. 1327 assert(isa<ConstantSDNode>(N->getOperand(0)) && 1328 isa<ConstantSDNode>(N->getOperand(1)) && 1329 "Invalid operand on VADD_SPLAT!"); 1330 1331 int Elt = N->getConstantOperandVal(0); 1332 int EltSize = N->getConstantOperandVal(1); 1333 unsigned Opc1, Opc2, Opc3; 1334 EVT VT; 1335 1336 if (EltSize == 1) { 1337 Opc1 = PPC::VSPLTISB; 1338 Opc2 = PPC::VADDUBM; 1339 Opc3 = PPC::VSUBUBM; 1340 VT = MVT::v16i8; 1341 } else if (EltSize == 2) { 1342 Opc1 = PPC::VSPLTISH; 1343 Opc2 = PPC::VADDUHM; 1344 Opc3 = PPC::VSUBUHM; 1345 VT = MVT::v8i16; 1346 } else { 1347 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!"); 1348 Opc1 = PPC::VSPLTISW; 1349 Opc2 = PPC::VADDUWM; 1350 Opc3 = PPC::VSUBUWM; 1351 VT = MVT::v4i32; 1352 } 1353 1354 if ((Elt & 1) == 0) { 1355 // Elt is even, in the range [-32,-18] + [16,30]. 1356 // 1357 // Convert: VADD_SPLAT elt, size 1358 // Into: tmp = VSPLTIS[BHW] elt 1359 // VADDU[BHW]M tmp, tmp 1360 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4 1361 SDValue EltVal = getI32Imm(Elt >> 1); 1362 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1363 SDValue TmpVal = SDValue(Tmp, 0); 1364 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal); 1365 1366 } else if (Elt > 0) { 1367 // Elt is odd and positive, in the range [17,31]. 1368 // 1369 // Convert: VADD_SPLAT elt, size 1370 // Into: tmp1 = VSPLTIS[BHW] elt-16 1371 // tmp2 = VSPLTIS[BHW] -16 1372 // VSUBU[BHW]M tmp1, tmp2 1373 SDValue EltVal = getI32Imm(Elt - 16); 1374 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1375 EltVal = getI32Imm(-16); 1376 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1377 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), 1378 SDValue(Tmp2, 0)); 1379 1380 } else { 1381 // Elt is odd and negative, in the range [-31,-17]. 1382 // 1383 // Convert: VADD_SPLAT elt, size 1384 // Into: tmp1 = VSPLTIS[BHW] elt+16 1385 // tmp2 = VSPLTIS[BHW] -16 1386 // VADDU[BHW]M tmp1, tmp2 1387 SDValue EltVal = getI32Imm(Elt + 16); 1388 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1389 EltVal = getI32Imm(-16); 1390 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 1391 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), 1392 SDValue(Tmp2, 0)); 1393 } 1394 } 1395 } 1396 1397 return SelectCode(N); 1398} 1399 1400/// PostProcessISelDAG - Perform some late peephole optimizations 1401/// on the DAG representation. 1402void PPCDAGToDAGISel::PostprocessISelDAG() { 1403 1404 // Skip peepholes at -O0. 1405 if (TM.getOptLevel() == CodeGenOpt::None) 1406 return; 1407 1408 // These optimizations are currently supported only for 64-bit SVR4. 1409 if (PPCSubTarget.isDarwin() || !PPCSubTarget.isPPC64()) 1410 return; 1411 1412 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); 1413 ++Position; 1414 1415 while (Position != CurDAG->allnodes_begin()) { 1416 SDNode *N = --Position; 1417 // Skip dead nodes and any non-machine opcodes. 1418 if (N->use_empty() || !N->isMachineOpcode()) 1419 continue; 1420 1421 unsigned FirstOp; 1422 unsigned StorageOpcode = N->getMachineOpcode(); 1423 1424 switch (StorageOpcode) { 1425 default: continue; 1426 1427 case PPC::LBZ: 1428 case PPC::LBZ8: 1429 case PPC::LD: 1430 case PPC::LFD: 1431 case PPC::LFS: 1432 case PPC::LHA: 1433 case PPC::LHA8: 1434 case PPC::LHZ: 1435 case PPC::LHZ8: 1436 case PPC::LWA: 1437 case PPC::LWZ: 1438 case PPC::LWZ8: 1439 FirstOp = 0; 1440 break; 1441 1442 case PPC::STB: 1443 case PPC::STB8: 1444 case PPC::STD: 1445 case PPC::STFD: 1446 case PPC::STFS: 1447 case PPC::STH: 1448 case PPC::STH8: 1449 case PPC::STW: 1450 case PPC::STW8: 1451 FirstOp = 1; 1452 break; 1453 } 1454 1455 // If this is a load or store with a zero offset, we may be able to 1456 // fold an add-immediate into the memory operation. 1457 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) || 1458 N->getConstantOperandVal(FirstOp) != 0) 1459 continue; 1460 1461 SDValue Base = N->getOperand(FirstOp + 1); 1462 if (!Base.isMachineOpcode()) 1463 continue; 1464 1465 unsigned Flags = 0; 1466 bool ReplaceFlags = true; 1467 1468 // When the feeding operation is an add-immediate of some sort, 1469 // determine whether we need to add relocation information to the 1470 // target flags on the immediate operand when we fold it into the 1471 // load instruction. 1472 // 1473 // For something like ADDItocL, the relocation information is 1474 // inferred from the opcode; when we process it in the AsmPrinter, 1475 // we add the necessary relocation there. A load, though, can receive 1476 // relocation from various flavors of ADDIxxx, so we need to carry 1477 // the relocation information in the target flags. 1478 switch (Base.getMachineOpcode()) { 1479 default: continue; 1480 1481 case PPC::ADDI8: 1482 case PPC::ADDI: 1483 // In some cases (such as TLS) the relocation information 1484 // is already in place on the operand, so copying the operand 1485 // is sufficient. 1486 ReplaceFlags = false; 1487 // For these cases, the immediate may not be divisible by 4, in 1488 // which case the fold is illegal for DS-form instructions. (The 1489 // other cases provide aligned addresses and are always safe.) 1490 if ((StorageOpcode == PPC::LWA || 1491 StorageOpcode == PPC::LD || 1492 StorageOpcode == PPC::STD) && 1493 (!isa<ConstantSDNode>(Base.getOperand(1)) || 1494 Base.getConstantOperandVal(1) % 4 != 0)) 1495 continue; 1496 break; 1497 case PPC::ADDIdtprelL: 1498 Flags = PPCII::MO_DTPREL16_LO; 1499 break; 1500 case PPC::ADDItlsldL: 1501 Flags = PPCII::MO_TLSLD16_LO; 1502 break; 1503 case PPC::ADDItocL: 1504 Flags = PPCII::MO_TOC16_LO; 1505 break; 1506 } 1507 1508 // We found an opportunity. Reverse the operands from the add 1509 // immediate and substitute them into the load or store. If 1510 // needed, update the target flags for the immediate operand to 1511 // reflect the necessary relocation information. 1512 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); 1513 DEBUG(Base->dump(CurDAG)); 1514 DEBUG(dbgs() << "\nN: "); 1515 DEBUG(N->dump(CurDAG)); 1516 DEBUG(dbgs() << "\n"); 1517 1518 SDValue ImmOpnd = Base.getOperand(1); 1519 1520 // If the relocation information isn't already present on the 1521 // immediate operand, add it now. 1522 if (ReplaceFlags) { 1523 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { 1524 DebugLoc dl = GA->getDebugLoc(); 1525 const GlobalValue *GV = GA->getGlobal(); 1526 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); 1527 } else if (ConstantPoolSDNode *CP = 1528 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { 1529 const Constant *C = CP->getConstVal(); 1530 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, 1531 CP->getAlignment(), 1532 0, Flags); 1533 } 1534 } 1535 1536 if (FirstOp == 1) // Store 1537 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd, 1538 Base.getOperand(0), N->getOperand(3)); 1539 else // Load 1540 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0), 1541 N->getOperand(2)); 1542 1543 // The add-immediate may now be dead, in which case remove it. 1544 if (Base.getNode()->use_empty()) 1545 CurDAG->RemoveDeadNode(Base.getNode()); 1546 } 1547} 1548 1549 1550/// createPPCISelDag - This pass converts a legalized DAG into a 1551/// PowerPC-specific DAG, ready for instruction scheduling. 1552/// 1553FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { 1554 return new PPCDAGToDAGISel(TM); 1555} 1556 1557static void initializePassOnce(PassRegistry &Registry) { 1558 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection"; 1559 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID, 0, 1560 false, false); 1561 Registry.registerPass(*PI, true); 1562} 1563 1564void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) { 1565 CALL_ONCE_INITIALIZATION(initializePassOnce); 1566} 1567 1568