/freebsd-10.0-release/sys/contrib/dev/acpica/components/executer/ |
H A D | exfldio.c | 618 AcpiExWriteWithUpdateRule( ACPI_OPERAND_OBJECT *ObjDesc, UINT64 Mask, UINT64 FieldValue, UINT32 FieldDatumByteOffset) argument 889 UINT64 Mask; local [all...] |
/freebsd-10.0-release/sys/contrib/dev/acpica/components/disassembler/ |
H A D | dmresrc.c | 194 AcpiDmBitList( UINT16 Mask) argument
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/freebsd-10.0-release/sys/contrib/dev/acpica/components/resources/ |
H A D | rsutils.c | 118 UINT16 Mask; local 71 AcpiRsDecodeBitmask( UINT16 Mask, UINT8 *List) argument
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/freebsd-10.0-release/sys/contrib/dev/acpica/include/ |
H A D | actbl1.h | 123 UINT64 Mask; /* Bitmask required for this register instruction */ member in struct:acpi_whea_header
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H A D | actbl2.h | 195 UINT8 Mask; member in struct:acpi_asf_alert_data 1305 UINT32 Mask; /* Bitmask required for this register instruction */ member in struct:acpi_wdat_entry
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/freebsd-10.0-release/sys/dev/asr/ |
H A D | asr.c | 554 U32 Mask = 0xffffffff; local 743 U32 Mask; local
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/freebsd-10.0-release/sys/dev/rp/ |
H A D | rp.c | 491 Byte_t Mask; /* Interrupt Mask Register */ local 536 Byte_t Mask; /* Interrupt Mask Register */ local [all...] |
/freebsd-10.0-release/lib/libvgl/ |
H A D | vgl.h | 81 VGLBitmap *Mask; member in struct:VGLObject
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 988 unsigned Mask = RegInfo.createVirtualRegister(RC); local 1224 unsigned Mask local 2230 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); local [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 47 unsigned Mask = MI.getOperand(1).getImm(); local
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H A D | MipsSEISelLowering.h | 34 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1314 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); local 2002 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask(); local 2495 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask, argument 2451 getLSBForBFI(SelectionDAG &DAG, DebugLoc DL, EVT VT, SDValue &MaskedVal, uint64_t Mask) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 505 int Mask = 0, ImmValue = 0; local
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H A D | HexagonInstrInfo.cpp | 337 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsAsmBackend.cpp | 138 uint64_t Mask = ((uint64_t)(-1) >> local
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/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 1055 uint64_t Mask = (1ULL << Num1s) - 1; local
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 246 bool Mask = false; local
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 90 unsigned Mask; member in struct:__anon2543::FPS::LiveBundle 115 unsigned Mask = 0; local [all...] |
H A D | X86ISelDAGToDAG.cpp | 1068 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1); local 770 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 813 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 880 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 1249 uint64_t Mask = N.getConstantOperandVal(1); local [all...] |
H A D | X86ISelLowering.cpp | 2665 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); local 3328 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, argument 3339 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { argument 3349 isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) argument 3378 isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) argument 3407 isPALIGNRMask(ArrayRef<int> Mask, EVT VT, const X86Subtarget *Subtarget) argument 3480 CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, unsigned NumElems) argument 3497 isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256, bool Commuted = false) argument 3550 isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) argument 3569 isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) argument 3586 isMOVLPMask(ArrayRef<int> Mask, EVT VT) argument 3608 isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) argument 3677 isUNPCKLMask(ArrayRef<int> Mask, EVT VT, bool HasInt256, bool V2IsSplat = false) argument 3716 isUNPCKHMask(ArrayRef<int> Mask, EVT VT, bool HasInt256, bool V2IsSplat = false) argument 3754 isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) argument 3797 isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) argument 3829 isMOVLMask(ArrayRef<int> Mask, EVT VT) argument 3853 isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) argument 3913 isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) argument 3944 isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, bool V2IsSplat = false, bool V2IsUndef = false) argument 3968 isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, const X86Subtarget *Subtarget) argument 3991 isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, const X86Subtarget *Subtarget) argument 4014 isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) argument 4034 isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) argument 4103 unsigned Mask = 0; local 4125 unsigned Mask = 0; local 4149 unsigned Mask = 0; local 4232 unsigned Mask = 0; local 4278 ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) argument 4334 ShouldXformToMOVLP(SDNode *V1, SDNode *V2, ArrayRef<int> Mask, EVT VT) argument 4466 NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) argument 4479 SmallVector<int, 8> Mask; local 4490 SmallVector<int, 8> Mask; local 4502 SmallVector<int, 8> Mask; local 4618 getTargetShuffleMask(SDNode *N, MVT VT, SmallVectorImpl<int> &Mask, bool &IsUnary) argument 5050 SmallVector<int, 8> Mask; local 5436 SmallVector<int, 4> Mask; local 6290 SmallVector<int, 16> Mask; local 7057 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, local 7228 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; local 7247 int Mask[2] = { 1, -1 }; local 8444 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1}; local 8647 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, local 8681 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, local 9401 const int Mask[] = { 1, 0, 3, 2 }; local 11618 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); local 11662 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); local 12965 isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT) const argument 16232 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); local 16447 APInt Mask = APInt::getAllOnesValue(InBits); local 16553 SDValue Mask = N1.getOperand(0); local 17240 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); local 17258 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 2265 unsigned Mask = 1; local 2412 unsigned Mask = 1; local
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 660 unsigned Mask = (1 << NumBits) - 1; local
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H A D | ARMISelLowering.cpp | 1708 const uint32_t *Mask; local 3211 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32); local 3430 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, local 4800 SmallVector<int, 8> Mask; local 8300 unsigned Mask = MaskC->getZExtValue(); local 8418 unsigned Mask = (1 << Width)-1; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 57 unsigned Mask:4; // Condition mask for instructions. member in struct:__anon2372::ARMAsmParser::__anon2373 332 unsigned Mask:4; member in struct:__anon2374::ARMOperand::ITMaskOp 1543 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> local 2109 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { argument 5080 unsigned Mask = 8; local 7399 unsigned Mask = MO.getImm(); local 7592 unsigned Mask = 1; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 65 void setITState(char Firstcond, char Mask) { argument 798 unsigned Mask = MI.getOperand(1).getImm(); local
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