1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "llvm/MC/MCDisassembler.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "MCTargetDesc/ARMMCExpr.h" 16#include "llvm/MC/MCContext.h" 17#include "llvm/MC/MCExpr.h" 18#include "llvm/MC/MCFixedLenDisassembler.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/MC/MCInstrDesc.h" 21#include "llvm/MC/MCSubtargetInfo.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/LEB128.h" 25#include "llvm/Support/MemoryObject.h" 26#include "llvm/Support/TargetRegistry.h" 27#include "llvm/Support/raw_ostream.h" 28#include <vector> 29 30using namespace llvm; 31 32typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = CountTrailingZeros_32(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85} 86 87namespace { 88/// ARMDisassembler - ARM disassembler for all ARM platforms. 89class ARMDisassembler : public MCDisassembler { 90public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107}; 108 109/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110class ThumbDisassembler : public MCDisassembler { 111public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133}; 134} 135 136static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149} 150 151 152// Forward declare these because the autogenerated code will reference them. 153// Definitions are further down. 154static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t Address, const void *Decoder); 167static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 176 uint64_t Address, const void *Decoder); 177static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 180 unsigned RegNo, uint64_t Address, 181 const void *Decoder); 182 183static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 196static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 199 uint64_t Address, const void *Decoder); 200static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 201 unsigned Insn, 202 uint64_t Address, 203 const void *Decoder); 204static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 205 uint64_t Address, const void *Decoder); 206static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 207 uint64_t Address, const void *Decoder); 208static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 213static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 214 unsigned Insn, 215 uint64_t Adddress, 216 const void *Decoder); 217static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 236 uint64_t Address, const void *Decoder); 237static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 252 uint64_t Address, const void *Decoder); 253static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 312 const void *Decoder); 313 314 315static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 316 uint64_t Address, const void *Decoder); 317static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 340 uint64_t Address, const void *Decoder); 341static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 342 uint64_t Address, const void *Decoder); 343static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 346 uint64_t Address, const void *Decoder); 347static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 348 uint64_t Address, const void *Decoder); 349static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 350 uint64_t Address, const void *Decoder); 351static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 354 uint64_t Address, const void *Decoder); 355static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 356 uint64_t Address, const void *Decoder); 357static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 358 uint64_t Address, const void *Decoder); 359static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 360 uint64_t Address, const void *Decoder); 361static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 362 uint64_t Address, const void *Decoder); 363static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 364 uint64_t Address, const void *Decoder); 365static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 366 uint64_t Address, const void *Decoder); 367static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 368 uint64_t Address, const void *Decoder); 369static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 370 uint64_t Address, const void *Decoder); 371static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 372 uint64_t Address, const void *Decoder); 373static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 374 uint64_t Address, const void *Decoder); 375static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 376 uint64_t Address, const void *Decoder); 377 378static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382#include "ARMGenDisassemblerTables.inc" 383 384static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 385 return new ARMDisassembler(STI); 386} 387 388static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 389 return new ThumbDisassembler(STI); 390} 391 392DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 393 const MemoryObject &Region, 394 uint64_t Address, 395 raw_ostream &os, 396 raw_ostream &cs) const { 397 CommentStream = &cs; 398 399 uint8_t bytes[4]; 400 401 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 402 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 403 404 // We want to read exactly 4 bytes of data. 405 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 406 Size = 0; 407 return MCDisassembler::Fail; 408 } 409 410 // Encoded as a small-endian 32-bit word in the stream. 411 uint32_t insn = (bytes[3] << 24) | 412 (bytes[2] << 16) | 413 (bytes[1] << 8) | 414 (bytes[0] << 0); 415 416 // Calling the auto-generated decoder function. 417 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 418 Address, this, STI); 419 if (result != MCDisassembler::Fail) { 420 Size = 4; 421 return result; 422 } 423 424 // VFP and NEON instructions, similarly, are shared between ARM 425 // and Thumb modes. 426 MI.clear(); 427 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 428 if (result != MCDisassembler::Fail) { 429 Size = 4; 430 return result; 431 } 432 433 MI.clear(); 434 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 435 this, STI); 436 if (result != MCDisassembler::Fail) { 437 Size = 4; 438 // Add a fake predicate operand, because we share these instruction 439 // definitions with Thumb2 where these instructions are predicable. 440 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 441 return MCDisassembler::Fail; 442 return result; 443 } 444 445 MI.clear(); 446 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 447 this, STI); 448 if (result != MCDisassembler::Fail) { 449 Size = 4; 450 // Add a fake predicate operand, because we share these instruction 451 // definitions with Thumb2 where these instructions are predicable. 452 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 453 return MCDisassembler::Fail; 454 return result; 455 } 456 457 MI.clear(); 458 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 459 this, STI); 460 if (result != MCDisassembler::Fail) { 461 Size = 4; 462 // Add a fake predicate operand, because we share these instruction 463 // definitions with Thumb2 where these instructions are predicable. 464 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 465 return MCDisassembler::Fail; 466 return result; 467 } 468 469 MI.clear(); 470 471 Size = 0; 472 return MCDisassembler::Fail; 473} 474 475namespace llvm { 476extern const MCInstrDesc ARMInsts[]; 477} 478 479/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 480/// immediate Value in the MCInst. The immediate Value has had any PC 481/// adjustment made by the caller. If the instruction is a branch instruction 482/// then isBranch is true, else false. If the getOpInfo() function was set as 483/// part of the setupForSymbolicDisassembly() call then that function is called 484/// to get any symbolic information at the Address for this instruction. If 485/// that returns non-zero then the symbolic information it returns is used to 486/// create an MCExpr and that is added as an operand to the MCInst. If 487/// getOpInfo() returns zero and isBranch is true then a symbol look up for 488/// Value is done and if a symbol is found an MCExpr is created with that, else 489/// an MCExpr with Value is created. This function returns true if it adds an 490/// operand to the MCInst and false otherwise. 491static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 492 bool isBranch, uint64_t InstSize, 493 MCInst &MI, const void *Decoder) { 494 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 495 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 496 struct LLVMOpInfo1 SymbolicOp; 497 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 498 SymbolicOp.Value = Value; 499 void *DisInfo = Dis->getDisInfoBlock(); 500 501 if (!getOpInfo || 502 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 503 // Clear SymbolicOp.Value from above and also all other fields. 504 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 505 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 506 if (!SymbolLookUp) 507 return false; 508 uint64_t ReferenceType; 509 if (isBranch) 510 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 511 else 512 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 513 const char *ReferenceName; 514 uint64_t SymbolValue = 0x00000000ffffffffULL & Value; 515 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType, 516 Address, &ReferenceName); 517 if (Name) { 518 SymbolicOp.AddSymbol.Name = Name; 519 SymbolicOp.AddSymbol.Present = true; 520 } 521 // For branches always create an MCExpr so it gets printed as hex address. 522 else if (isBranch) { 523 SymbolicOp.Value = Value; 524 } 525 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 526 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 527 if (!Name && !isBranch) 528 return false; 529 } 530 531 MCContext *Ctx = Dis->getMCContext(); 532 const MCExpr *Add = NULL; 533 if (SymbolicOp.AddSymbol.Present) { 534 if (SymbolicOp.AddSymbol.Name) { 535 StringRef Name(SymbolicOp.AddSymbol.Name); 536 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 537 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 538 } else { 539 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 540 } 541 } 542 543 const MCExpr *Sub = NULL; 544 if (SymbolicOp.SubtractSymbol.Present) { 545 if (SymbolicOp.SubtractSymbol.Name) { 546 StringRef Name(SymbolicOp.SubtractSymbol.Name); 547 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 548 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 549 } else { 550 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 551 } 552 } 553 554 const MCExpr *Off = NULL; 555 if (SymbolicOp.Value != 0) 556 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 557 558 const MCExpr *Expr; 559 if (Sub) { 560 const MCExpr *LHS; 561 if (Add) 562 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 563 else 564 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 565 if (Off != 0) 566 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 567 else 568 Expr = LHS; 569 } else if (Add) { 570 if (Off != 0) 571 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 572 else 573 Expr = Add; 574 } else { 575 if (Off != 0) 576 Expr = Off; 577 else 578 Expr = MCConstantExpr::Create(0, *Ctx); 579 } 580 581 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 582 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 583 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 584 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 585 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 586 MI.addOperand(MCOperand::CreateExpr(Expr)); 587 else 588 llvm_unreachable("bad SymbolicOp.VariantKind"); 589 590 return true; 591} 592 593/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 594/// referenced by a load instruction with the base register that is the Pc. 595/// These can often be values in a literal pool near the Address of the 596/// instruction. The Address of the instruction and its immediate Value are 597/// used as a possible literal pool entry. The SymbolLookUp call back will 598/// return the name of a symbol referenced by the literal pool's entry if 599/// the referenced address is that of a symbol. Or it will return a pointer to 600/// a literal 'C' string if the referenced address of the literal pool's entry 601/// is an address into a section with 'C' string literals. 602static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 603 const void *Decoder) { 604 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 605 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 606 if (SymbolLookUp) { 607 void *DisInfo = Dis->getDisInfoBlock(); 608 uint64_t ReferenceType; 609 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 610 const char *ReferenceName; 611 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 612 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 613 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 614 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 615 } 616} 617 618// Thumb1 instructions don't have explicit S bits. Rather, they 619// implicitly set CPSR. Since it's not represented in the encoding, the 620// auto-generated decoder won't inject the CPSR operand. We need to fix 621// that as a post-pass. 622static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 623 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 624 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 625 MCInst::iterator I = MI.begin(); 626 for (unsigned i = 0; i < NumOps; ++i, ++I) { 627 if (I == MI.end()) break; 628 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 629 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 630 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 631 return; 632 } 633 } 634 635 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 636} 637 638// Most Thumb instructions don't have explicit predicates in the 639// encoding, but rather get their predicates from IT context. We need 640// to fix up the predicate operands using this context information as a 641// post-pass. 642MCDisassembler::DecodeStatus 643ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 644 MCDisassembler::DecodeStatus S = Success; 645 646 // A few instructions actually have predicates encoded in them. Don't 647 // try to overwrite it if we're seeing one of those. 648 switch (MI.getOpcode()) { 649 case ARM::tBcc: 650 case ARM::t2Bcc: 651 case ARM::tCBZ: 652 case ARM::tCBNZ: 653 case ARM::tCPS: 654 case ARM::t2CPS3p: 655 case ARM::t2CPS2p: 656 case ARM::t2CPS1p: 657 case ARM::tMOVSr: 658 case ARM::tSETEND: 659 // Some instructions (mostly conditional branches) are not 660 // allowed in IT blocks. 661 if (ITBlock.instrInITBlock()) 662 S = SoftFail; 663 else 664 return Success; 665 break; 666 case ARM::tB: 667 case ARM::t2B: 668 case ARM::t2TBB: 669 case ARM::t2TBH: 670 // Some instructions (mostly unconditional branches) can 671 // only appears at the end of, or outside of, an IT. 672 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 673 S = SoftFail; 674 break; 675 default: 676 break; 677 } 678 679 // If we're in an IT block, base the predicate on that. Otherwise, 680 // assume a predicate of AL. 681 unsigned CC; 682 CC = ITBlock.getITCC(); 683 if (CC == 0xF) 684 CC = ARMCC::AL; 685 if (ITBlock.instrInITBlock()) 686 ITBlock.advanceITState(); 687 688 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 689 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 690 MCInst::iterator I = MI.begin(); 691 for (unsigned i = 0; i < NumOps; ++i, ++I) { 692 if (I == MI.end()) break; 693 if (OpInfo[i].isPredicate()) { 694 I = MI.insert(I, MCOperand::CreateImm(CC)); 695 ++I; 696 if (CC == ARMCC::AL) 697 MI.insert(I, MCOperand::CreateReg(0)); 698 else 699 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 700 return S; 701 } 702 } 703 704 I = MI.insert(I, MCOperand::CreateImm(CC)); 705 ++I; 706 if (CC == ARMCC::AL) 707 MI.insert(I, MCOperand::CreateReg(0)); 708 else 709 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 710 711 return S; 712} 713 714// Thumb VFP instructions are a special case. Because we share their 715// encodings between ARM and Thumb modes, and they are predicable in ARM 716// mode, the auto-generated decoder will give them an (incorrect) 717// predicate operand. We need to rewrite these operands based on the IT 718// context as a post-pass. 719void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 720 unsigned CC; 721 CC = ITBlock.getITCC(); 722 if (ITBlock.instrInITBlock()) 723 ITBlock.advanceITState(); 724 725 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 726 MCInst::iterator I = MI.begin(); 727 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 728 for (unsigned i = 0; i < NumOps; ++i, ++I) { 729 if (OpInfo[i].isPredicate() ) { 730 I->setImm(CC); 731 ++I; 732 if (CC == ARMCC::AL) 733 I->setReg(0); 734 else 735 I->setReg(ARM::CPSR); 736 return; 737 } 738 } 739} 740 741DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 742 const MemoryObject &Region, 743 uint64_t Address, 744 raw_ostream &os, 745 raw_ostream &cs) const { 746 CommentStream = &cs; 747 748 uint8_t bytes[4]; 749 750 assert((STI.getFeatureBits() & ARM::ModeThumb) && 751 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 752 753 // We want to read exactly 2 bytes of data. 754 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 755 Size = 0; 756 return MCDisassembler::Fail; 757 } 758 759 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 760 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 761 Address, this, STI); 762 if (result != MCDisassembler::Fail) { 763 Size = 2; 764 Check(result, AddThumbPredicate(MI)); 765 return result; 766 } 767 768 MI.clear(); 769 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 770 Address, this, STI); 771 if (result) { 772 Size = 2; 773 bool InITBlock = ITBlock.instrInITBlock(); 774 Check(result, AddThumbPredicate(MI)); 775 AddThumb1SBit(MI, InITBlock); 776 return result; 777 } 778 779 MI.clear(); 780 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 781 Address, this, STI); 782 if (result != MCDisassembler::Fail) { 783 Size = 2; 784 785 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 786 // the Thumb predicate. 787 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 788 result = MCDisassembler::SoftFail; 789 790 Check(result, AddThumbPredicate(MI)); 791 792 // If we find an IT instruction, we need to parse its condition 793 // code and mask operands so that we can apply them correctly 794 // to the subsequent instructions. 795 if (MI.getOpcode() == ARM::t2IT) { 796 797 unsigned Firstcond = MI.getOperand(0).getImm(); 798 unsigned Mask = MI.getOperand(1).getImm(); 799 ITBlock.setITState(Firstcond, Mask); 800 } 801 802 return result; 803 } 804 805 // We want to read exactly 4 bytes of data. 806 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 807 Size = 0; 808 return MCDisassembler::Fail; 809 } 810 811 uint32_t insn32 = (bytes[3] << 8) | 812 (bytes[2] << 0) | 813 (bytes[1] << 24) | 814 (bytes[0] << 16); 815 MI.clear(); 816 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 817 this, STI); 818 if (result != MCDisassembler::Fail) { 819 Size = 4; 820 bool InITBlock = ITBlock.instrInITBlock(); 821 Check(result, AddThumbPredicate(MI)); 822 AddThumb1SBit(MI, InITBlock); 823 return result; 824 } 825 826 MI.clear(); 827 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 828 this, STI); 829 if (result != MCDisassembler::Fail) { 830 Size = 4; 831 Check(result, AddThumbPredicate(MI)); 832 return result; 833 } 834 835 MI.clear(); 836 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 837 if (result != MCDisassembler::Fail) { 838 Size = 4; 839 UpdateThumbVFPPredicate(MI); 840 return result; 841 } 842 843 MI.clear(); 844 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 845 this, STI); 846 if (result != MCDisassembler::Fail) { 847 Size = 4; 848 Check(result, AddThumbPredicate(MI)); 849 return result; 850 } 851 852 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 853 MI.clear(); 854 uint32_t NEONLdStInsn = insn32; 855 NEONLdStInsn &= 0xF0FFFFFF; 856 NEONLdStInsn |= 0x04000000; 857 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 858 Address, this, STI); 859 if (result != MCDisassembler::Fail) { 860 Size = 4; 861 Check(result, AddThumbPredicate(MI)); 862 return result; 863 } 864 } 865 866 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 867 MI.clear(); 868 uint32_t NEONDataInsn = insn32; 869 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 870 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 871 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 872 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 873 Address, this, STI); 874 if (result != MCDisassembler::Fail) { 875 Size = 4; 876 Check(result, AddThumbPredicate(MI)); 877 return result; 878 } 879 } 880 881 Size = 0; 882 return MCDisassembler::Fail; 883} 884 885 886extern "C" void LLVMInitializeARMDisassembler() { 887 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 888 createARMDisassembler); 889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 890 createThumbDisassembler); 891} 892 893static const uint16_t GPRDecoderTable[] = { 894 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 895 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 896 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 897 ARM::R12, ARM::SP, ARM::LR, ARM::PC 898}; 899 900static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 if (RegNo > 15) 903 return MCDisassembler::Fail; 904 905 unsigned Register = GPRDecoderTable[RegNo]; 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908} 909 910static DecodeStatus 911DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 DecodeStatus S = MCDisassembler::Success; 914 915 if (RegNo == 15) 916 S = MCDisassembler::SoftFail; 917 918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 919 920 return S; 921} 922 923static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 if (RegNo > 7) 926 return MCDisassembler::Fail; 927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 928} 929 930static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 unsigned Register = 0; 933 switch (RegNo) { 934 case 0: 935 Register = ARM::R0; 936 break; 937 case 1: 938 Register = ARM::R1; 939 break; 940 case 2: 941 Register = ARM::R2; 942 break; 943 case 3: 944 Register = ARM::R3; 945 break; 946 case 9: 947 Register = ARM::R9; 948 break; 949 case 12: 950 Register = ARM::R12; 951 break; 952 default: 953 return MCDisassembler::Fail; 954 } 955 956 Inst.addOperand(MCOperand::CreateReg(Register)); 957 return MCDisassembler::Success; 958} 959 960static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 961 uint64_t Address, const void *Decoder) { 962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 964} 965 966static const uint16_t SPRDecoderTable[] = { 967 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 968 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 969 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 970 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 971 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 972 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 973 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 974 ARM::S28, ARM::S29, ARM::S30, ARM::S31 975}; 976 977static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 978 uint64_t Address, const void *Decoder) { 979 if (RegNo > 31) 980 return MCDisassembler::Fail; 981 982 unsigned Register = SPRDecoderTable[RegNo]; 983 Inst.addOperand(MCOperand::CreateReg(Register)); 984 return MCDisassembler::Success; 985} 986 987static const uint16_t DPRDecoderTable[] = { 988 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 989 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 990 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 991 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 992 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 993 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 994 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 995 ARM::D28, ARM::D29, ARM::D30, ARM::D31 996}; 997 998static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 999 uint64_t Address, const void *Decoder) { 1000 if (RegNo > 31) 1001 return MCDisassembler::Fail; 1002 1003 unsigned Register = DPRDecoderTable[RegNo]; 1004 Inst.addOperand(MCOperand::CreateReg(Register)); 1005 return MCDisassembler::Success; 1006} 1007 1008static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1009 uint64_t Address, const void *Decoder) { 1010 if (RegNo > 7) 1011 return MCDisassembler::Fail; 1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1013} 1014 1015static DecodeStatus 1016DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1017 uint64_t Address, const void *Decoder) { 1018 if (RegNo > 15) 1019 return MCDisassembler::Fail; 1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1021} 1022 1023static const uint16_t QPRDecoderTable[] = { 1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1028}; 1029 1030 1031static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1032 uint64_t Address, const void *Decoder) { 1033 if (RegNo > 31) 1034 return MCDisassembler::Fail; 1035 RegNo >>= 1; 1036 1037 unsigned Register = QPRDecoderTable[RegNo]; 1038 Inst.addOperand(MCOperand::CreateReg(Register)); 1039 return MCDisassembler::Success; 1040} 1041 1042static const uint16_t DPairDecoderTable[] = { 1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1048 ARM::Q15 1049}; 1050 1051static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1052 uint64_t Address, const void *Decoder) { 1053 if (RegNo > 30) 1054 return MCDisassembler::Fail; 1055 1056 unsigned Register = DPairDecoderTable[RegNo]; 1057 Inst.addOperand(MCOperand::CreateReg(Register)); 1058 return MCDisassembler::Success; 1059} 1060 1061static const uint16_t DPairSpacedDecoderTable[] = { 1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1069 ARM::D28_D30, ARM::D29_D31 1070}; 1071 1072static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1073 unsigned RegNo, 1074 uint64_t Address, 1075 const void *Decoder) { 1076 if (RegNo > 29) 1077 return MCDisassembler::Fail; 1078 1079 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1080 Inst.addOperand(MCOperand::CreateReg(Register)); 1081 return MCDisassembler::Success; 1082} 1083 1084static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1085 uint64_t Address, const void *Decoder) { 1086 if (Val == 0xF) return MCDisassembler::Fail; 1087 // AL predicate is not allowed on Thumb1 branches. 1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1089 return MCDisassembler::Fail; 1090 Inst.addOperand(MCOperand::CreateImm(Val)); 1091 if (Val == ARMCC::AL) { 1092 Inst.addOperand(MCOperand::CreateReg(0)); 1093 } else 1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1095 return MCDisassembler::Success; 1096} 1097 1098static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val) 1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1102 else 1103 Inst.addOperand(MCOperand::CreateReg(0)); 1104 return MCDisassembler::Success; 1105} 1106 1107static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1108 uint64_t Address, const void *Decoder) { 1109 uint32_t imm = Val & 0xFF; 1110 uint32_t rot = (Val & 0xF00) >> 7; 1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1112 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1113 return MCDisassembler::Success; 1114} 1115 1116static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1117 uint64_t Address, const void *Decoder) { 1118 DecodeStatus S = MCDisassembler::Success; 1119 1120 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1121 unsigned type = fieldFromInstruction(Val, 5, 2); 1122 unsigned imm = fieldFromInstruction(Val, 7, 5); 1123 1124 // Register-immediate 1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1126 return MCDisassembler::Fail; 1127 1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1129 switch (type) { 1130 case 0: 1131 Shift = ARM_AM::lsl; 1132 break; 1133 case 1: 1134 Shift = ARM_AM::lsr; 1135 break; 1136 case 2: 1137 Shift = ARM_AM::asr; 1138 break; 1139 case 3: 1140 Shift = ARM_AM::ror; 1141 break; 1142 } 1143 1144 if (Shift == ARM_AM::ror && imm == 0) 1145 Shift = ARM_AM::rrx; 1146 1147 unsigned Op = Shift | (imm << 3); 1148 Inst.addOperand(MCOperand::CreateImm(Op)); 1149 1150 return S; 1151} 1152 1153static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1154 uint64_t Address, const void *Decoder) { 1155 DecodeStatus S = MCDisassembler::Success; 1156 1157 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1158 unsigned type = fieldFromInstruction(Val, 5, 2); 1159 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1160 1161 // Register-register 1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1165 return MCDisassembler::Fail; 1166 1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1168 switch (type) { 1169 case 0: 1170 Shift = ARM_AM::lsl; 1171 break; 1172 case 1: 1173 Shift = ARM_AM::lsr; 1174 break; 1175 case 2: 1176 Shift = ARM_AM::asr; 1177 break; 1178 case 3: 1179 Shift = ARM_AM::ror; 1180 break; 1181 } 1182 1183 Inst.addOperand(MCOperand::CreateImm(Shift)); 1184 1185 return S; 1186} 1187 1188static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1189 uint64_t Address, const void *Decoder) { 1190 DecodeStatus S = MCDisassembler::Success; 1191 1192 bool writebackLoad = false; 1193 unsigned writebackReg = 0; 1194 switch (Inst.getOpcode()) { 1195 default: 1196 break; 1197 case ARM::LDMIA_UPD: 1198 case ARM::LDMDB_UPD: 1199 case ARM::LDMIB_UPD: 1200 case ARM::LDMDA_UPD: 1201 case ARM::t2LDMIA_UPD: 1202 case ARM::t2LDMDB_UPD: 1203 writebackLoad = true; 1204 writebackReg = Inst.getOperand(0).getReg(); 1205 break; 1206 } 1207 1208 // Empty register lists are not allowed. 1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1210 for (unsigned i = 0; i < 16; ++i) { 1211 if (Val & (1 << i)) { 1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1213 return MCDisassembler::Fail; 1214 // Writeback not allowed if Rn is in the target list. 1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1216 Check(S, MCDisassembler::SoftFail); 1217 } 1218 } 1219 1220 return S; 1221} 1222 1223static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1228 unsigned regs = fieldFromInstruction(Val, 0, 8); 1229 1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1231 return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < (regs - 1); ++i) { 1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1234 return MCDisassembler::Fail; 1235 } 1236 1237 return S; 1238} 1239 1240static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1241 uint64_t Address, const void *Decoder) { 1242 DecodeStatus S = MCDisassembler::Success; 1243 1244 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1245 unsigned regs = fieldFromInstruction(Val, 0, 8); 1246 1247 regs = regs >> 1; 1248 1249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 for (unsigned i = 0; i < (regs - 1); ++i) { 1252 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1253 return MCDisassembler::Fail; 1254 } 1255 1256 return S; 1257} 1258 1259static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1260 uint64_t Address, const void *Decoder) { 1261 // This operand encodes a mask of contiguous zeros between a specified MSB 1262 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1263 // the mask of all bits LSB-and-lower, and then xor them to create 1264 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1265 // create the final mask. 1266 unsigned msb = fieldFromInstruction(Val, 5, 5); 1267 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1268 1269 DecodeStatus S = MCDisassembler::Success; 1270 if (lsb > msb) { 1271 Check(S, MCDisassembler::SoftFail); 1272 // The check above will cause the warning for the "potentially undefined 1273 // instruction encoding" but we can't build a bad MCOperand value here 1274 // with a lsb > msb or else printing the MCInst will cause a crash. 1275 lsb = msb; 1276 } 1277 1278 uint32_t msb_mask = 0xFFFFFFFF; 1279 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1280 uint32_t lsb_mask = (1U << lsb) - 1; 1281 1282 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1283 return S; 1284} 1285 1286static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1287 uint64_t Address, const void *Decoder) { 1288 DecodeStatus S = MCDisassembler::Success; 1289 1290 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1291 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1292 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1293 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1294 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1295 unsigned U = fieldFromInstruction(Insn, 23, 1); 1296 1297 switch (Inst.getOpcode()) { 1298 case ARM::LDC_OFFSET: 1299 case ARM::LDC_PRE: 1300 case ARM::LDC_POST: 1301 case ARM::LDC_OPTION: 1302 case ARM::LDCL_OFFSET: 1303 case ARM::LDCL_PRE: 1304 case ARM::LDCL_POST: 1305 case ARM::LDCL_OPTION: 1306 case ARM::STC_OFFSET: 1307 case ARM::STC_PRE: 1308 case ARM::STC_POST: 1309 case ARM::STC_OPTION: 1310 case ARM::STCL_OFFSET: 1311 case ARM::STCL_PRE: 1312 case ARM::STCL_POST: 1313 case ARM::STCL_OPTION: 1314 case ARM::t2LDC_OFFSET: 1315 case ARM::t2LDC_PRE: 1316 case ARM::t2LDC_POST: 1317 case ARM::t2LDC_OPTION: 1318 case ARM::t2LDCL_OFFSET: 1319 case ARM::t2LDCL_PRE: 1320 case ARM::t2LDCL_POST: 1321 case ARM::t2LDCL_OPTION: 1322 case ARM::t2STC_OFFSET: 1323 case ARM::t2STC_PRE: 1324 case ARM::t2STC_POST: 1325 case ARM::t2STC_OPTION: 1326 case ARM::t2STCL_OFFSET: 1327 case ARM::t2STCL_PRE: 1328 case ARM::t2STCL_POST: 1329 case ARM::t2STCL_OPTION: 1330 if (coproc == 0xA || coproc == 0xB) 1331 return MCDisassembler::Fail; 1332 break; 1333 default: 1334 break; 1335 } 1336 1337 Inst.addOperand(MCOperand::CreateImm(coproc)); 1338 Inst.addOperand(MCOperand::CreateImm(CRd)); 1339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1340 return MCDisassembler::Fail; 1341 1342 switch (Inst.getOpcode()) { 1343 case ARM::t2LDC2_OFFSET: 1344 case ARM::t2LDC2L_OFFSET: 1345 case ARM::t2LDC2_PRE: 1346 case ARM::t2LDC2L_PRE: 1347 case ARM::t2STC2_OFFSET: 1348 case ARM::t2STC2L_OFFSET: 1349 case ARM::t2STC2_PRE: 1350 case ARM::t2STC2L_PRE: 1351 case ARM::LDC2_OFFSET: 1352 case ARM::LDC2L_OFFSET: 1353 case ARM::LDC2_PRE: 1354 case ARM::LDC2L_PRE: 1355 case ARM::STC2_OFFSET: 1356 case ARM::STC2L_OFFSET: 1357 case ARM::STC2_PRE: 1358 case ARM::STC2L_PRE: 1359 case ARM::t2LDC_OFFSET: 1360 case ARM::t2LDCL_OFFSET: 1361 case ARM::t2LDC_PRE: 1362 case ARM::t2LDCL_PRE: 1363 case ARM::t2STC_OFFSET: 1364 case ARM::t2STCL_OFFSET: 1365 case ARM::t2STC_PRE: 1366 case ARM::t2STCL_PRE: 1367 case ARM::LDC_OFFSET: 1368 case ARM::LDCL_OFFSET: 1369 case ARM::LDC_PRE: 1370 case ARM::LDCL_PRE: 1371 case ARM::STC_OFFSET: 1372 case ARM::STCL_OFFSET: 1373 case ARM::STC_PRE: 1374 case ARM::STCL_PRE: 1375 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1376 Inst.addOperand(MCOperand::CreateImm(imm)); 1377 break; 1378 case ARM::t2LDC2_POST: 1379 case ARM::t2LDC2L_POST: 1380 case ARM::t2STC2_POST: 1381 case ARM::t2STC2L_POST: 1382 case ARM::LDC2_POST: 1383 case ARM::LDC2L_POST: 1384 case ARM::STC2_POST: 1385 case ARM::STC2L_POST: 1386 case ARM::t2LDC_POST: 1387 case ARM::t2LDCL_POST: 1388 case ARM::t2STC_POST: 1389 case ARM::t2STCL_POST: 1390 case ARM::LDC_POST: 1391 case ARM::LDCL_POST: 1392 case ARM::STC_POST: 1393 case ARM::STCL_POST: 1394 imm |= U << 8; 1395 // fall through. 1396 default: 1397 // The 'option' variant doesn't encode 'U' in the immediate since 1398 // the immediate is unsigned [0,255]. 1399 Inst.addOperand(MCOperand::CreateImm(imm)); 1400 break; 1401 } 1402 1403 switch (Inst.getOpcode()) { 1404 case ARM::LDC_OFFSET: 1405 case ARM::LDC_PRE: 1406 case ARM::LDC_POST: 1407 case ARM::LDC_OPTION: 1408 case ARM::LDCL_OFFSET: 1409 case ARM::LDCL_PRE: 1410 case ARM::LDCL_POST: 1411 case ARM::LDCL_OPTION: 1412 case ARM::STC_OFFSET: 1413 case ARM::STC_PRE: 1414 case ARM::STC_POST: 1415 case ARM::STC_OPTION: 1416 case ARM::STCL_OFFSET: 1417 case ARM::STCL_PRE: 1418 case ARM::STCL_POST: 1419 case ARM::STCL_OPTION: 1420 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1421 return MCDisassembler::Fail; 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return S; 1428} 1429 1430static DecodeStatus 1431DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1432 uint64_t Address, const void *Decoder) { 1433 DecodeStatus S = MCDisassembler::Success; 1434 1435 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1436 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1437 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1438 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1439 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1440 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1441 unsigned P = fieldFromInstruction(Insn, 24, 1); 1442 unsigned W = fieldFromInstruction(Insn, 21, 1); 1443 1444 // On stores, the writeback operand precedes Rt. 1445 switch (Inst.getOpcode()) { 1446 case ARM::STR_POST_IMM: 1447 case ARM::STR_POST_REG: 1448 case ARM::STRB_POST_IMM: 1449 case ARM::STRB_POST_REG: 1450 case ARM::STRT_POST_REG: 1451 case ARM::STRT_POST_IMM: 1452 case ARM::STRBT_POST_REG: 1453 case ARM::STRBT_POST_IMM: 1454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1455 return MCDisassembler::Fail; 1456 break; 1457 default: 1458 break; 1459 } 1460 1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1462 return MCDisassembler::Fail; 1463 1464 // On loads, the writeback operand comes after Rt. 1465 switch (Inst.getOpcode()) { 1466 case ARM::LDR_POST_IMM: 1467 case ARM::LDR_POST_REG: 1468 case ARM::LDRB_POST_IMM: 1469 case ARM::LDRB_POST_REG: 1470 case ARM::LDRBT_POST_REG: 1471 case ARM::LDRBT_POST_IMM: 1472 case ARM::LDRT_POST_REG: 1473 case ARM::LDRT_POST_IMM: 1474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1475 return MCDisassembler::Fail; 1476 break; 1477 default: 1478 break; 1479 } 1480 1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 1484 ARM_AM::AddrOpc Op = ARM_AM::add; 1485 if (!fieldFromInstruction(Insn, 23, 1)) 1486 Op = ARM_AM::sub; 1487 1488 bool writeback = (P == 0) || (W == 1); 1489 unsigned idx_mode = 0; 1490 if (P && writeback) 1491 idx_mode = ARMII::IndexModePre; 1492 else if (!P && writeback) 1493 idx_mode = ARMII::IndexModePost; 1494 1495 if (writeback && (Rn == 15 || Rn == Rt)) 1496 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1497 1498 if (reg) { 1499 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1500 return MCDisassembler::Fail; 1501 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1502 switch( fieldFromInstruction(Insn, 5, 2)) { 1503 case 0: 1504 Opc = ARM_AM::lsl; 1505 break; 1506 case 1: 1507 Opc = ARM_AM::lsr; 1508 break; 1509 case 2: 1510 Opc = ARM_AM::asr; 1511 break; 1512 case 3: 1513 Opc = ARM_AM::ror; 1514 break; 1515 default: 1516 return MCDisassembler::Fail; 1517 } 1518 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1519 if (Opc == ARM_AM::ror && amt == 0) 1520 Opc = ARM_AM::rrx; 1521 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1522 1523 Inst.addOperand(MCOperand::CreateImm(imm)); 1524 } else { 1525 Inst.addOperand(MCOperand::CreateReg(0)); 1526 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1527 Inst.addOperand(MCOperand::CreateImm(tmp)); 1528 } 1529 1530 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1531 return MCDisassembler::Fail; 1532 1533 return S; 1534} 1535 1536static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1537 uint64_t Address, const void *Decoder) { 1538 DecodeStatus S = MCDisassembler::Success; 1539 1540 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1541 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1542 unsigned type = fieldFromInstruction(Val, 5, 2); 1543 unsigned imm = fieldFromInstruction(Val, 7, 5); 1544 unsigned U = fieldFromInstruction(Val, 12, 1); 1545 1546 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1547 switch (type) { 1548 case 0: 1549 ShOp = ARM_AM::lsl; 1550 break; 1551 case 1: 1552 ShOp = ARM_AM::lsr; 1553 break; 1554 case 2: 1555 ShOp = ARM_AM::asr; 1556 break; 1557 case 3: 1558 ShOp = ARM_AM::ror; 1559 break; 1560 } 1561 1562 if (ShOp == ARM_AM::ror && imm == 0) 1563 ShOp = ARM_AM::rrx; 1564 1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1566 return MCDisassembler::Fail; 1567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1568 return MCDisassembler::Fail; 1569 unsigned shift; 1570 if (U) 1571 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1572 else 1573 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1574 Inst.addOperand(MCOperand::CreateImm(shift)); 1575 1576 return S; 1577} 1578 1579static DecodeStatus 1580DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1581 uint64_t Address, const void *Decoder) { 1582 DecodeStatus S = MCDisassembler::Success; 1583 1584 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1585 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1586 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1587 unsigned type = fieldFromInstruction(Insn, 22, 1); 1588 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1589 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1590 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1591 unsigned W = fieldFromInstruction(Insn, 21, 1); 1592 unsigned P = fieldFromInstruction(Insn, 24, 1); 1593 unsigned Rt2 = Rt + 1; 1594 1595 bool writeback = (W == 1) | (P == 0); 1596 1597 // For {LD,ST}RD, Rt must be even, else undefined. 1598 switch (Inst.getOpcode()) { 1599 case ARM::STRD: 1600 case ARM::STRD_PRE: 1601 case ARM::STRD_POST: 1602 case ARM::LDRD: 1603 case ARM::LDRD_PRE: 1604 case ARM::LDRD_POST: 1605 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1606 break; 1607 default: 1608 break; 1609 } 1610 switch (Inst.getOpcode()) { 1611 case ARM::STRD: 1612 case ARM::STRD_PRE: 1613 case ARM::STRD_POST: 1614 if (P == 0 && W == 1) 1615 S = MCDisassembler::SoftFail; 1616 1617 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1618 S = MCDisassembler::SoftFail; 1619 if (type && Rm == 15) 1620 S = MCDisassembler::SoftFail; 1621 if (Rt2 == 15) 1622 S = MCDisassembler::SoftFail; 1623 if (!type && fieldFromInstruction(Insn, 8, 4)) 1624 S = MCDisassembler::SoftFail; 1625 break; 1626 case ARM::STRH: 1627 case ARM::STRH_PRE: 1628 case ARM::STRH_POST: 1629 if (Rt == 15) 1630 S = MCDisassembler::SoftFail; 1631 if (writeback && (Rn == 15 || Rn == Rt)) 1632 S = MCDisassembler::SoftFail; 1633 if (!type && Rm == 15) 1634 S = MCDisassembler::SoftFail; 1635 break; 1636 case ARM::LDRD: 1637 case ARM::LDRD_PRE: 1638 case ARM::LDRD_POST: 1639 if (type && Rn == 15){ 1640 if (Rt2 == 15) 1641 S = MCDisassembler::SoftFail; 1642 break; 1643 } 1644 if (P == 0 && W == 1) 1645 S = MCDisassembler::SoftFail; 1646 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1647 S = MCDisassembler::SoftFail; 1648 if (!type && writeback && Rn == 15) 1649 S = MCDisassembler::SoftFail; 1650 if (writeback && (Rn == Rt || Rn == Rt2)) 1651 S = MCDisassembler::SoftFail; 1652 break; 1653 case ARM::LDRH: 1654 case ARM::LDRH_PRE: 1655 case ARM::LDRH_POST: 1656 if (type && Rn == 15){ 1657 if (Rt == 15) 1658 S = MCDisassembler::SoftFail; 1659 break; 1660 } 1661 if (Rt == 15) 1662 S = MCDisassembler::SoftFail; 1663 if (!type && Rm == 15) 1664 S = MCDisassembler::SoftFail; 1665 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1666 S = MCDisassembler::SoftFail; 1667 break; 1668 case ARM::LDRSH: 1669 case ARM::LDRSH_PRE: 1670 case ARM::LDRSH_POST: 1671 case ARM::LDRSB: 1672 case ARM::LDRSB_PRE: 1673 case ARM::LDRSB_POST: 1674 if (type && Rn == 15){ 1675 if (Rt == 15) 1676 S = MCDisassembler::SoftFail; 1677 break; 1678 } 1679 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1680 S = MCDisassembler::SoftFail; 1681 if (!type && (Rt == 15 || Rm == 15)) 1682 S = MCDisassembler::SoftFail; 1683 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1684 S = MCDisassembler::SoftFail; 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 if (writeback) { // Writeback 1691 if (P) 1692 U |= ARMII::IndexModePre << 9; 1693 else 1694 U |= ARMII::IndexModePost << 9; 1695 1696 // On stores, the writeback operand precedes Rt. 1697 switch (Inst.getOpcode()) { 1698 case ARM::STRD: 1699 case ARM::STRD_PRE: 1700 case ARM::STRD_POST: 1701 case ARM::STRH: 1702 case ARM::STRH_PRE: 1703 case ARM::STRH_POST: 1704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1705 return MCDisassembler::Fail; 1706 break; 1707 default: 1708 break; 1709 } 1710 } 1711 1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1713 return MCDisassembler::Fail; 1714 switch (Inst.getOpcode()) { 1715 case ARM::STRD: 1716 case ARM::STRD_PRE: 1717 case ARM::STRD_POST: 1718 case ARM::LDRD: 1719 case ARM::LDRD_PRE: 1720 case ARM::LDRD_POST: 1721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1722 return MCDisassembler::Fail; 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 if (writeback) { 1729 // On loads, the writeback operand comes after Rt. 1730 switch (Inst.getOpcode()) { 1731 case ARM::LDRD: 1732 case ARM::LDRD_PRE: 1733 case ARM::LDRD_POST: 1734 case ARM::LDRH: 1735 case ARM::LDRH_PRE: 1736 case ARM::LDRH_POST: 1737 case ARM::LDRSH: 1738 case ARM::LDRSH_PRE: 1739 case ARM::LDRSH_POST: 1740 case ARM::LDRSB: 1741 case ARM::LDRSB_PRE: 1742 case ARM::LDRSB_POST: 1743 case ARM::LDRHTr: 1744 case ARM::LDRSBTr: 1745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1746 return MCDisassembler::Fail; 1747 break; 1748 default: 1749 break; 1750 } 1751 } 1752 1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1754 return MCDisassembler::Fail; 1755 1756 if (type) { 1757 Inst.addOperand(MCOperand::CreateReg(0)); 1758 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1759 } else { 1760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1761 return MCDisassembler::Fail; 1762 Inst.addOperand(MCOperand::CreateImm(U)); 1763 } 1764 1765 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1766 return MCDisassembler::Fail; 1767 1768 return S; 1769} 1770 1771static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1772 uint64_t Address, const void *Decoder) { 1773 DecodeStatus S = MCDisassembler::Success; 1774 1775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1776 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1777 1778 switch (mode) { 1779 case 0: 1780 mode = ARM_AM::da; 1781 break; 1782 case 1: 1783 mode = ARM_AM::ia; 1784 break; 1785 case 2: 1786 mode = ARM_AM::db; 1787 break; 1788 case 3: 1789 mode = ARM_AM::ib; 1790 break; 1791 } 1792 1793 Inst.addOperand(MCOperand::CreateImm(mode)); 1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1795 return MCDisassembler::Fail; 1796 1797 return S; 1798} 1799 1800static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1801 unsigned Insn, 1802 uint64_t Address, const void *Decoder) { 1803 DecodeStatus S = MCDisassembler::Success; 1804 1805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1806 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1807 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1808 1809 if (pred == 0xF) { 1810 switch (Inst.getOpcode()) { 1811 case ARM::LDMDA: 1812 Inst.setOpcode(ARM::RFEDA); 1813 break; 1814 case ARM::LDMDA_UPD: 1815 Inst.setOpcode(ARM::RFEDA_UPD); 1816 break; 1817 case ARM::LDMDB: 1818 Inst.setOpcode(ARM::RFEDB); 1819 break; 1820 case ARM::LDMDB_UPD: 1821 Inst.setOpcode(ARM::RFEDB_UPD); 1822 break; 1823 case ARM::LDMIA: 1824 Inst.setOpcode(ARM::RFEIA); 1825 break; 1826 case ARM::LDMIA_UPD: 1827 Inst.setOpcode(ARM::RFEIA_UPD); 1828 break; 1829 case ARM::LDMIB: 1830 Inst.setOpcode(ARM::RFEIB); 1831 break; 1832 case ARM::LDMIB_UPD: 1833 Inst.setOpcode(ARM::RFEIB_UPD); 1834 break; 1835 case ARM::STMDA: 1836 Inst.setOpcode(ARM::SRSDA); 1837 break; 1838 case ARM::STMDA_UPD: 1839 Inst.setOpcode(ARM::SRSDA_UPD); 1840 break; 1841 case ARM::STMDB: 1842 Inst.setOpcode(ARM::SRSDB); 1843 break; 1844 case ARM::STMDB_UPD: 1845 Inst.setOpcode(ARM::SRSDB_UPD); 1846 break; 1847 case ARM::STMIA: 1848 Inst.setOpcode(ARM::SRSIA); 1849 break; 1850 case ARM::STMIA_UPD: 1851 Inst.setOpcode(ARM::SRSIA_UPD); 1852 break; 1853 case ARM::STMIB: 1854 Inst.setOpcode(ARM::SRSIB); 1855 break; 1856 case ARM::STMIB_UPD: 1857 Inst.setOpcode(ARM::SRSIB_UPD); 1858 break; 1859 default: 1860 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1861 } 1862 1863 // For stores (which become SRS's, the only operand is the mode. 1864 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1865 Inst.addOperand( 1866 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1867 return S; 1868 } 1869 1870 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1871 } 1872 1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1874 return MCDisassembler::Fail; 1875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1876 return MCDisassembler::Fail; // Tied 1877 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1878 return MCDisassembler::Fail; 1879 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 1882 return S; 1883} 1884 1885static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1886 uint64_t Address, const void *Decoder) { 1887 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1888 unsigned M = fieldFromInstruction(Insn, 17, 1); 1889 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1890 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1891 1892 DecodeStatus S = MCDisassembler::Success; 1893 1894 // imod == '01' --> UNPREDICTABLE 1895 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1896 // return failure here. The '01' imod value is unprintable, so there's 1897 // nothing useful we could do even if we returned UNPREDICTABLE. 1898 1899 if (imod == 1) return MCDisassembler::Fail; 1900 1901 if (imod && M) { 1902 Inst.setOpcode(ARM::CPS3p); 1903 Inst.addOperand(MCOperand::CreateImm(imod)); 1904 Inst.addOperand(MCOperand::CreateImm(iflags)); 1905 Inst.addOperand(MCOperand::CreateImm(mode)); 1906 } else if (imod && !M) { 1907 Inst.setOpcode(ARM::CPS2p); 1908 Inst.addOperand(MCOperand::CreateImm(imod)); 1909 Inst.addOperand(MCOperand::CreateImm(iflags)); 1910 if (mode) S = MCDisassembler::SoftFail; 1911 } else if (!imod && M) { 1912 Inst.setOpcode(ARM::CPS1p); 1913 Inst.addOperand(MCOperand::CreateImm(mode)); 1914 if (iflags) S = MCDisassembler::SoftFail; 1915 } else { 1916 // imod == '00' && M == '0' --> UNPREDICTABLE 1917 Inst.setOpcode(ARM::CPS1p); 1918 Inst.addOperand(MCOperand::CreateImm(mode)); 1919 S = MCDisassembler::SoftFail; 1920 } 1921 1922 return S; 1923} 1924 1925static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1926 uint64_t Address, const void *Decoder) { 1927 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1928 unsigned M = fieldFromInstruction(Insn, 8, 1); 1929 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1930 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1931 1932 DecodeStatus S = MCDisassembler::Success; 1933 1934 // imod == '01' --> UNPREDICTABLE 1935 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1936 // return failure here. The '01' imod value is unprintable, so there's 1937 // nothing useful we could do even if we returned UNPREDICTABLE. 1938 1939 if (imod == 1) return MCDisassembler::Fail; 1940 1941 if (imod && M) { 1942 Inst.setOpcode(ARM::t2CPS3p); 1943 Inst.addOperand(MCOperand::CreateImm(imod)); 1944 Inst.addOperand(MCOperand::CreateImm(iflags)); 1945 Inst.addOperand(MCOperand::CreateImm(mode)); 1946 } else if (imod && !M) { 1947 Inst.setOpcode(ARM::t2CPS2p); 1948 Inst.addOperand(MCOperand::CreateImm(imod)); 1949 Inst.addOperand(MCOperand::CreateImm(iflags)); 1950 if (mode) S = MCDisassembler::SoftFail; 1951 } else if (!imod && M) { 1952 Inst.setOpcode(ARM::t2CPS1p); 1953 Inst.addOperand(MCOperand::CreateImm(mode)); 1954 if (iflags) S = MCDisassembler::SoftFail; 1955 } else { 1956 // imod == '00' && M == '0' --> this is a HINT instruction 1957 int imm = fieldFromInstruction(Insn, 0, 8); 1958 // HINT are defined only for immediate in [0..4] 1959 if(imm > 4) return MCDisassembler::Fail; 1960 Inst.setOpcode(ARM::t2HINT); 1961 Inst.addOperand(MCOperand::CreateImm(imm)); 1962 } 1963 1964 return S; 1965} 1966 1967static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1968 uint64_t Address, const void *Decoder) { 1969 DecodeStatus S = MCDisassembler::Success; 1970 1971 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1972 unsigned imm = 0; 1973 1974 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1975 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1976 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1977 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1978 1979 if (Inst.getOpcode() == ARM::t2MOVTi16) 1980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1983 return MCDisassembler::Fail; 1984 1985 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1986 Inst.addOperand(MCOperand::CreateImm(imm)); 1987 1988 return S; 1989} 1990 1991static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1992 uint64_t Address, const void *Decoder) { 1993 DecodeStatus S = MCDisassembler::Success; 1994 1995 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1996 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1997 unsigned imm = 0; 1998 1999 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2000 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2001 2002 if (Inst.getOpcode() == ARM::MOVTi16) 2003 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2004 return MCDisassembler::Fail; 2005 2006 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2007 return MCDisassembler::Fail; 2008 2009 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2010 Inst.addOperand(MCOperand::CreateImm(imm)); 2011 2012 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2013 return MCDisassembler::Fail; 2014 2015 return S; 2016} 2017 2018static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2019 uint64_t Address, const void *Decoder) { 2020 DecodeStatus S = MCDisassembler::Success; 2021 2022 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2023 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2024 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2025 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2026 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2027 2028 if (pred == 0xF) 2029 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2030 2031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2032 return MCDisassembler::Fail; 2033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2034 return MCDisassembler::Fail; 2035 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2036 return MCDisassembler::Fail; 2037 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2038 return MCDisassembler::Fail; 2039 2040 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2041 return MCDisassembler::Fail; 2042 2043 return S; 2044} 2045 2046static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2047 uint64_t Address, const void *Decoder) { 2048 DecodeStatus S = MCDisassembler::Success; 2049 2050 unsigned add = fieldFromInstruction(Val, 12, 1); 2051 unsigned imm = fieldFromInstruction(Val, 0, 12); 2052 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2053 2054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2055 return MCDisassembler::Fail; 2056 2057 if (!add) imm *= -1; 2058 if (imm == 0 && !add) imm = INT32_MIN; 2059 Inst.addOperand(MCOperand::CreateImm(imm)); 2060 if (Rn == 15) 2061 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2062 2063 return S; 2064} 2065 2066static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2067 uint64_t Address, const void *Decoder) { 2068 DecodeStatus S = MCDisassembler::Success; 2069 2070 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2071 unsigned U = fieldFromInstruction(Val, 8, 1); 2072 unsigned imm = fieldFromInstruction(Val, 0, 8); 2073 2074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2075 return MCDisassembler::Fail; 2076 2077 if (U) 2078 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2079 else 2080 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2081 2082 return S; 2083} 2084 2085static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2086 uint64_t Address, const void *Decoder) { 2087 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2088} 2089 2090static DecodeStatus 2091DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2092 uint64_t Address, const void *Decoder) { 2093 DecodeStatus Status = MCDisassembler::Success; 2094 2095 // Note the J1 and J2 values are from the encoded instruction. So here 2096 // change them to I1 and I2 values via as documented: 2097 // I1 = NOT(J1 EOR S); 2098 // I2 = NOT(J2 EOR S); 2099 // and build the imm32 with one trailing zero as documented: 2100 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2101 unsigned S = fieldFromInstruction(Insn, 26, 1); 2102 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2103 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2104 unsigned I1 = !(J1 ^ S); 2105 unsigned I2 = !(J2 ^ S); 2106 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2107 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2108 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2109 int imm32 = SignExtend32<24>(tmp << 1); 2110 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2111 true, 4, Inst, Decoder)) 2112 Inst.addOperand(MCOperand::CreateImm(imm32)); 2113 2114 return Status; 2115} 2116 2117static DecodeStatus 2118DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2119 uint64_t Address, const void *Decoder) { 2120 DecodeStatus S = MCDisassembler::Success; 2121 2122 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2123 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2124 2125 if (pred == 0xF) { 2126 Inst.setOpcode(ARM::BLXi); 2127 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2128 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2129 true, 4, Inst, Decoder)) 2130 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2131 return S; 2132 } 2133 2134 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2135 true, 4, Inst, Decoder)) 2136 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2137 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2138 return MCDisassembler::Fail; 2139 2140 return S; 2141} 2142 2143 2144static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2145 uint64_t Address, const void *Decoder) { 2146 DecodeStatus S = MCDisassembler::Success; 2147 2148 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2149 unsigned align = fieldFromInstruction(Val, 4, 2); 2150 2151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2152 return MCDisassembler::Fail; 2153 if (!align) 2154 Inst.addOperand(MCOperand::CreateImm(0)); 2155 else 2156 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2157 2158 return S; 2159} 2160 2161static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2162 uint64_t Address, const void *Decoder) { 2163 DecodeStatus S = MCDisassembler::Success; 2164 2165 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2166 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2167 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2168 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2169 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2170 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2171 2172 // First output register 2173 switch (Inst.getOpcode()) { 2174 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2175 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2176 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2177 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2178 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2179 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2180 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2181 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2182 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2183 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2184 return MCDisassembler::Fail; 2185 break; 2186 case ARM::VLD2b16: 2187 case ARM::VLD2b32: 2188 case ARM::VLD2b8: 2189 case ARM::VLD2b16wb_fixed: 2190 case ARM::VLD2b16wb_register: 2191 case ARM::VLD2b32wb_fixed: 2192 case ARM::VLD2b32wb_register: 2193 case ARM::VLD2b8wb_fixed: 2194 case ARM::VLD2b8wb_register: 2195 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2196 return MCDisassembler::Fail; 2197 break; 2198 default: 2199 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2200 return MCDisassembler::Fail; 2201 } 2202 2203 // Second output register 2204 switch (Inst.getOpcode()) { 2205 case ARM::VLD3d8: 2206 case ARM::VLD3d16: 2207 case ARM::VLD3d32: 2208 case ARM::VLD3d8_UPD: 2209 case ARM::VLD3d16_UPD: 2210 case ARM::VLD3d32_UPD: 2211 case ARM::VLD4d8: 2212 case ARM::VLD4d16: 2213 case ARM::VLD4d32: 2214 case ARM::VLD4d8_UPD: 2215 case ARM::VLD4d16_UPD: 2216 case ARM::VLD4d32_UPD: 2217 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 break; 2220 case ARM::VLD3q8: 2221 case ARM::VLD3q16: 2222 case ARM::VLD3q32: 2223 case ARM::VLD3q8_UPD: 2224 case ARM::VLD3q16_UPD: 2225 case ARM::VLD3q32_UPD: 2226 case ARM::VLD4q8: 2227 case ARM::VLD4q16: 2228 case ARM::VLD4q32: 2229 case ARM::VLD4q8_UPD: 2230 case ARM::VLD4q16_UPD: 2231 case ARM::VLD4q32_UPD: 2232 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2233 return MCDisassembler::Fail; 2234 default: 2235 break; 2236 } 2237 2238 // Third output register 2239 switch(Inst.getOpcode()) { 2240 case ARM::VLD3d8: 2241 case ARM::VLD3d16: 2242 case ARM::VLD3d32: 2243 case ARM::VLD3d8_UPD: 2244 case ARM::VLD3d16_UPD: 2245 case ARM::VLD3d32_UPD: 2246 case ARM::VLD4d8: 2247 case ARM::VLD4d16: 2248 case ARM::VLD4d32: 2249 case ARM::VLD4d8_UPD: 2250 case ARM::VLD4d16_UPD: 2251 case ARM::VLD4d32_UPD: 2252 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2253 return MCDisassembler::Fail; 2254 break; 2255 case ARM::VLD3q8: 2256 case ARM::VLD3q16: 2257 case ARM::VLD3q32: 2258 case ARM::VLD3q8_UPD: 2259 case ARM::VLD3q16_UPD: 2260 case ARM::VLD3q32_UPD: 2261 case ARM::VLD4q8: 2262 case ARM::VLD4q16: 2263 case ARM::VLD4q32: 2264 case ARM::VLD4q8_UPD: 2265 case ARM::VLD4q16_UPD: 2266 case ARM::VLD4q32_UPD: 2267 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2268 return MCDisassembler::Fail; 2269 break; 2270 default: 2271 break; 2272 } 2273 2274 // Fourth output register 2275 switch (Inst.getOpcode()) { 2276 case ARM::VLD4d8: 2277 case ARM::VLD4d16: 2278 case ARM::VLD4d32: 2279 case ARM::VLD4d8_UPD: 2280 case ARM::VLD4d16_UPD: 2281 case ARM::VLD4d32_UPD: 2282 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2283 return MCDisassembler::Fail; 2284 break; 2285 case ARM::VLD4q8: 2286 case ARM::VLD4q16: 2287 case ARM::VLD4q32: 2288 case ARM::VLD4q8_UPD: 2289 case ARM::VLD4q16_UPD: 2290 case ARM::VLD4q32_UPD: 2291 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2292 return MCDisassembler::Fail; 2293 break; 2294 default: 2295 break; 2296 } 2297 2298 // Writeback operand 2299 switch (Inst.getOpcode()) { 2300 case ARM::VLD1d8wb_fixed: 2301 case ARM::VLD1d16wb_fixed: 2302 case ARM::VLD1d32wb_fixed: 2303 case ARM::VLD1d64wb_fixed: 2304 case ARM::VLD1d8wb_register: 2305 case ARM::VLD1d16wb_register: 2306 case ARM::VLD1d32wb_register: 2307 case ARM::VLD1d64wb_register: 2308 case ARM::VLD1q8wb_fixed: 2309 case ARM::VLD1q16wb_fixed: 2310 case ARM::VLD1q32wb_fixed: 2311 case ARM::VLD1q64wb_fixed: 2312 case ARM::VLD1q8wb_register: 2313 case ARM::VLD1q16wb_register: 2314 case ARM::VLD1q32wb_register: 2315 case ARM::VLD1q64wb_register: 2316 case ARM::VLD1d8Twb_fixed: 2317 case ARM::VLD1d8Twb_register: 2318 case ARM::VLD1d16Twb_fixed: 2319 case ARM::VLD1d16Twb_register: 2320 case ARM::VLD1d32Twb_fixed: 2321 case ARM::VLD1d32Twb_register: 2322 case ARM::VLD1d64Twb_fixed: 2323 case ARM::VLD1d64Twb_register: 2324 case ARM::VLD1d8Qwb_fixed: 2325 case ARM::VLD1d8Qwb_register: 2326 case ARM::VLD1d16Qwb_fixed: 2327 case ARM::VLD1d16Qwb_register: 2328 case ARM::VLD1d32Qwb_fixed: 2329 case ARM::VLD1d32Qwb_register: 2330 case ARM::VLD1d64Qwb_fixed: 2331 case ARM::VLD1d64Qwb_register: 2332 case ARM::VLD2d8wb_fixed: 2333 case ARM::VLD2d16wb_fixed: 2334 case ARM::VLD2d32wb_fixed: 2335 case ARM::VLD2q8wb_fixed: 2336 case ARM::VLD2q16wb_fixed: 2337 case ARM::VLD2q32wb_fixed: 2338 case ARM::VLD2d8wb_register: 2339 case ARM::VLD2d16wb_register: 2340 case ARM::VLD2d32wb_register: 2341 case ARM::VLD2q8wb_register: 2342 case ARM::VLD2q16wb_register: 2343 case ARM::VLD2q32wb_register: 2344 case ARM::VLD2b8wb_fixed: 2345 case ARM::VLD2b16wb_fixed: 2346 case ARM::VLD2b32wb_fixed: 2347 case ARM::VLD2b8wb_register: 2348 case ARM::VLD2b16wb_register: 2349 case ARM::VLD2b32wb_register: 2350 Inst.addOperand(MCOperand::CreateImm(0)); 2351 break; 2352 case ARM::VLD3d8_UPD: 2353 case ARM::VLD3d16_UPD: 2354 case ARM::VLD3d32_UPD: 2355 case ARM::VLD3q8_UPD: 2356 case ARM::VLD3q16_UPD: 2357 case ARM::VLD3q32_UPD: 2358 case ARM::VLD4d8_UPD: 2359 case ARM::VLD4d16_UPD: 2360 case ARM::VLD4d32_UPD: 2361 case ARM::VLD4q8_UPD: 2362 case ARM::VLD4q16_UPD: 2363 case ARM::VLD4q32_UPD: 2364 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2365 return MCDisassembler::Fail; 2366 break; 2367 default: 2368 break; 2369 } 2370 2371 // AddrMode6 Base (register+alignment) 2372 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2373 return MCDisassembler::Fail; 2374 2375 // AddrMode6 Offset (register) 2376 switch (Inst.getOpcode()) { 2377 default: 2378 // The below have been updated to have explicit am6offset split 2379 // between fixed and register offset. For those instructions not 2380 // yet updated, we need to add an additional reg0 operand for the 2381 // fixed variant. 2382 // 2383 // The fixed offset encodes as Rm == 0xd, so we check for that. 2384 if (Rm == 0xd) { 2385 Inst.addOperand(MCOperand::CreateReg(0)); 2386 break; 2387 } 2388 // Fall through to handle the register offset variant. 2389 case ARM::VLD1d8wb_fixed: 2390 case ARM::VLD1d16wb_fixed: 2391 case ARM::VLD1d32wb_fixed: 2392 case ARM::VLD1d64wb_fixed: 2393 case ARM::VLD1d8Twb_fixed: 2394 case ARM::VLD1d16Twb_fixed: 2395 case ARM::VLD1d32Twb_fixed: 2396 case ARM::VLD1d64Twb_fixed: 2397 case ARM::VLD1d8Qwb_fixed: 2398 case ARM::VLD1d16Qwb_fixed: 2399 case ARM::VLD1d32Qwb_fixed: 2400 case ARM::VLD1d64Qwb_fixed: 2401 case ARM::VLD1d8wb_register: 2402 case ARM::VLD1d16wb_register: 2403 case ARM::VLD1d32wb_register: 2404 case ARM::VLD1d64wb_register: 2405 case ARM::VLD1q8wb_fixed: 2406 case ARM::VLD1q16wb_fixed: 2407 case ARM::VLD1q32wb_fixed: 2408 case ARM::VLD1q64wb_fixed: 2409 case ARM::VLD1q8wb_register: 2410 case ARM::VLD1q16wb_register: 2411 case ARM::VLD1q32wb_register: 2412 case ARM::VLD1q64wb_register: 2413 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2414 // variant encodes Rm == 0xf. Anything else is a register offset post- 2415 // increment and we need to add the register operand to the instruction. 2416 if (Rm != 0xD && Rm != 0xF && 2417 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2418 return MCDisassembler::Fail; 2419 break; 2420 case ARM::VLD2d8wb_fixed: 2421 case ARM::VLD2d16wb_fixed: 2422 case ARM::VLD2d32wb_fixed: 2423 case ARM::VLD2b8wb_fixed: 2424 case ARM::VLD2b16wb_fixed: 2425 case ARM::VLD2b32wb_fixed: 2426 case ARM::VLD2q8wb_fixed: 2427 case ARM::VLD2q16wb_fixed: 2428 case ARM::VLD2q32wb_fixed: 2429 break; 2430 } 2431 2432 return S; 2433} 2434 2435static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2436 uint64_t Address, const void *Decoder) { 2437 DecodeStatus S = MCDisassembler::Success; 2438 2439 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2440 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2441 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2442 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2443 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2444 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2445 2446 // Writeback Operand 2447 switch (Inst.getOpcode()) { 2448 case ARM::VST1d8wb_fixed: 2449 case ARM::VST1d16wb_fixed: 2450 case ARM::VST1d32wb_fixed: 2451 case ARM::VST1d64wb_fixed: 2452 case ARM::VST1d8wb_register: 2453 case ARM::VST1d16wb_register: 2454 case ARM::VST1d32wb_register: 2455 case ARM::VST1d64wb_register: 2456 case ARM::VST1q8wb_fixed: 2457 case ARM::VST1q16wb_fixed: 2458 case ARM::VST1q32wb_fixed: 2459 case ARM::VST1q64wb_fixed: 2460 case ARM::VST1q8wb_register: 2461 case ARM::VST1q16wb_register: 2462 case ARM::VST1q32wb_register: 2463 case ARM::VST1q64wb_register: 2464 case ARM::VST1d8Twb_fixed: 2465 case ARM::VST1d16Twb_fixed: 2466 case ARM::VST1d32Twb_fixed: 2467 case ARM::VST1d64Twb_fixed: 2468 case ARM::VST1d8Twb_register: 2469 case ARM::VST1d16Twb_register: 2470 case ARM::VST1d32Twb_register: 2471 case ARM::VST1d64Twb_register: 2472 case ARM::VST1d8Qwb_fixed: 2473 case ARM::VST1d16Qwb_fixed: 2474 case ARM::VST1d32Qwb_fixed: 2475 case ARM::VST1d64Qwb_fixed: 2476 case ARM::VST1d8Qwb_register: 2477 case ARM::VST1d16Qwb_register: 2478 case ARM::VST1d32Qwb_register: 2479 case ARM::VST1d64Qwb_register: 2480 case ARM::VST2d8wb_fixed: 2481 case ARM::VST2d16wb_fixed: 2482 case ARM::VST2d32wb_fixed: 2483 case ARM::VST2d8wb_register: 2484 case ARM::VST2d16wb_register: 2485 case ARM::VST2d32wb_register: 2486 case ARM::VST2q8wb_fixed: 2487 case ARM::VST2q16wb_fixed: 2488 case ARM::VST2q32wb_fixed: 2489 case ARM::VST2q8wb_register: 2490 case ARM::VST2q16wb_register: 2491 case ARM::VST2q32wb_register: 2492 case ARM::VST2b8wb_fixed: 2493 case ARM::VST2b16wb_fixed: 2494 case ARM::VST2b32wb_fixed: 2495 case ARM::VST2b8wb_register: 2496 case ARM::VST2b16wb_register: 2497 case ARM::VST2b32wb_register: 2498 if (Rm == 0xF) 2499 return MCDisassembler::Fail; 2500 Inst.addOperand(MCOperand::CreateImm(0)); 2501 break; 2502 case ARM::VST3d8_UPD: 2503 case ARM::VST3d16_UPD: 2504 case ARM::VST3d32_UPD: 2505 case ARM::VST3q8_UPD: 2506 case ARM::VST3q16_UPD: 2507 case ARM::VST3q32_UPD: 2508 case ARM::VST4d8_UPD: 2509 case ARM::VST4d16_UPD: 2510 case ARM::VST4d32_UPD: 2511 case ARM::VST4q8_UPD: 2512 case ARM::VST4q16_UPD: 2513 case ARM::VST4q32_UPD: 2514 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2515 return MCDisassembler::Fail; 2516 break; 2517 default: 2518 break; 2519 } 2520 2521 // AddrMode6 Base (register+alignment) 2522 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2523 return MCDisassembler::Fail; 2524 2525 // AddrMode6 Offset (register) 2526 switch (Inst.getOpcode()) { 2527 default: 2528 if (Rm == 0xD) 2529 Inst.addOperand(MCOperand::CreateReg(0)); 2530 else if (Rm != 0xF) { 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 } 2534 break; 2535 case ARM::VST1d8wb_fixed: 2536 case ARM::VST1d16wb_fixed: 2537 case ARM::VST1d32wb_fixed: 2538 case ARM::VST1d64wb_fixed: 2539 case ARM::VST1q8wb_fixed: 2540 case ARM::VST1q16wb_fixed: 2541 case ARM::VST1q32wb_fixed: 2542 case ARM::VST1q64wb_fixed: 2543 case ARM::VST1d8Twb_fixed: 2544 case ARM::VST1d16Twb_fixed: 2545 case ARM::VST1d32Twb_fixed: 2546 case ARM::VST1d64Twb_fixed: 2547 case ARM::VST1d8Qwb_fixed: 2548 case ARM::VST1d16Qwb_fixed: 2549 case ARM::VST1d32Qwb_fixed: 2550 case ARM::VST1d64Qwb_fixed: 2551 case ARM::VST2d8wb_fixed: 2552 case ARM::VST2d16wb_fixed: 2553 case ARM::VST2d32wb_fixed: 2554 case ARM::VST2q8wb_fixed: 2555 case ARM::VST2q16wb_fixed: 2556 case ARM::VST2q32wb_fixed: 2557 case ARM::VST2b8wb_fixed: 2558 case ARM::VST2b16wb_fixed: 2559 case ARM::VST2b32wb_fixed: 2560 break; 2561 } 2562 2563 2564 // First input register 2565 switch (Inst.getOpcode()) { 2566 case ARM::VST1q16: 2567 case ARM::VST1q32: 2568 case ARM::VST1q64: 2569 case ARM::VST1q8: 2570 case ARM::VST1q16wb_fixed: 2571 case ARM::VST1q16wb_register: 2572 case ARM::VST1q32wb_fixed: 2573 case ARM::VST1q32wb_register: 2574 case ARM::VST1q64wb_fixed: 2575 case ARM::VST1q64wb_register: 2576 case ARM::VST1q8wb_fixed: 2577 case ARM::VST1q8wb_register: 2578 case ARM::VST2d16: 2579 case ARM::VST2d32: 2580 case ARM::VST2d8: 2581 case ARM::VST2d16wb_fixed: 2582 case ARM::VST2d16wb_register: 2583 case ARM::VST2d32wb_fixed: 2584 case ARM::VST2d32wb_register: 2585 case ARM::VST2d8wb_fixed: 2586 case ARM::VST2d8wb_register: 2587 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2588 return MCDisassembler::Fail; 2589 break; 2590 case ARM::VST2b16: 2591 case ARM::VST2b32: 2592 case ARM::VST2b8: 2593 case ARM::VST2b16wb_fixed: 2594 case ARM::VST2b16wb_register: 2595 case ARM::VST2b32wb_fixed: 2596 case ARM::VST2b32wb_register: 2597 case ARM::VST2b8wb_fixed: 2598 case ARM::VST2b8wb_register: 2599 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2600 return MCDisassembler::Fail; 2601 break; 2602 default: 2603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2604 return MCDisassembler::Fail; 2605 } 2606 2607 // Second input register 2608 switch (Inst.getOpcode()) { 2609 case ARM::VST3d8: 2610 case ARM::VST3d16: 2611 case ARM::VST3d32: 2612 case ARM::VST3d8_UPD: 2613 case ARM::VST3d16_UPD: 2614 case ARM::VST3d32_UPD: 2615 case ARM::VST4d8: 2616 case ARM::VST4d16: 2617 case ARM::VST4d32: 2618 case ARM::VST4d8_UPD: 2619 case ARM::VST4d16_UPD: 2620 case ARM::VST4d32_UPD: 2621 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2622 return MCDisassembler::Fail; 2623 break; 2624 case ARM::VST3q8: 2625 case ARM::VST3q16: 2626 case ARM::VST3q32: 2627 case ARM::VST3q8_UPD: 2628 case ARM::VST3q16_UPD: 2629 case ARM::VST3q32_UPD: 2630 case ARM::VST4q8: 2631 case ARM::VST4q16: 2632 case ARM::VST4q32: 2633 case ARM::VST4q8_UPD: 2634 case ARM::VST4q16_UPD: 2635 case ARM::VST4q32_UPD: 2636 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2637 return MCDisassembler::Fail; 2638 break; 2639 default: 2640 break; 2641 } 2642 2643 // Third input register 2644 switch (Inst.getOpcode()) { 2645 case ARM::VST3d8: 2646 case ARM::VST3d16: 2647 case ARM::VST3d32: 2648 case ARM::VST3d8_UPD: 2649 case ARM::VST3d16_UPD: 2650 case ARM::VST3d32_UPD: 2651 case ARM::VST4d8: 2652 case ARM::VST4d16: 2653 case ARM::VST4d32: 2654 case ARM::VST4d8_UPD: 2655 case ARM::VST4d16_UPD: 2656 case ARM::VST4d32_UPD: 2657 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2658 return MCDisassembler::Fail; 2659 break; 2660 case ARM::VST3q8: 2661 case ARM::VST3q16: 2662 case ARM::VST3q32: 2663 case ARM::VST3q8_UPD: 2664 case ARM::VST3q16_UPD: 2665 case ARM::VST3q32_UPD: 2666 case ARM::VST4q8: 2667 case ARM::VST4q16: 2668 case ARM::VST4q32: 2669 case ARM::VST4q8_UPD: 2670 case ARM::VST4q16_UPD: 2671 case ARM::VST4q32_UPD: 2672 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2673 return MCDisassembler::Fail; 2674 break; 2675 default: 2676 break; 2677 } 2678 2679 // Fourth input register 2680 switch (Inst.getOpcode()) { 2681 case ARM::VST4d8: 2682 case ARM::VST4d16: 2683 case ARM::VST4d32: 2684 case ARM::VST4d8_UPD: 2685 case ARM::VST4d16_UPD: 2686 case ARM::VST4d32_UPD: 2687 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2688 return MCDisassembler::Fail; 2689 break; 2690 case ARM::VST4q8: 2691 case ARM::VST4q16: 2692 case ARM::VST4q32: 2693 case ARM::VST4q8_UPD: 2694 case ARM::VST4q16_UPD: 2695 case ARM::VST4q32_UPD: 2696 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 break; 2699 default: 2700 break; 2701 } 2702 2703 return S; 2704} 2705 2706static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2707 uint64_t Address, const void *Decoder) { 2708 DecodeStatus S = MCDisassembler::Success; 2709 2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2711 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2712 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2713 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2714 unsigned align = fieldFromInstruction(Insn, 4, 1); 2715 unsigned size = fieldFromInstruction(Insn, 6, 2); 2716 2717 if (size == 0 && align == 1) 2718 return MCDisassembler::Fail; 2719 align *= (1 << size); 2720 2721 switch (Inst.getOpcode()) { 2722 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2723 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2724 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2725 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2726 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 break; 2729 default: 2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 break; 2733 } 2734 if (Rm != 0xF) { 2735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 } 2738 2739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2740 return MCDisassembler::Fail; 2741 Inst.addOperand(MCOperand::CreateImm(align)); 2742 2743 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2744 // variant encodes Rm == 0xf. Anything else is a register offset post- 2745 // increment and we need to add the register operand to the instruction. 2746 if (Rm != 0xD && Rm != 0xF && 2747 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 2750 return S; 2751} 2752 2753static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2754 uint64_t Address, const void *Decoder) { 2755 DecodeStatus S = MCDisassembler::Success; 2756 2757 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2758 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2759 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2760 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2761 unsigned align = fieldFromInstruction(Insn, 4, 1); 2762 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2763 align *= 2*size; 2764 2765 switch (Inst.getOpcode()) { 2766 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2767 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2768 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2769 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2770 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2771 return MCDisassembler::Fail; 2772 break; 2773 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2774 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2775 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2776 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2777 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 break; 2780 default: 2781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 break; 2784 } 2785 2786 if (Rm != 0xF) 2787 Inst.addOperand(MCOperand::CreateImm(0)); 2788 2789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2790 return MCDisassembler::Fail; 2791 Inst.addOperand(MCOperand::CreateImm(align)); 2792 2793 if (Rm != 0xD && Rm != 0xF) { 2794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 } 2797 2798 return S; 2799} 2800 2801static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2802 uint64_t Address, const void *Decoder) { 2803 DecodeStatus S = MCDisassembler::Success; 2804 2805 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2806 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2807 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2808 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2809 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2810 2811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2816 return MCDisassembler::Fail; 2817 if (Rm != 0xF) { 2818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2819 return MCDisassembler::Fail; 2820 } 2821 2822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 Inst.addOperand(MCOperand::CreateImm(0)); 2825 2826 if (Rm == 0xD) 2827 Inst.addOperand(MCOperand::CreateReg(0)); 2828 else if (Rm != 0xF) { 2829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2830 return MCDisassembler::Fail; 2831 } 2832 2833 return S; 2834} 2835 2836static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2837 uint64_t Address, const void *Decoder) { 2838 DecodeStatus S = MCDisassembler::Success; 2839 2840 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2841 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2842 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2843 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2844 unsigned size = fieldFromInstruction(Insn, 6, 2); 2845 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2846 unsigned align = fieldFromInstruction(Insn, 4, 1); 2847 2848 if (size == 0x3) { 2849 if (align == 0) 2850 return MCDisassembler::Fail; 2851 size = 4; 2852 align = 16; 2853 } else { 2854 if (size == 2) { 2855 size = 1 << size; 2856 align *= 8; 2857 } else { 2858 size = 1 << size; 2859 align *= 4*size; 2860 } 2861 } 2862 2863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2864 return MCDisassembler::Fail; 2865 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2866 return MCDisassembler::Fail; 2867 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2868 return MCDisassembler::Fail; 2869 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2870 return MCDisassembler::Fail; 2871 if (Rm != 0xF) { 2872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2873 return MCDisassembler::Fail; 2874 } 2875 2876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 Inst.addOperand(MCOperand::CreateImm(align)); 2879 2880 if (Rm == 0xD) 2881 Inst.addOperand(MCOperand::CreateReg(0)); 2882 else if (Rm != 0xF) { 2883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 } 2886 2887 return S; 2888} 2889 2890static DecodeStatus 2891DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2892 uint64_t Address, const void *Decoder) { 2893 DecodeStatus S = MCDisassembler::Success; 2894 2895 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2896 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2897 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2898 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2899 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2900 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2901 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2902 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2903 2904 if (Q) { 2905 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2906 return MCDisassembler::Fail; 2907 } else { 2908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 } 2911 2912 Inst.addOperand(MCOperand::CreateImm(imm)); 2913 2914 switch (Inst.getOpcode()) { 2915 case ARM::VORRiv4i16: 2916 case ARM::VORRiv2i32: 2917 case ARM::VBICiv4i16: 2918 case ARM::VBICiv2i32: 2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 break; 2922 case ARM::VORRiv8i16: 2923 case ARM::VORRiv4i32: 2924 case ARM::VBICiv8i16: 2925 case ARM::VBICiv4i32: 2926 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2927 return MCDisassembler::Fail; 2928 break; 2929 default: 2930 break; 2931 } 2932 2933 return S; 2934} 2935 2936static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2937 uint64_t Address, const void *Decoder) { 2938 DecodeStatus S = MCDisassembler::Success; 2939 2940 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2941 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2942 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2943 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2944 unsigned size = fieldFromInstruction(Insn, 18, 2); 2945 2946 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2949 return MCDisassembler::Fail; 2950 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2951 2952 return S; 2953} 2954 2955static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2956 uint64_t Address, const void *Decoder) { 2957 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2958 return MCDisassembler::Success; 2959} 2960 2961static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2962 uint64_t Address, const void *Decoder) { 2963 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2964 return MCDisassembler::Success; 2965} 2966 2967static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2968 uint64_t Address, const void *Decoder) { 2969 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2970 return MCDisassembler::Success; 2971} 2972 2973static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2974 uint64_t Address, const void *Decoder) { 2975 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2976 return MCDisassembler::Success; 2977} 2978 2979static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2980 uint64_t Address, const void *Decoder) { 2981 DecodeStatus S = MCDisassembler::Success; 2982 2983 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2984 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2986 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2987 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2988 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2989 unsigned op = fieldFromInstruction(Insn, 6, 1); 2990 2991 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2992 return MCDisassembler::Fail; 2993 if (op) { 2994 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2995 return MCDisassembler::Fail; // Writeback 2996 } 2997 2998 switch (Inst.getOpcode()) { 2999 case ARM::VTBL2: 3000 case ARM::VTBX2: 3001 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 break; 3004 default: 3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 } 3008 3009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 3012 return S; 3013} 3014 3015static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3016 uint64_t Address, const void *Decoder) { 3017 DecodeStatus S = MCDisassembler::Success; 3018 3019 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3020 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3021 3022 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 3025 switch(Inst.getOpcode()) { 3026 default: 3027 return MCDisassembler::Fail; 3028 case ARM::tADR: 3029 break; // tADR does not explicitly represent the PC as an operand. 3030 case ARM::tADDrSPi: 3031 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3032 break; 3033 } 3034 3035 Inst.addOperand(MCOperand::CreateImm(imm)); 3036 return S; 3037} 3038 3039static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3040 uint64_t Address, const void *Decoder) { 3041 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3042 true, 2, Inst, Decoder)) 3043 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3044 return MCDisassembler::Success; 3045} 3046 3047static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3048 uint64_t Address, const void *Decoder) { 3049 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3050 true, 4, Inst, Decoder)) 3051 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3052 return MCDisassembler::Success; 3053} 3054 3055static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3056 uint64_t Address, const void *Decoder) { 3057 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3058 true, 2, Inst, Decoder)) 3059 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3060 return MCDisassembler::Success; 3061} 3062 3063static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3064 uint64_t Address, const void *Decoder) { 3065 DecodeStatus S = MCDisassembler::Success; 3066 3067 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3068 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3069 3070 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3071 return MCDisassembler::Fail; 3072 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3073 return MCDisassembler::Fail; 3074 3075 return S; 3076} 3077 3078static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3079 uint64_t Address, const void *Decoder) { 3080 DecodeStatus S = MCDisassembler::Success; 3081 3082 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3083 unsigned imm = fieldFromInstruction(Val, 3, 5); 3084 3085 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3086 return MCDisassembler::Fail; 3087 Inst.addOperand(MCOperand::CreateImm(imm)); 3088 3089 return S; 3090} 3091 3092static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3093 uint64_t Address, const void *Decoder) { 3094 unsigned imm = Val << 2; 3095 3096 Inst.addOperand(MCOperand::CreateImm(imm)); 3097 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3098 3099 return MCDisassembler::Success; 3100} 3101 3102static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3103 uint64_t Address, const void *Decoder) { 3104 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3105 Inst.addOperand(MCOperand::CreateImm(Val)); 3106 3107 return MCDisassembler::Success; 3108} 3109 3110static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3111 uint64_t Address, const void *Decoder) { 3112 DecodeStatus S = MCDisassembler::Success; 3113 3114 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3115 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3116 unsigned imm = fieldFromInstruction(Val, 0, 2); 3117 3118 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3119 return MCDisassembler::Fail; 3120 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3121 return MCDisassembler::Fail; 3122 Inst.addOperand(MCOperand::CreateImm(imm)); 3123 3124 return S; 3125} 3126 3127static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3128 uint64_t Address, const void *Decoder) { 3129 DecodeStatus S = MCDisassembler::Success; 3130 3131 switch (Inst.getOpcode()) { 3132 case ARM::t2PLDs: 3133 case ARM::t2PLDWs: 3134 case ARM::t2PLIs: 3135 break; 3136 default: { 3137 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3138 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 } 3141 } 3142 3143 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3144 if (Rn == 0xF) { 3145 switch (Inst.getOpcode()) { 3146 case ARM::t2LDRBs: 3147 Inst.setOpcode(ARM::t2LDRBpci); 3148 break; 3149 case ARM::t2LDRHs: 3150 Inst.setOpcode(ARM::t2LDRHpci); 3151 break; 3152 case ARM::t2LDRSHs: 3153 Inst.setOpcode(ARM::t2LDRSHpci); 3154 break; 3155 case ARM::t2LDRSBs: 3156 Inst.setOpcode(ARM::t2LDRSBpci); 3157 break; 3158 case ARM::t2PLDs: 3159 Inst.setOpcode(ARM::t2PLDi12); 3160 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3161 break; 3162 default: 3163 return MCDisassembler::Fail; 3164 } 3165 3166 int imm = fieldFromInstruction(Insn, 0, 12); 3167 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3168 Inst.addOperand(MCOperand::CreateImm(imm)); 3169 3170 return S; 3171 } 3172 3173 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3174 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3175 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3176 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3177 return MCDisassembler::Fail; 3178 3179 return S; 3180} 3181 3182static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3183 uint64_t Address, const void *Decoder) { 3184 if (Val == 0) 3185 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3186 else { 3187 int imm = Val & 0xFF; 3188 3189 if (!(Val & 0x100)) imm *= -1; 3190 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3191 } 3192 3193 return MCDisassembler::Success; 3194} 3195 3196static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3197 uint64_t Address, const void *Decoder) { 3198 DecodeStatus S = MCDisassembler::Success; 3199 3200 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3201 unsigned imm = fieldFromInstruction(Val, 0, 9); 3202 3203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3204 return MCDisassembler::Fail; 3205 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3206 return MCDisassembler::Fail; 3207 3208 return S; 3209} 3210 3211static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3212 uint64_t Address, const void *Decoder) { 3213 DecodeStatus S = MCDisassembler::Success; 3214 3215 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3216 unsigned imm = fieldFromInstruction(Val, 0, 8); 3217 3218 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3219 return MCDisassembler::Fail; 3220 3221 Inst.addOperand(MCOperand::CreateImm(imm)); 3222 3223 return S; 3224} 3225 3226static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3227 uint64_t Address, const void *Decoder) { 3228 int imm = Val & 0xFF; 3229 if (Val == 0) 3230 imm = INT32_MIN; 3231 else if (!(Val & 0x100)) 3232 imm *= -1; 3233 Inst.addOperand(MCOperand::CreateImm(imm)); 3234 3235 return MCDisassembler::Success; 3236} 3237 3238 3239static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3240 uint64_t Address, const void *Decoder) { 3241 DecodeStatus S = MCDisassembler::Success; 3242 3243 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3244 unsigned imm = fieldFromInstruction(Val, 0, 9); 3245 3246 // Some instructions always use an additive offset. 3247 switch (Inst.getOpcode()) { 3248 case ARM::t2LDRT: 3249 case ARM::t2LDRBT: 3250 case ARM::t2LDRHT: 3251 case ARM::t2LDRSBT: 3252 case ARM::t2LDRSHT: 3253 case ARM::t2STRT: 3254 case ARM::t2STRBT: 3255 case ARM::t2STRHT: 3256 imm |= 0x100; 3257 break; 3258 default: 3259 break; 3260 } 3261 3262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3263 return MCDisassembler::Fail; 3264 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3265 return MCDisassembler::Fail; 3266 3267 return S; 3268} 3269 3270static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3271 uint64_t Address, const void *Decoder) { 3272 DecodeStatus S = MCDisassembler::Success; 3273 3274 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3275 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3276 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3277 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3278 addr |= Rn << 9; 3279 unsigned load = fieldFromInstruction(Insn, 20, 1); 3280 3281 if (!load) { 3282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 } 3285 3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 3289 if (load) { 3290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 } 3293 3294 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 3297 return S; 3298} 3299 3300static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3301 uint64_t Address, const void *Decoder) { 3302 DecodeStatus S = MCDisassembler::Success; 3303 3304 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3305 unsigned imm = fieldFromInstruction(Val, 0, 12); 3306 3307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 Inst.addOperand(MCOperand::CreateImm(imm)); 3310 3311 return S; 3312} 3313 3314 3315static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3316 uint64_t Address, const void *Decoder) { 3317 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3318 3319 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3320 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3321 Inst.addOperand(MCOperand::CreateImm(imm)); 3322 3323 return MCDisassembler::Success; 3324} 3325 3326static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3327 uint64_t Address, const void *Decoder) { 3328 DecodeStatus S = MCDisassembler::Success; 3329 3330 if (Inst.getOpcode() == ARM::tADDrSP) { 3331 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3332 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3333 3334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3335 return MCDisassembler::Fail; 3336 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3338 return MCDisassembler::Fail; 3339 } else if (Inst.getOpcode() == ARM::tADDspr) { 3340 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3341 3342 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3343 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3345 return MCDisassembler::Fail; 3346 } 3347 3348 return S; 3349} 3350 3351static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3352 uint64_t Address, const void *Decoder) { 3353 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3354 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3355 3356 Inst.addOperand(MCOperand::CreateImm(imod)); 3357 Inst.addOperand(MCOperand::CreateImm(flags)); 3358 3359 return MCDisassembler::Success; 3360} 3361 3362static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3363 uint64_t Address, const void *Decoder) { 3364 DecodeStatus S = MCDisassembler::Success; 3365 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3366 unsigned add = fieldFromInstruction(Insn, 4, 1); 3367 3368 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3369 return MCDisassembler::Fail; 3370 Inst.addOperand(MCOperand::CreateImm(add)); 3371 3372 return S; 3373} 3374 3375static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3376 uint64_t Address, const void *Decoder) { 3377 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3378 // Note only one trailing zero not two. Also the J1 and J2 values are from 3379 // the encoded instruction. So here change to I1 and I2 values via: 3380 // I1 = NOT(J1 EOR S); 3381 // I2 = NOT(J2 EOR S); 3382 // and build the imm32 with two trailing zeros as documented: 3383 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3384 unsigned S = (Val >> 23) & 1; 3385 unsigned J1 = (Val >> 22) & 1; 3386 unsigned J2 = (Val >> 21) & 1; 3387 unsigned I1 = !(J1 ^ S); 3388 unsigned I2 = !(J2 ^ S); 3389 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3390 int imm32 = SignExtend32<25>(tmp << 1); 3391 3392 if (!tryAddingSymbolicOperand(Address, 3393 (Address & ~2u) + imm32 + 4, 3394 true, 4, Inst, Decoder)) 3395 Inst.addOperand(MCOperand::CreateImm(imm32)); 3396 return MCDisassembler::Success; 3397} 3398 3399static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3400 uint64_t Address, const void *Decoder) { 3401 if (Val == 0xA || Val == 0xB) 3402 return MCDisassembler::Fail; 3403 3404 Inst.addOperand(MCOperand::CreateImm(Val)); 3405 return MCDisassembler::Success; 3406} 3407 3408static DecodeStatus 3409DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3410 uint64_t Address, const void *Decoder) { 3411 DecodeStatus S = MCDisassembler::Success; 3412 3413 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3414 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3415 3416 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3420 return MCDisassembler::Fail; 3421 return S; 3422} 3423 3424static DecodeStatus 3425DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3426 uint64_t Address, const void *Decoder) { 3427 DecodeStatus S = MCDisassembler::Success; 3428 3429 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3430 if (pred == 0xE || pred == 0xF) { 3431 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3432 switch (opc) { 3433 default: 3434 return MCDisassembler::Fail; 3435 case 0xf3bf8f4: 3436 Inst.setOpcode(ARM::t2DSB); 3437 break; 3438 case 0xf3bf8f5: 3439 Inst.setOpcode(ARM::t2DMB); 3440 break; 3441 case 0xf3bf8f6: 3442 Inst.setOpcode(ARM::t2ISB); 3443 break; 3444 } 3445 3446 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3447 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3448 } 3449 3450 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3451 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3452 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3453 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3454 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3455 3456 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3457 return MCDisassembler::Fail; 3458 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 3461 return S; 3462} 3463 3464// Decode a shifted immediate operand. These basically consist 3465// of an 8-bit value, and a 4-bit directive that specifies either 3466// a splat operation or a rotation. 3467static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3468 uint64_t Address, const void *Decoder) { 3469 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3470 if (ctrl == 0) { 3471 unsigned byte = fieldFromInstruction(Val, 8, 2); 3472 unsigned imm = fieldFromInstruction(Val, 0, 8); 3473 switch (byte) { 3474 case 0: 3475 Inst.addOperand(MCOperand::CreateImm(imm)); 3476 break; 3477 case 1: 3478 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3479 break; 3480 case 2: 3481 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3482 break; 3483 case 3: 3484 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3485 (imm << 8) | imm)); 3486 break; 3487 } 3488 } else { 3489 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3490 unsigned rot = fieldFromInstruction(Val, 7, 5); 3491 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3492 Inst.addOperand(MCOperand::CreateImm(imm)); 3493 } 3494 3495 return MCDisassembler::Success; 3496} 3497 3498static DecodeStatus 3499DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3500 uint64_t Address, const void *Decoder){ 3501 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3502 true, 2, Inst, Decoder)) 3503 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3504 return MCDisassembler::Success; 3505} 3506 3507static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3508 uint64_t Address, const void *Decoder){ 3509 // Val is passed in as S:J1:J2:imm10:imm11 3510 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3511 // the encoded instruction. So here change to I1 and I2 values via: 3512 // I1 = NOT(J1 EOR S); 3513 // I2 = NOT(J2 EOR S); 3514 // and build the imm32 with one trailing zero as documented: 3515 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3516 unsigned S = (Val >> 23) & 1; 3517 unsigned J1 = (Val >> 22) & 1; 3518 unsigned J2 = (Val >> 21) & 1; 3519 unsigned I1 = !(J1 ^ S); 3520 unsigned I2 = !(J2 ^ S); 3521 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3522 int imm32 = SignExtend32<25>(tmp << 1); 3523 3524 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3525 true, 4, Inst, Decoder)) 3526 Inst.addOperand(MCOperand::CreateImm(imm32)); 3527 return MCDisassembler::Success; 3528} 3529 3530static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3531 uint64_t Address, const void *Decoder) { 3532 if (Val & ~0xf) 3533 return MCDisassembler::Fail; 3534 3535 Inst.addOperand(MCOperand::CreateImm(Val)); 3536 return MCDisassembler::Success; 3537} 3538 3539static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3540 uint64_t Address, const void *Decoder) { 3541 if (!Val) return MCDisassembler::Fail; 3542 Inst.addOperand(MCOperand::CreateImm(Val)); 3543 return MCDisassembler::Success; 3544} 3545 3546static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3547 uint64_t Address, const void *Decoder) { 3548 DecodeStatus S = MCDisassembler::Success; 3549 3550 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3551 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3552 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3553 3554 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3555 3556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3557 return MCDisassembler::Fail; 3558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3559 return MCDisassembler::Fail; 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 3565 return S; 3566} 3567 3568 3569static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3570 uint64_t Address, const void *Decoder){ 3571 DecodeStatus S = MCDisassembler::Success; 3572 3573 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3574 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3575 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3576 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3577 3578 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 3581 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3582 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3583 3584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3585 return MCDisassembler::Fail; 3586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3587 return MCDisassembler::Fail; 3588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 3593 return S; 3594} 3595 3596static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3597 uint64_t Address, const void *Decoder) { 3598 DecodeStatus S = MCDisassembler::Success; 3599 3600 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3601 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3602 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3603 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3604 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3605 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3606 3607 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3608 3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3614 return MCDisassembler::Fail; 3615 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 3618 return S; 3619} 3620 3621static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3622 uint64_t Address, const void *Decoder) { 3623 DecodeStatus S = MCDisassembler::Success; 3624 3625 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3626 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3627 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3628 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3629 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3630 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3631 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3632 3633 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3634 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3635 3636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 3645 return S; 3646} 3647 3648 3649static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3650 uint64_t Address, const void *Decoder) { 3651 DecodeStatus S = MCDisassembler::Success; 3652 3653 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3654 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3655 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3656 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3657 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3658 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3659 3660 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3661 3662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3663 return MCDisassembler::Fail; 3664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3665 return MCDisassembler::Fail; 3666 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3667 return MCDisassembler::Fail; 3668 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3669 return MCDisassembler::Fail; 3670 3671 return S; 3672} 3673 3674static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3675 uint64_t Address, const void *Decoder) { 3676 DecodeStatus S = MCDisassembler::Success; 3677 3678 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3679 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3680 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3681 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3682 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3683 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3684 3685 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3686 3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3688 return MCDisassembler::Fail; 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3692 return MCDisassembler::Fail; 3693 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3694 return MCDisassembler::Fail; 3695 3696 return S; 3697} 3698 3699static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3700 uint64_t Address, const void *Decoder) { 3701 DecodeStatus S = MCDisassembler::Success; 3702 3703 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3704 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3705 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3706 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3707 unsigned size = fieldFromInstruction(Insn, 10, 2); 3708 3709 unsigned align = 0; 3710 unsigned index = 0; 3711 switch (size) { 3712 default: 3713 return MCDisassembler::Fail; 3714 case 0: 3715 if (fieldFromInstruction(Insn, 4, 1)) 3716 return MCDisassembler::Fail; // UNDEFINED 3717 index = fieldFromInstruction(Insn, 5, 3); 3718 break; 3719 case 1: 3720 if (fieldFromInstruction(Insn, 5, 1)) 3721 return MCDisassembler::Fail; // UNDEFINED 3722 index = fieldFromInstruction(Insn, 6, 2); 3723 if (fieldFromInstruction(Insn, 4, 1)) 3724 align = 2; 3725 break; 3726 case 2: 3727 if (fieldFromInstruction(Insn, 6, 1)) 3728 return MCDisassembler::Fail; // UNDEFINED 3729 index = fieldFromInstruction(Insn, 7, 1); 3730 3731 switch (fieldFromInstruction(Insn, 4, 2)) { 3732 case 0 : 3733 align = 0; break; 3734 case 3: 3735 align = 4; break; 3736 default: 3737 return MCDisassembler::Fail; 3738 } 3739 break; 3740 } 3741 3742 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3743 return MCDisassembler::Fail; 3744 if (Rm != 0xF) { // Writeback 3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 } 3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 Inst.addOperand(MCOperand::CreateImm(align)); 3751 if (Rm != 0xF) { 3752 if (Rm != 0xD) { 3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 } else 3756 Inst.addOperand(MCOperand::CreateReg(0)); 3757 } 3758 3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 Inst.addOperand(MCOperand::CreateImm(index)); 3762 3763 return S; 3764} 3765 3766static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3767 uint64_t Address, const void *Decoder) { 3768 DecodeStatus S = MCDisassembler::Success; 3769 3770 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3771 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3772 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3773 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3774 unsigned size = fieldFromInstruction(Insn, 10, 2); 3775 3776 unsigned align = 0; 3777 unsigned index = 0; 3778 switch (size) { 3779 default: 3780 return MCDisassembler::Fail; 3781 case 0: 3782 if (fieldFromInstruction(Insn, 4, 1)) 3783 return MCDisassembler::Fail; // UNDEFINED 3784 index = fieldFromInstruction(Insn, 5, 3); 3785 break; 3786 case 1: 3787 if (fieldFromInstruction(Insn, 5, 1)) 3788 return MCDisassembler::Fail; // UNDEFINED 3789 index = fieldFromInstruction(Insn, 6, 2); 3790 if (fieldFromInstruction(Insn, 4, 1)) 3791 align = 2; 3792 break; 3793 case 2: 3794 if (fieldFromInstruction(Insn, 6, 1)) 3795 return MCDisassembler::Fail; // UNDEFINED 3796 index = fieldFromInstruction(Insn, 7, 1); 3797 3798 switch (fieldFromInstruction(Insn, 4, 2)) { 3799 case 0: 3800 align = 0; break; 3801 case 3: 3802 align = 4; break; 3803 default: 3804 return MCDisassembler::Fail; 3805 } 3806 break; 3807 } 3808 3809 if (Rm != 0xF) { // Writeback 3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 } 3813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 Inst.addOperand(MCOperand::CreateImm(align)); 3816 if (Rm != 0xF) { 3817 if (Rm != 0xD) { 3818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 } else 3821 Inst.addOperand(MCOperand::CreateReg(0)); 3822 } 3823 3824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3825 return MCDisassembler::Fail; 3826 Inst.addOperand(MCOperand::CreateImm(index)); 3827 3828 return S; 3829} 3830 3831 3832static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3833 uint64_t Address, const void *Decoder) { 3834 DecodeStatus S = MCDisassembler::Success; 3835 3836 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3837 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3838 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3839 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3840 unsigned size = fieldFromInstruction(Insn, 10, 2); 3841 3842 unsigned align = 0; 3843 unsigned index = 0; 3844 unsigned inc = 1; 3845 switch (size) { 3846 default: 3847 return MCDisassembler::Fail; 3848 case 0: 3849 index = fieldFromInstruction(Insn, 5, 3); 3850 if (fieldFromInstruction(Insn, 4, 1)) 3851 align = 2; 3852 break; 3853 case 1: 3854 index = fieldFromInstruction(Insn, 6, 2); 3855 if (fieldFromInstruction(Insn, 4, 1)) 3856 align = 4; 3857 if (fieldFromInstruction(Insn, 5, 1)) 3858 inc = 2; 3859 break; 3860 case 2: 3861 if (fieldFromInstruction(Insn, 5, 1)) 3862 return MCDisassembler::Fail; // UNDEFINED 3863 index = fieldFromInstruction(Insn, 7, 1); 3864 if (fieldFromInstruction(Insn, 4, 1) != 0) 3865 align = 8; 3866 if (fieldFromInstruction(Insn, 6, 1)) 3867 inc = 2; 3868 break; 3869 } 3870 3871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3874 return MCDisassembler::Fail; 3875 if (Rm != 0xF) { // Writeback 3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3877 return MCDisassembler::Fail; 3878 } 3879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3880 return MCDisassembler::Fail; 3881 Inst.addOperand(MCOperand::CreateImm(align)); 3882 if (Rm != 0xF) { 3883 if (Rm != 0xD) { 3884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 } else 3887 Inst.addOperand(MCOperand::CreateReg(0)); 3888 } 3889 3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3893 return MCDisassembler::Fail; 3894 Inst.addOperand(MCOperand::CreateImm(index)); 3895 3896 return S; 3897} 3898 3899static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3900 uint64_t Address, const void *Decoder) { 3901 DecodeStatus S = MCDisassembler::Success; 3902 3903 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3904 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3905 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3906 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3907 unsigned size = fieldFromInstruction(Insn, 10, 2); 3908 3909 unsigned align = 0; 3910 unsigned index = 0; 3911 unsigned inc = 1; 3912 switch (size) { 3913 default: 3914 return MCDisassembler::Fail; 3915 case 0: 3916 index = fieldFromInstruction(Insn, 5, 3); 3917 if (fieldFromInstruction(Insn, 4, 1)) 3918 align = 2; 3919 break; 3920 case 1: 3921 index = fieldFromInstruction(Insn, 6, 2); 3922 if (fieldFromInstruction(Insn, 4, 1)) 3923 align = 4; 3924 if (fieldFromInstruction(Insn, 5, 1)) 3925 inc = 2; 3926 break; 3927 case 2: 3928 if (fieldFromInstruction(Insn, 5, 1)) 3929 return MCDisassembler::Fail; // UNDEFINED 3930 index = fieldFromInstruction(Insn, 7, 1); 3931 if (fieldFromInstruction(Insn, 4, 1) != 0) 3932 align = 8; 3933 if (fieldFromInstruction(Insn, 6, 1)) 3934 inc = 2; 3935 break; 3936 } 3937 3938 if (Rm != 0xF) { // Writeback 3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3940 return MCDisassembler::Fail; 3941 } 3942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3943 return MCDisassembler::Fail; 3944 Inst.addOperand(MCOperand::CreateImm(align)); 3945 if (Rm != 0xF) { 3946 if (Rm != 0xD) { 3947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3948 return MCDisassembler::Fail; 3949 } else 3950 Inst.addOperand(MCOperand::CreateReg(0)); 3951 } 3952 3953 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3954 return MCDisassembler::Fail; 3955 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3956 return MCDisassembler::Fail; 3957 Inst.addOperand(MCOperand::CreateImm(index)); 3958 3959 return S; 3960} 3961 3962 3963static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3964 uint64_t Address, const void *Decoder) { 3965 DecodeStatus S = MCDisassembler::Success; 3966 3967 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3968 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3969 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3970 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3971 unsigned size = fieldFromInstruction(Insn, 10, 2); 3972 3973 unsigned align = 0; 3974 unsigned index = 0; 3975 unsigned inc = 1; 3976 switch (size) { 3977 default: 3978 return MCDisassembler::Fail; 3979 case 0: 3980 if (fieldFromInstruction(Insn, 4, 1)) 3981 return MCDisassembler::Fail; // UNDEFINED 3982 index = fieldFromInstruction(Insn, 5, 3); 3983 break; 3984 case 1: 3985 if (fieldFromInstruction(Insn, 4, 1)) 3986 return MCDisassembler::Fail; // UNDEFINED 3987 index = fieldFromInstruction(Insn, 6, 2); 3988 if (fieldFromInstruction(Insn, 5, 1)) 3989 inc = 2; 3990 break; 3991 case 2: 3992 if (fieldFromInstruction(Insn, 4, 2)) 3993 return MCDisassembler::Fail; // UNDEFINED 3994 index = fieldFromInstruction(Insn, 7, 1); 3995 if (fieldFromInstruction(Insn, 6, 1)) 3996 inc = 2; 3997 break; 3998 } 3999 4000 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 4007 if (Rm != 0xF) { // Writeback 4008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 } 4011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 Inst.addOperand(MCOperand::CreateImm(align)); 4014 if (Rm != 0xF) { 4015 if (Rm != 0xD) { 4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4017 return MCDisassembler::Fail; 4018 } else 4019 Inst.addOperand(MCOperand::CreateReg(0)); 4020 } 4021 4022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4025 return MCDisassembler::Fail; 4026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 Inst.addOperand(MCOperand::CreateImm(index)); 4029 4030 return S; 4031} 4032 4033static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4034 uint64_t Address, const void *Decoder) { 4035 DecodeStatus S = MCDisassembler::Success; 4036 4037 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4038 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4039 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4040 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4041 unsigned size = fieldFromInstruction(Insn, 10, 2); 4042 4043 unsigned align = 0; 4044 unsigned index = 0; 4045 unsigned inc = 1; 4046 switch (size) { 4047 default: 4048 return MCDisassembler::Fail; 4049 case 0: 4050 if (fieldFromInstruction(Insn, 4, 1)) 4051 return MCDisassembler::Fail; // UNDEFINED 4052 index = fieldFromInstruction(Insn, 5, 3); 4053 break; 4054 case 1: 4055 if (fieldFromInstruction(Insn, 4, 1)) 4056 return MCDisassembler::Fail; // UNDEFINED 4057 index = fieldFromInstruction(Insn, 6, 2); 4058 if (fieldFromInstruction(Insn, 5, 1)) 4059 inc = 2; 4060 break; 4061 case 2: 4062 if (fieldFromInstruction(Insn, 4, 2)) 4063 return MCDisassembler::Fail; // UNDEFINED 4064 index = fieldFromInstruction(Insn, 7, 1); 4065 if (fieldFromInstruction(Insn, 6, 1)) 4066 inc = 2; 4067 break; 4068 } 4069 4070 if (Rm != 0xF) { // Writeback 4071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4072 return MCDisassembler::Fail; 4073 } 4074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4075 return MCDisassembler::Fail; 4076 Inst.addOperand(MCOperand::CreateImm(align)); 4077 if (Rm != 0xF) { 4078 if (Rm != 0xD) { 4079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4080 return MCDisassembler::Fail; 4081 } else 4082 Inst.addOperand(MCOperand::CreateReg(0)); 4083 } 4084 4085 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4086 return MCDisassembler::Fail; 4087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4088 return MCDisassembler::Fail; 4089 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4090 return MCDisassembler::Fail; 4091 Inst.addOperand(MCOperand::CreateImm(index)); 4092 4093 return S; 4094} 4095 4096 4097static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4098 uint64_t Address, const void *Decoder) { 4099 DecodeStatus S = MCDisassembler::Success; 4100 4101 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4102 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4103 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4104 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4105 unsigned size = fieldFromInstruction(Insn, 10, 2); 4106 4107 unsigned align = 0; 4108 unsigned index = 0; 4109 unsigned inc = 1; 4110 switch (size) { 4111 default: 4112 return MCDisassembler::Fail; 4113 case 0: 4114 if (fieldFromInstruction(Insn, 4, 1)) 4115 align = 4; 4116 index = fieldFromInstruction(Insn, 5, 3); 4117 break; 4118 case 1: 4119 if (fieldFromInstruction(Insn, 4, 1)) 4120 align = 8; 4121 index = fieldFromInstruction(Insn, 6, 2); 4122 if (fieldFromInstruction(Insn, 5, 1)) 4123 inc = 2; 4124 break; 4125 case 2: 4126 switch (fieldFromInstruction(Insn, 4, 2)) { 4127 case 0: 4128 align = 0; break; 4129 case 3: 4130 return MCDisassembler::Fail; 4131 default: 4132 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4133 } 4134 4135 index = fieldFromInstruction(Insn, 7, 1); 4136 if (fieldFromInstruction(Insn, 6, 1)) 4137 inc = 2; 4138 break; 4139 } 4140 4141 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4142 return MCDisassembler::Fail; 4143 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4144 return MCDisassembler::Fail; 4145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4146 return MCDisassembler::Fail; 4147 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4148 return MCDisassembler::Fail; 4149 4150 if (Rm != 0xF) { // Writeback 4151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4152 return MCDisassembler::Fail; 4153 } 4154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4155 return MCDisassembler::Fail; 4156 Inst.addOperand(MCOperand::CreateImm(align)); 4157 if (Rm != 0xF) { 4158 if (Rm != 0xD) { 4159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4160 return MCDisassembler::Fail; 4161 } else 4162 Inst.addOperand(MCOperand::CreateReg(0)); 4163 } 4164 4165 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4168 return MCDisassembler::Fail; 4169 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4172 return MCDisassembler::Fail; 4173 Inst.addOperand(MCOperand::CreateImm(index)); 4174 4175 return S; 4176} 4177 4178static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4179 uint64_t Address, const void *Decoder) { 4180 DecodeStatus S = MCDisassembler::Success; 4181 4182 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4183 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4184 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4185 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4186 unsigned size = fieldFromInstruction(Insn, 10, 2); 4187 4188 unsigned align = 0; 4189 unsigned index = 0; 4190 unsigned inc = 1; 4191 switch (size) { 4192 default: 4193 return MCDisassembler::Fail; 4194 case 0: 4195 if (fieldFromInstruction(Insn, 4, 1)) 4196 align = 4; 4197 index = fieldFromInstruction(Insn, 5, 3); 4198 break; 4199 case 1: 4200 if (fieldFromInstruction(Insn, 4, 1)) 4201 align = 8; 4202 index = fieldFromInstruction(Insn, 6, 2); 4203 if (fieldFromInstruction(Insn, 5, 1)) 4204 inc = 2; 4205 break; 4206 case 2: 4207 switch (fieldFromInstruction(Insn, 4, 2)) { 4208 case 0: 4209 align = 0; break; 4210 case 3: 4211 return MCDisassembler::Fail; 4212 default: 4213 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4214 } 4215 4216 index = fieldFromInstruction(Insn, 7, 1); 4217 if (fieldFromInstruction(Insn, 6, 1)) 4218 inc = 2; 4219 break; 4220 } 4221 4222 if (Rm != 0xF) { // Writeback 4223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4224 return MCDisassembler::Fail; 4225 } 4226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 Inst.addOperand(MCOperand::CreateImm(align)); 4229 if (Rm != 0xF) { 4230 if (Rm != 0xD) { 4231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4232 return MCDisassembler::Fail; 4233 } else 4234 Inst.addOperand(MCOperand::CreateReg(0)); 4235 } 4236 4237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 Inst.addOperand(MCOperand::CreateImm(index)); 4246 4247 return S; 4248} 4249 4250static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4251 uint64_t Address, const void *Decoder) { 4252 DecodeStatus S = MCDisassembler::Success; 4253 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4254 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4255 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4256 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4257 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4258 4259 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4260 S = MCDisassembler::SoftFail; 4261 4262 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4267 return MCDisassembler::Fail; 4268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4271 return MCDisassembler::Fail; 4272 4273 return S; 4274} 4275 4276static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4277 uint64_t Address, const void *Decoder) { 4278 DecodeStatus S = MCDisassembler::Success; 4279 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4280 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4281 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4282 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4283 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4284 4285 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4286 S = MCDisassembler::SoftFail; 4287 4288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4291 return MCDisassembler::Fail; 4292 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 4299 return S; 4300} 4301 4302static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4303 uint64_t Address, const void *Decoder) { 4304 DecodeStatus S = MCDisassembler::Success; 4305 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4306 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4307 4308 if (pred == 0xF) { 4309 pred = 0xE; 4310 S = MCDisassembler::SoftFail; 4311 } 4312 4313 if (mask == 0x0) { 4314 mask |= 0x8; 4315 S = MCDisassembler::SoftFail; 4316 } 4317 4318 Inst.addOperand(MCOperand::CreateImm(pred)); 4319 Inst.addOperand(MCOperand::CreateImm(mask)); 4320 return S; 4321} 4322 4323static DecodeStatus 4324DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4325 uint64_t Address, const void *Decoder) { 4326 DecodeStatus S = MCDisassembler::Success; 4327 4328 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4329 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4330 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4331 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4332 unsigned W = fieldFromInstruction(Insn, 21, 1); 4333 unsigned U = fieldFromInstruction(Insn, 23, 1); 4334 unsigned P = fieldFromInstruction(Insn, 24, 1); 4335 bool writeback = (W == 1) | (P == 0); 4336 4337 addr |= (U << 8) | (Rn << 9); 4338 4339 if (writeback && (Rn == Rt || Rn == Rt2)) 4340 Check(S, MCDisassembler::SoftFail); 4341 if (Rt == Rt2) 4342 Check(S, MCDisassembler::SoftFail); 4343 4344 // Rt 4345 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4346 return MCDisassembler::Fail; 4347 // Rt2 4348 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4349 return MCDisassembler::Fail; 4350 // Writeback operand 4351 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4352 return MCDisassembler::Fail; 4353 // addr 4354 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4355 return MCDisassembler::Fail; 4356 4357 return S; 4358} 4359 4360static DecodeStatus 4361DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4362 uint64_t Address, const void *Decoder) { 4363 DecodeStatus S = MCDisassembler::Success; 4364 4365 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4366 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4367 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4368 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4369 unsigned W = fieldFromInstruction(Insn, 21, 1); 4370 unsigned U = fieldFromInstruction(Insn, 23, 1); 4371 unsigned P = fieldFromInstruction(Insn, 24, 1); 4372 bool writeback = (W == 1) | (P == 0); 4373 4374 addr |= (U << 8) | (Rn << 9); 4375 4376 if (writeback && (Rn == Rt || Rn == Rt2)) 4377 Check(S, MCDisassembler::SoftFail); 4378 4379 // Writeback operand 4380 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4381 return MCDisassembler::Fail; 4382 // Rt 4383 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4384 return MCDisassembler::Fail; 4385 // Rt2 4386 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4387 return MCDisassembler::Fail; 4388 // addr 4389 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4390 return MCDisassembler::Fail; 4391 4392 return S; 4393} 4394 4395static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4396 uint64_t Address, const void *Decoder) { 4397 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4398 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4399 if (sign1 != sign2) return MCDisassembler::Fail; 4400 4401 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4402 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4403 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4404 Val |= sign1 << 12; 4405 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4406 4407 return MCDisassembler::Success; 4408} 4409 4410static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4411 uint64_t Address, 4412 const void *Decoder) { 4413 DecodeStatus S = MCDisassembler::Success; 4414 4415 // Shift of "asr #32" is not allowed in Thumb2 mode. 4416 if (Val == 0x20) S = MCDisassembler::SoftFail; 4417 Inst.addOperand(MCOperand::CreateImm(Val)); 4418 return S; 4419} 4420 4421static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4422 uint64_t Address, const void *Decoder) { 4423 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4424 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4425 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4426 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4427 4428 if (pred == 0xF) 4429 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4430 4431 DecodeStatus S = MCDisassembler::Success; 4432 4433 if (Rt == Rn || Rn == Rt2) 4434 S = MCDisassembler::SoftFail; 4435 4436 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4437 return MCDisassembler::Fail; 4438 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4439 return MCDisassembler::Fail; 4440 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4441 return MCDisassembler::Fail; 4442 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4443 return MCDisassembler::Fail; 4444 4445 return S; 4446} 4447 4448static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4449 uint64_t Address, const void *Decoder) { 4450 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4451 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4452 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4453 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4454 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4455 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4456 4457 DecodeStatus S = MCDisassembler::Success; 4458 4459 // VMOVv2f32 is ambiguous with these decodings. 4460 if (!(imm & 0x38) && cmode == 0xF) { 4461 Inst.setOpcode(ARM::VMOVv2f32); 4462 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4463 } 4464 4465 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4466 4467 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4468 return MCDisassembler::Fail; 4469 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4470 return MCDisassembler::Fail; 4471 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4472 4473 return S; 4474} 4475 4476static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4477 uint64_t Address, const void *Decoder) { 4478 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4479 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4480 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4481 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4482 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4483 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4484 4485 DecodeStatus S = MCDisassembler::Success; 4486 4487 // VMOVv4f32 is ambiguous with these decodings. 4488 if (!(imm & 0x38) && cmode == 0xF) { 4489 Inst.setOpcode(ARM::VMOVv4f32); 4490 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4491 } 4492 4493 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4494 4495 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4496 return MCDisassembler::Fail; 4497 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4498 return MCDisassembler::Fail; 4499 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4500 4501 return S; 4502} 4503 4504static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4505 const void *Decoder) 4506{ 4507 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4508 if (Imm > 4) return MCDisassembler::Fail; 4509 Inst.addOperand(MCOperand::CreateImm(Imm)); 4510 return MCDisassembler::Success; 4511} 4512 4513static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4514 uint64_t Address, const void *Decoder) { 4515 DecodeStatus S = MCDisassembler::Success; 4516 4517 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4518 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4519 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4520 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4521 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4522 4523 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4524 S = MCDisassembler::SoftFail; 4525 4526 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4527 return MCDisassembler::Fail; 4528 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4529 return MCDisassembler::Fail; 4530 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4531 return MCDisassembler::Fail; 4532 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4533 return MCDisassembler::Fail; 4534 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4535 return MCDisassembler::Fail; 4536 4537 return S; 4538} 4539 4540static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4541 uint64_t Address, const void *Decoder) { 4542 4543 DecodeStatus S = MCDisassembler::Success; 4544 4545 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4546 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4547 unsigned cop = fieldFromInstruction(Val, 8, 4); 4548 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4549 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4550 4551 if ((cop & ~0x1) == 0xa) 4552 return MCDisassembler::Fail; 4553 4554 if (Rt == Rt2) 4555 S = MCDisassembler::SoftFail; 4556 4557 Inst.addOperand(MCOperand::CreateImm(cop)); 4558 Inst.addOperand(MCOperand::CreateImm(opc1)); 4559 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4562 return MCDisassembler::Fail; 4563 Inst.addOperand(MCOperand::CreateImm(CRm)); 4564 4565 return S; 4566} 4567 4568