1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * ASPEED FMC/SPI Controller driver 4 * 5 * Copyright (c) 2022 ASPEED Corporation. 6 * Copyright (c) 2022 IBM Corporation. 7 * 8 * Author: 9 * Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> 10 * Cedric Le Goater <clg@kaod.org> 11 */ 12 13#include <asm/io.h> 14#include <clk.h> 15#include <common.h> 16#include <dm.h> 17#include <dm/device_compat.h> 18#include <linux/bitops.h> 19#include <linux/bug.h> 20#include <linux/err.h> 21#include <linux/iopoll.h> 22#include <linux/kernel.h> 23#include <linux/mtd/spi-nor.h> 24#include <linux/sizes.h> 25#include <malloc.h> 26#include <spi.h> 27#include <spi-mem.h> 28 29#define ASPEED_SPI_MAX_CS 5 30 31#define CTRL_IO_SINGLE_DATA 0 32#define CTRL_IO_QUAD_DATA BIT(30) 33#define CTRL_IO_DUAL_DATA BIT(29) 34 35#define CTRL_IO_MODE_USER GENMASK(1, 0) 36#define CTRL_IO_MODE_CMD_READ BIT(0) 37#define CTRL_IO_MODE_CMD_WRITE BIT(1) 38#define CTRL_STOP_ACTIVE BIT(2) 39 40struct aspeed_spi_regs { 41 u32 conf; /* 0x00 CE Type Setting */ 42 u32 ctrl; /* 0x04 CE Control */ 43 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 44 u32 cmd_ctrl; /* 0x0c Command Control */ 45 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x20 CEx Control */ 46 u32 _reserved0[3]; /* .. */ 47 u32 segment_addr[ASPEED_SPI_MAX_CS]; /* 0x30 .. 0x40 Segment Address */ 48 u32 _reserved1[3]; /* .. */ 49 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */ 50 u32 _reserved2[11]; /* .. */ 51 u32 dma_ctrl; /* 0x80 DMA Control/Status */ 52 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 53 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 54 u32 dma_len; /* 0x8c DMA Length Register */ 55 u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 56 u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */ 57}; 58 59struct aspeed_spi_plat { 60 u8 max_cs; 61 void __iomem *ahb_base; /* AHB address base for all flash devices. */ 62 fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */ 63 u32 hclk_rate; /* AHB clock rate */ 64}; 65 66struct aspeed_spi_flash { 67 void __iomem *ahb_base; 68 u32 ahb_decoded_sz; 69 u32 ce_ctrl_user; 70 u32 ce_ctrl_read; 71 u32 max_freq; 72}; 73 74struct aspeed_spi_priv { 75 u32 num_cs; 76 struct aspeed_spi_regs *regs; 77 struct aspeed_spi_info *info; 78 struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 79 bool fixed_decoded_range; 80}; 81 82struct aspeed_spi_info { 83 u32 io_mode_mask; 84 u32 max_bus_width; 85 u32 min_decoded_sz; 86 u32 clk_ctrl_mask; 87 void (*set_4byte)(struct udevice *bus, u32 cs); 88 u32 (*segment_start)(struct udevice *bus, u32 reg); 89 u32 (*segment_end)(struct udevice *bus, u32 reg); 90 u32 (*segment_reg)(u32 start, u32 end); 91 int (*adjust_decoded_sz)(struct udevice *bus); 92 u32 (*get_clk_setting)(struct udevice *dev, uint hz); 93}; 94 95struct aspeed_spi_decoded_range { 96 u32 cs; 97 u32 ahb_base; 98 u32 sz; 99}; 100 101static const struct aspeed_spi_info ast2400_spi_info; 102static const struct aspeed_spi_info ast2500_fmc_info; 103static const struct aspeed_spi_info ast2500_spi_info; 104static int aspeed_spi_decoded_range_config(struct udevice *bus); 105static int aspeed_spi_trim_decoded_size(struct udevice *bus); 106 107static u32 aspeed_spi_get_io_mode(u32 bus_width) 108{ 109 switch (bus_width) { 110 case 1: 111 return CTRL_IO_SINGLE_DATA; 112 case 2: 113 return CTRL_IO_DUAL_DATA; 114 case 4: 115 return CTRL_IO_QUAD_DATA; 116 default: 117 /* keep in default value */ 118 return CTRL_IO_SINGLE_DATA; 119 } 120} 121 122static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg) 123{ 124 struct aspeed_spi_plat *plat = dev_get_plat(bus); 125 u32 start_offset = ((reg >> 16) & 0xff) << 23; 126 127 if (start_offset == 0) 128 return (u32)plat->ahb_base; 129 130 return (u32)plat->ahb_base + start_offset; 131} 132 133static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg) 134{ 135 struct aspeed_spi_plat *plat = dev_get_plat(bus); 136 u32 end_offset = ((reg >> 24) & 0xff) << 23; 137 138 /* Meaningless end_offset, set to physical ahb base. */ 139 if (end_offset == 0) 140 return (u32)plat->ahb_base; 141 142 return (u32)plat->ahb_base + end_offset; 143} 144 145static u32 ast2400_spi_segment_reg(u32 start, u32 end) 146{ 147 if (start == end) 148 return 0; 149 150 return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24); 151} 152 153static void ast2400_fmc_chip_set_4byte(struct udevice *bus, u32 cs) 154{ 155 struct aspeed_spi_priv *priv = dev_get_priv(bus); 156 u32 reg_val; 157 158 reg_val = readl(&priv->regs->ctrl); 159 reg_val |= 0x1 << cs; 160 writel(reg_val, &priv->regs->ctrl); 161} 162 163static void ast2400_spi_chip_set_4byte(struct udevice *bus, u32 cs) 164{ 165 struct aspeed_spi_priv *priv = dev_get_priv(bus); 166 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 167 168 flash->ce_ctrl_read |= BIT(13); 169 writel(flash->ce_ctrl_read, &priv->regs->ctrl); 170} 171 172/* Transfer maximum clock frequency to register setting */ 173static u32 ast2400_get_clk_setting(struct udevice *dev, uint max_hz) 174{ 175 struct aspeed_spi_plat *plat = dev_get_plat(dev->parent); 176 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 177 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 178 u32 hclk_clk = plat->hclk_rate; 179 u32 hclk_div = 0x0000; /* default value */ 180 u32 i; 181 bool found = false; 182 /* HCLK/1 .. HCLK/16 */ 183 u32 hclk_masks[] = {15, 7, 14, 6, 13, 5, 12, 4, 184 11, 3, 10, 2, 9, 1, 8, 0}; 185 186 /* FMC/SPIR10[11:8] */ 187 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 188 if (hclk_clk / (i + 1) <= max_hz) { 189 found = true; 190 break; 191 } 192 } 193 194 if (found) { 195 hclk_div = hclk_masks[i] << 8; 196 priv->flashes[slave_plat->cs].max_freq = hclk_clk / (i + 1); 197 } 198 199 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no", 200 hclk_clk, max_hz); 201 202 if (found) { 203 dev_dbg(dev, "h_div: %d (mask %x), speed: %d\n", 204 i + 1, hclk_masks[i], priv->flashes[slave_plat->cs].max_freq); 205 } 206 207 return hclk_div; 208} 209 210static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg) 211{ 212 struct aspeed_spi_plat *plat = dev_get_plat(bus); 213 u32 start_offset = ((reg >> 16) & 0xff) << 23; 214 215 if (start_offset == 0) 216 return (u32)plat->ahb_base; 217 218 return (u32)plat->ahb_base + start_offset; 219} 220 221static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg) 222{ 223 struct aspeed_spi_plat *plat = dev_get_plat(bus); 224 u32 end_offset = ((reg >> 24) & 0xff) << 23; 225 226 /* Meaningless end_offset, set to physical ahb base. */ 227 if (end_offset == 0) 228 return (u32)plat->ahb_base; 229 230 return (u32)plat->ahb_base + end_offset; 231} 232 233static u32 ast2500_spi_segment_reg(u32 start, u32 end) 234{ 235 if (start == end) 236 return 0; 237 238 return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24); 239} 240 241static void ast2500_spi_chip_set_4byte(struct udevice *bus, u32 cs) 242{ 243 struct aspeed_spi_priv *priv = dev_get_priv(bus); 244 u32 reg_val; 245 246 reg_val = readl(&priv->regs->ctrl); 247 reg_val |= 0x1 << cs; 248 writel(reg_val, &priv->regs->ctrl); 249} 250 251/* 252 * For AST2500, the minimum address decoded size for each CS 253 * is 8MB instead of zero. This address decoded size is 254 * mandatory for each CS no matter whether it will be used. 255 * This is a HW limitation. 256 */ 257static int ast2500_adjust_decoded_size(struct udevice *bus) 258{ 259 struct aspeed_spi_plat *plat = dev_get_plat(bus); 260 struct aspeed_spi_priv *priv = dev_get_priv(bus); 261 struct aspeed_spi_flash *flashes = &priv->flashes[0]; 262 int ret; 263 int i; 264 int cs; 265 u32 pre_sz; 266 u32 lack_sz; 267 268 /* Assign min_decoded_sz to unused CS. */ 269 for (cs = priv->num_cs; cs < plat->max_cs; cs++) 270 flashes[cs].ahb_decoded_sz = priv->info->min_decoded_sz; 271 272 /* 273 * If command mode or normal mode is used, the start address of a 274 * decoded range should be multiple of its related flash size. 275 * Namely, the total decoded size from flash 0 to flash N should 276 * be multiple of the size of flash (N + 1). 277 */ 278 for (cs = priv->num_cs - 1; cs >= 0; cs--) { 279 pre_sz = 0; 280 for (i = 0; i < cs; i++) 281 pre_sz += flashes[i].ahb_decoded_sz; 282 283 if (flashes[cs].ahb_decoded_sz != 0 && 284 (pre_sz % flashes[cs].ahb_decoded_sz) != 0) { 285 lack_sz = flashes[cs].ahb_decoded_sz - 286 (pre_sz % flashes[cs].ahb_decoded_sz); 287 flashes[0].ahb_decoded_sz += lack_sz; 288 } 289 } 290 291 ret = aspeed_spi_trim_decoded_size(bus); 292 if (ret != 0) 293 return ret; 294 295 return 0; 296} 297 298static u32 ast2500_get_clk_setting(struct udevice *dev, uint max_hz) 299{ 300 struct aspeed_spi_plat *plat = dev_get_plat(dev->parent); 301 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 302 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 303 u32 hclk_clk = plat->hclk_rate; 304 u32 hclk_div = 0x0000; /* default value */ 305 u32 i; 306 bool found = false; 307 /* HCLK/1 .. HCLK/16 */ 308 u32 hclk_masks[] = {15, 7, 14, 6, 13, 5, 12, 4, 309 11, 3, 10, 2, 9, 1, 8, 0}; 310 311 /* FMC/SPIR10[11:8] */ 312 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 313 if (hclk_clk / (i + 1) <= max_hz) { 314 found = true; 315 priv->flashes[slave_plat->cs].max_freq = 316 hclk_clk / (i + 1); 317 break; 318 } 319 } 320 321 if (found) { 322 hclk_div = hclk_masks[i] << 8; 323 goto end; 324 } 325 326 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 327 if (hclk_clk / ((i + 1) * 4) <= max_hz) { 328 found = true; 329 priv->flashes[slave_plat->cs].max_freq = 330 hclk_clk / ((i + 1) * 4); 331 break; 332 } 333 } 334 335 if (found) 336 hclk_div = BIT(13) | (hclk_masks[i] << 8); 337 338end: 339 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no", 340 hclk_clk, max_hz); 341 342 if (found) { 343 dev_dbg(dev, "h_div: %d (mask %x), speed: %d\n", 344 i + 1, hclk_masks[i], priv->flashes[slave_plat->cs].max_freq); 345 } 346 347 return hclk_div; 348} 349 350static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg) 351{ 352 struct aspeed_spi_plat *plat = dev_get_plat(bus); 353 u32 start_offset = (reg << 16) & 0x0ff00000; 354 355 if (start_offset == 0) 356 return (u32)plat->ahb_base; 357 358 return (u32)plat->ahb_base + start_offset; 359} 360 361static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg) 362{ 363 struct aspeed_spi_plat *plat = dev_get_plat(bus); 364 u32 end_offset = reg & 0x0ff00000; 365 366 /* Meaningless end_offset, set to physical ahb base. */ 367 if (end_offset == 0) 368 return (u32)plat->ahb_base; 369 370 return (u32)plat->ahb_base + end_offset + 0x100000; 371} 372 373static u32 ast2600_spi_segment_reg(u32 start, u32 end) 374{ 375 if (start == end) 376 return 0; 377 378 return ((start & 0x0ff00000) >> 16) | ((end - 0x100000) & 0x0ff00000); 379} 380 381static void ast2600_spi_chip_set_4byte(struct udevice *bus, u32 cs) 382{ 383 struct aspeed_spi_priv *priv = dev_get_priv(bus); 384 u32 reg_val; 385 386 reg_val = readl(&priv->regs->ctrl); 387 reg_val |= 0x11 << cs; 388 writel(reg_val, &priv->regs->ctrl); 389} 390 391static int ast2600_adjust_decoded_size(struct udevice *bus) 392{ 393 struct aspeed_spi_plat *plat = dev_get_plat(bus); 394 struct aspeed_spi_priv *priv = dev_get_priv(bus); 395 struct aspeed_spi_flash *flashes = &priv->flashes[0]; 396 int ret; 397 int i; 398 int cs; 399 u32 pre_sz; 400 u32 lack_sz; 401 402 /* Close unused CS. */ 403 for (cs = priv->num_cs; cs < plat->max_cs; cs++) 404 flashes[cs].ahb_decoded_sz = 0; 405 406 /* 407 * If command mode or normal mode is used, the start address of a 408 * decoded range should be multiple of its related flash size. 409 * Namely, the total decoded size from flash 0 to flash N should 410 * be multiple of the size of flash (N + 1). 411 */ 412 for (cs = priv->num_cs - 1; cs >= 0; cs--) { 413 pre_sz = 0; 414 for (i = 0; i < cs; i++) 415 pre_sz += flashes[i].ahb_decoded_sz; 416 417 if (flashes[cs].ahb_decoded_sz != 0 && 418 (pre_sz % flashes[cs].ahb_decoded_sz) != 0) { 419 lack_sz = flashes[cs].ahb_decoded_sz - 420 (pre_sz % flashes[cs].ahb_decoded_sz); 421 flashes[0].ahb_decoded_sz += lack_sz; 422 } 423 } 424 425 ret = aspeed_spi_trim_decoded_size(bus); 426 if (ret != 0) 427 return ret; 428 429 return 0; 430} 431 432static u32 ast2600_get_clk_setting(struct udevice *dev, uint max_hz) 433{ 434 struct aspeed_spi_plat *plat = dev_get_plat(dev->parent); 435 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 436 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 437 u32 hclk_clk = plat->hclk_rate; 438 u32 hclk_div = 0x0400; /* default value */ 439 u32 i, j; 440 bool found = false; 441 /* HCLK/1 .. HCLK/16 */ 442 u32 hclk_masks[] = {15, 7, 14, 6, 13, 5, 12, 4, 443 11, 3, 10, 2, 9, 1, 8, 0}; 444 445 /* FMC/SPIR10[27:24] */ 446 for (j = 0; j < 0xf; j++) { 447 /* FMC/SPIR10[11:8] */ 448 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 449 if (i == 0 && j == 0) 450 continue; 451 452 if (hclk_clk / (i + 1 + (j * 16)) <= max_hz) { 453 found = true; 454 break; 455 } 456 } 457 458 if (found) { 459 hclk_div = ((j << 24) | hclk_masks[i] << 8); 460 priv->flashes[slave_plat->cs].max_freq = 461 hclk_clk / (i + 1 + j * 16); 462 break; 463 } 464 } 465 466 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no", 467 hclk_clk, max_hz); 468 469 if (found) { 470 dev_dbg(dev, "base_clk: %d, h_div: %d (mask %x), speed: %d\n", 471 j, i + 1, hclk_masks[i], priv->flashes[slave_plat->cs].max_freq); 472 } 473 474 return hclk_div; 475} 476 477/* 478 * As the flash size grows up, we need to trim some decoded 479 * size if needed for the sake of conforming the maximum 480 * decoded size. We trim the decoded size from the largest 481 * CS in order to avoid affecting the default boot up sequence 482 * from CS0 where command mode or normal mode is used. 483 * Notice, if a CS decoded size is trimmed, command mode may 484 * not work perfectly on that CS. 485 */ 486static int aspeed_spi_trim_decoded_size(struct udevice *bus) 487{ 488 struct aspeed_spi_plat *plat = dev_get_plat(bus); 489 struct aspeed_spi_priv *priv = dev_get_priv(bus); 490 struct aspeed_spi_flash *flashes = &priv->flashes[0]; 491 u32 total_sz; 492 int cs = plat->max_cs - 1; 493 u32 i; 494 495 do { 496 total_sz = 0; 497 for (i = 0; i < plat->max_cs; i++) 498 total_sz += flashes[i].ahb_decoded_sz; 499 500 if (flashes[cs].ahb_decoded_sz <= priv->info->min_decoded_sz) 501 cs--; 502 503 if (cs < 0) 504 return -ENOMEM; 505 506 if (total_sz > plat->ahb_sz) { 507 flashes[cs].ahb_decoded_sz -= 508 priv->info->min_decoded_sz; 509 total_sz -= priv->info->min_decoded_sz; 510 } 511 } while (total_sz > plat->ahb_sz); 512 513 return 0; 514} 515 516static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 517 size_t len) 518{ 519 size_t offset = 0; 520 521 if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && 522 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 523 readsl(ahb_base, buf, len >> 2); 524 offset = len & ~0x3; 525 len -= offset; 526 } 527 528 readsb(ahb_base, (u8 *)buf + offset, len); 529 530 return 0; 531} 532 533static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 534 size_t len) 535{ 536 size_t offset = 0; 537 538 if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && 539 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 540 writesl(ahb_base, buf, len >> 2); 541 offset = len & ~0x3; 542 len -= offset; 543 } 544 545 writesb(ahb_base, (u8 *)buf + offset, len); 546 547 return 0; 548} 549 550/* 551 * Currently, only support 1-1-1, 1-1-2 or 1-1-4 552 * SPI NOR flash operation format. 553 */ 554static bool aspeed_spi_supports_op(struct spi_slave *slave, 555 const struct spi_mem_op *op) 556{ 557 struct udevice *bus = slave->dev->parent; 558 struct aspeed_spi_priv *priv = dev_get_priv(bus); 559 560 if (op->cmd.buswidth > 1) 561 return false; 562 563 if (op->addr.nbytes != 0) { 564 if (op->addr.buswidth > 1) 565 return false; 566 if (op->addr.nbytes < 3 || op->addr.nbytes > 4) 567 return false; 568 } 569 570 if (op->dummy.nbytes != 0) { 571 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7) 572 return false; 573 } 574 575 if (op->data.nbytes != 0 && 576 op->data.buswidth > priv->info->max_bus_width) 577 return false; 578 579 if (!spi_mem_default_supports_op(slave, op)) 580 return false; 581 582 return true; 583} 584 585static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, 586 const struct spi_mem_op *op) 587{ 588 struct udevice *dev = slave->dev; 589 struct udevice *bus = dev->parent; 590 struct aspeed_spi_priv *priv = dev_get_priv(bus); 591 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); 592 u32 cs = slave_plat->cs; 593 u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; 594 u32 ce_ctrl_val; 595 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 596 u8 dummy_data[16] = {0}; 597 u8 addr[4] = {0}; 598 int i; 599 600 dev_dbg(dev, "cmd:%x(%d),addr:%llx(%d),dummy:%d(%d),data_len:0x%x(%d)\n", 601 op->cmd.opcode, op->cmd.buswidth, op->addr.val, 602 op->addr.buswidth, op->dummy.nbytes, op->dummy.buswidth, 603 op->data.nbytes, op->data.buswidth); 604 605 if (priv->info == &ast2400_spi_info) 606 ce_ctrl_reg = (u32)&priv->regs->ctrl; 607 608 /* 609 * Set controller to 4-byte address mode 610 * if flash is in 4-byte address mode. 611 */ 612 if (op->cmd.opcode == SPINOR_OP_EN4B) 613 priv->info->set_4byte(bus, cs); 614 615 /* Start user mode */ 616 ce_ctrl_val = flash->ce_ctrl_user; 617 writel(ce_ctrl_val, ce_ctrl_reg); 618 ce_ctrl_val &= (~CTRL_STOP_ACTIVE); 619 writel(ce_ctrl_val, ce_ctrl_reg); 620 621 /* Send command */ 622 aspeed_spi_write_to_ahb(flash->ahb_base, &op->cmd.opcode, 1); 623 624 /* Send address */ 625 for (i = op->addr.nbytes; i > 0; i--) { 626 addr[op->addr.nbytes - i] = 627 ((u32)op->addr.val >> ((i - 1) * 8)) & 0xff; 628 } 629 630 /* Change io_mode */ 631 ce_ctrl_val &= ~priv->info->io_mode_mask; 632 ce_ctrl_val |= aspeed_spi_get_io_mode(op->addr.buswidth); 633 writel(ce_ctrl_val, ce_ctrl_reg); 634 aspeed_spi_write_to_ahb(flash->ahb_base, addr, op->addr.nbytes); 635 636 /* Send dummy cycles */ 637 aspeed_spi_write_to_ahb(flash->ahb_base, dummy_data, op->dummy.nbytes); 638 639 /* Change io_mode */ 640 ce_ctrl_val &= ~priv->info->io_mode_mask; 641 ce_ctrl_val |= aspeed_spi_get_io_mode(op->data.buswidth); 642 writel(ce_ctrl_val, ce_ctrl_reg); 643 644 /* Send data */ 645 if (op->data.dir == SPI_MEM_DATA_OUT) { 646 aspeed_spi_write_to_ahb(flash->ahb_base, op->data.buf.out, 647 op->data.nbytes); 648 } else { 649 aspeed_spi_read_from_ahb(flash->ahb_base, op->data.buf.in, 650 op->data.nbytes); 651 } 652 653 ce_ctrl_val |= CTRL_STOP_ACTIVE; 654 writel(ce_ctrl_val, ce_ctrl_reg); 655 656 /* Restore controller setting. */ 657 writel(flash->ce_ctrl_read, ce_ctrl_reg); 658 659 return 0; 660} 661 662static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) 663{ 664 int ret = 0; 665 struct udevice *dev = desc->slave->dev; 666 struct udevice *bus = dev->parent; 667 struct aspeed_spi_priv *priv = dev_get_priv(bus); 668 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 669 const struct aspeed_spi_info *info = priv->info; 670 struct spi_mem_op op_tmpl = desc->info.op_tmpl; 671 u32 i; 672 u32 cs = slave_plat->cs; 673 u32 cmd_io_conf; 674 u32 ce_ctrl_reg; 675 676 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { 677 /* 678 * dirmap_write is not supported currently due to a HW 679 * limitation for command write mode: The written data 680 * length should be multiple of 4-byte. 681 */ 682 return -EOPNOTSUPP; 683 } 684 685 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; 686 if (info == &ast2400_spi_info) 687 ce_ctrl_reg = (u32)&priv->regs->ctrl; 688 689 if (desc->info.length > 0x1000000) 690 priv->info->set_4byte(bus, cs); 691 692 /* AST2400 SPI1 doesn't have decoded address segment register. */ 693 if (info != &ast2400_spi_info) { 694 priv->flashes[cs].ahb_decoded_sz = desc->info.length; 695 696 for (i = 0; i < priv->num_cs; i++) { 697 dev_dbg(dev, "cs: %d, sz: 0x%x\n", i, 698 priv->flashes[cs].ahb_decoded_sz); 699 } 700 701 ret = aspeed_spi_decoded_range_config(bus); 702 if (ret) 703 return ret; 704 } 705 706 cmd_io_conf = aspeed_spi_get_io_mode(op_tmpl.data.buswidth) | 707 op_tmpl.cmd.opcode << 16 | 708 ((op_tmpl.dummy.nbytes) & 0x3) << 6 | 709 ((op_tmpl.dummy.nbytes) & 0x4) << 14 | 710 CTRL_IO_MODE_CMD_READ; 711 712 priv->flashes[cs].ce_ctrl_read &= priv->info->clk_ctrl_mask; 713 priv->flashes[cs].ce_ctrl_read |= cmd_io_conf; 714 715 writel(priv->flashes[cs].ce_ctrl_read, ce_ctrl_reg); 716 717 dev_dbg(dev, "read bus width: %d ce_ctrl_val: 0x%08x\n", 718 op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read); 719 720 return ret; 721} 722 723static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, 724 u64 offs, size_t len, void *buf) 725{ 726 struct udevice *dev = desc->slave->dev; 727 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 728 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 729 u32 cs = slave_plat->cs; 730 int ret; 731 732 dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n", 733 desc->info.op_tmpl.cmd.opcode, offs, len); 734 735 if (priv->flashes[cs].ahb_decoded_sz < offs + len || 736 (offs % 4) != 0) { 737 ret = aspeed_spi_exec_op_user_mode(desc->slave, 738 &desc->info.op_tmpl); 739 if (ret != 0) 740 return 0; 741 } else { 742 memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len); 743 } 744 745 return len; 746} 747 748static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 749{ 750 struct udevice *bus = dev->parent; 751 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 752 struct aspeed_spi_plat *plat = dev_get_plat(bus); 753 struct aspeed_spi_priv *priv = dev_get_priv(bus); 754 u32 cs = slave_plat->cs; 755 756 if (cs >= plat->max_cs) { 757 dev_err(dev, "invalid CS %u\n", cs); 758 return NULL; 759 } 760 761 return &priv->flashes[cs]; 762} 763 764static void aspeed_spi_decoded_base_calculate(struct udevice *bus) 765{ 766 struct aspeed_spi_plat *plat = dev_get_plat(bus); 767 struct aspeed_spi_priv *priv = dev_get_priv(bus); 768 u32 cs; 769 770 if (priv->fixed_decoded_range) 771 return; 772 773 priv->flashes[0].ahb_base = plat->ahb_base; 774 775 for (cs = 1; cs < plat->max_cs; cs++) { 776 priv->flashes[cs].ahb_base = 777 priv->flashes[cs - 1].ahb_base + 778 priv->flashes[cs - 1].ahb_decoded_sz; 779 } 780} 781 782static void aspeed_spi_decoded_range_set(struct udevice *bus) 783{ 784 struct aspeed_spi_plat *plat = dev_get_plat(bus); 785 struct aspeed_spi_priv *priv = dev_get_priv(bus); 786 u32 decoded_reg_val; 787 u32 start_addr, end_addr; 788 u32 cs; 789 790 for (cs = 0; cs < plat->max_cs; cs++) { 791 start_addr = (u32)priv->flashes[cs].ahb_base; 792 end_addr = (u32)priv->flashes[cs].ahb_base + 793 priv->flashes[cs].ahb_decoded_sz; 794 795 decoded_reg_val = priv->info->segment_reg(start_addr, end_addr); 796 797 writel(decoded_reg_val, &priv->regs->segment_addr[cs]); 798 799 dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n", 800 cs, decoded_reg_val, start_addr, end_addr); 801 } 802} 803 804static int aspeed_spi_decoded_range_config(struct udevice *bus) 805{ 806 int ret = 0; 807 struct aspeed_spi_priv *priv = dev_get_priv(bus); 808 809 if (priv->info->adjust_decoded_sz && 810 !priv->fixed_decoded_range) { 811 ret = priv->info->adjust_decoded_sz(bus); 812 if (ret != 0) 813 return ret; 814 } 815 816 aspeed_spi_decoded_base_calculate(bus); 817 aspeed_spi_decoded_range_set(bus); 818 819 return ret; 820} 821 822static int aspeed_spi_decoded_ranges_sanity(struct udevice *bus) 823{ 824 struct aspeed_spi_plat *plat = dev_get_plat(bus); 825 struct aspeed_spi_priv *priv = dev_get_priv(bus); 826 u32 cs; 827 u32 total_sz = 0; 828 829 /* Check overall size. */ 830 for (cs = 0; cs < plat->max_cs; cs++) 831 total_sz += priv->flashes[cs].ahb_decoded_sz; 832 833 if (total_sz > plat->ahb_sz) { 834 dev_err(bus, "invalid total size 0x%08x\n", total_sz); 835 return -EINVAL; 836 } 837 838 /* Check each decoded range size for AST2500. */ 839 if (priv->info == &ast2500_fmc_info || 840 priv->info == &ast2500_spi_info) { 841 for (cs = 0; cs < plat->max_cs; cs++) { 842 if (priv->flashes[cs].ahb_decoded_sz < 843 priv->info->min_decoded_sz) { 844 dev_err(bus, "insufficient decoded range.\n"); 845 return -EINVAL; 846 } 847 } 848 } 849 850 /* 851 * Check overlay. Here, we assume the deccded ranges and 852 * address base are monotonic increasing with CE#. 853 */ 854 for (cs = plat->max_cs - 1; cs > 0; cs--) { 855 if ((u32)priv->flashes[cs].ahb_base != 0 && 856 (u32)priv->flashes[cs].ahb_base < 857 (u32)priv->flashes[cs - 1].ahb_base + 858 priv->flashes[cs - 1].ahb_decoded_sz) { 859 dev_err(bus, "decoded range overlay 0x%08x 0x%08x\n", 860 (u32)priv->flashes[cs].ahb_base, 861 (u32)priv->flashes[cs - 1].ahb_base); 862 return -EINVAL; 863 } 864 } 865 866 return 0; 867} 868 869static int aspeed_spi_read_fixed_decoded_ranges(struct udevice *bus) 870{ 871 int ret = 0; 872 struct aspeed_spi_plat *plat = dev_get_plat(bus); 873 struct aspeed_spi_priv *priv = dev_get_priv(bus); 874 const char *range_prop = "decoded-ranges"; 875 struct aspeed_spi_decoded_range ranges[ASPEED_SPI_MAX_CS]; 876 const struct property *prop; 877 u32 prop_sz; 878 u32 count; 879 u32 i; 880 881 priv->fixed_decoded_range = false; 882 883 prop = dev_read_prop(bus, range_prop, &prop_sz); 884 if (!prop) 885 return 0; 886 887 count = prop_sz / sizeof(struct aspeed_spi_decoded_range); 888 if (count > plat->max_cs || count < priv->num_cs) { 889 dev_err(bus, "invalid '%s' property %d %d\n", 890 range_prop, count, priv->num_cs); 891 return -EINVAL; 892 } 893 894 ret = dev_read_u32_array(bus, range_prop, (u32 *)ranges, count * 3); 895 if (ret) 896 return ret; 897 898 for (i = 0; i < count; i++) { 899 priv->flashes[ranges[i].cs].ahb_base = 900 (void __iomem *)ranges[i].ahb_base; 901 priv->flashes[ranges[i].cs].ahb_decoded_sz = 902 ranges[i].sz; 903 } 904 905 for (i = 0; i < plat->max_cs; i++) { 906 dev_dbg(bus, "ahb_base: 0x%p, size: 0x%08x\n", 907 priv->flashes[i].ahb_base, 908 priv->flashes[i].ahb_decoded_sz); 909 } 910 911 ret = aspeed_spi_decoded_ranges_sanity(bus); 912 if (ret != 0) 913 return ret; 914 915 priv->fixed_decoded_range = true; 916 917 return 0; 918} 919 920/* 921 * Initialize SPI controller for each chip select. 922 * Here, only the minimum decode range is configured 923 * in order to get device (SPI NOR flash) information 924 * at the early stage. 925 */ 926static int aspeed_spi_ctrl_init(struct udevice *bus) 927{ 928 int ret; 929 struct aspeed_spi_plat *plat = dev_get_plat(bus); 930 struct aspeed_spi_priv *priv = dev_get_priv(bus); 931 u32 cs; 932 u32 reg_val; 933 u32 decoded_sz; 934 935 /* Enable write capability for all CS. */ 936 reg_val = readl(&priv->regs->conf); 937 if (priv->info == &ast2400_spi_info) { 938 writel(reg_val | BIT(0), &priv->regs->conf); 939 } else { 940 writel(reg_val | (GENMASK(plat->max_cs - 1, 0) << 16), 941 &priv->regs->conf); 942 } 943 944 memset(priv->flashes, 0x0, 945 sizeof(struct aspeed_spi_flash) * ASPEED_SPI_MAX_CS); 946 947 /* Initial user mode. */ 948 for (cs = 0; cs < priv->num_cs; cs++) { 949 priv->flashes[cs].ce_ctrl_user &= priv->info->clk_ctrl_mask; 950 priv->flashes[cs].ce_ctrl_user |= 951 (CTRL_STOP_ACTIVE | CTRL_IO_MODE_USER); 952 } 953 954 /* 955 * SPI1 on AST2400 only supports CS0. 956 * It is unnecessary to configure segment address register. 957 */ 958 if (priv->info == &ast2400_spi_info) { 959 priv->flashes[cs].ahb_base = plat->ahb_base; 960 priv->flashes[cs].ahb_decoded_sz = 0x10000000; 961 return 0; 962 } 963 964 965 ret = aspeed_spi_read_fixed_decoded_ranges(bus); 966 if (ret != 0) 967 return ret; 968 969 if (!priv->fixed_decoded_range) { 970 /* Assign basic AHB decoded size for each CS. */ 971 for (cs = 0; cs < plat->max_cs; cs++) { 972 reg_val = readl(&priv->regs->segment_addr[cs]); 973 decoded_sz = priv->info->segment_end(bus, reg_val) - 974 priv->info->segment_start(bus, reg_val); 975 976 if (decoded_sz < priv->info->min_decoded_sz) 977 decoded_sz = priv->info->min_decoded_sz; 978 979 priv->flashes[cs].ahb_decoded_sz = decoded_sz; 980 } 981 } 982 983 ret = aspeed_spi_decoded_range_config(bus); 984 985 return ret; 986} 987 988static const struct aspeed_spi_info ast2400_fmc_info = { 989 .io_mode_mask = 0x70000000, 990 .max_bus_width = 2, 991 .min_decoded_sz = 0x800000, 992 .clk_ctrl_mask = 0x00002f00, 993 .set_4byte = ast2400_fmc_chip_set_4byte, 994 .segment_start = ast2400_spi_segment_start, 995 .segment_end = ast2400_spi_segment_end, 996 .segment_reg = ast2400_spi_segment_reg, 997 .get_clk_setting = ast2400_get_clk_setting, 998}; 999 1000static const struct aspeed_spi_info ast2400_spi_info = { 1001 .io_mode_mask = 0x70000000, 1002 .max_bus_width = 2, 1003 .min_decoded_sz = 0x800000, 1004 .clk_ctrl_mask = 0x00000f00, 1005 .set_4byte = ast2400_spi_chip_set_4byte, 1006 .segment_start = ast2400_spi_segment_start, 1007 .segment_end = ast2400_spi_segment_end, 1008 .segment_reg = ast2400_spi_segment_reg, 1009 .get_clk_setting = ast2400_get_clk_setting, 1010}; 1011 1012static const struct aspeed_spi_info ast2500_fmc_info = { 1013 .io_mode_mask = 0x70000000, 1014 .max_bus_width = 2, 1015 .min_decoded_sz = 0x800000, 1016 .clk_ctrl_mask = 0x00002f00, 1017 .set_4byte = ast2500_spi_chip_set_4byte, 1018 .segment_start = ast2500_spi_segment_start, 1019 .segment_end = ast2500_spi_segment_end, 1020 .segment_reg = ast2500_spi_segment_reg, 1021 .adjust_decoded_sz = ast2500_adjust_decoded_size, 1022 .get_clk_setting = ast2500_get_clk_setting, 1023}; 1024 1025/* 1026 * There are some different between FMC and SPI controllers. 1027 * For example, DMA operation, but this isn't implemented currently. 1028 */ 1029static const struct aspeed_spi_info ast2500_spi_info = { 1030 .io_mode_mask = 0x70000000, 1031 .max_bus_width = 2, 1032 .min_decoded_sz = 0x800000, 1033 .clk_ctrl_mask = 0x00002f00, 1034 .set_4byte = ast2500_spi_chip_set_4byte, 1035 .segment_start = ast2500_spi_segment_start, 1036 .segment_end = ast2500_spi_segment_end, 1037 .segment_reg = ast2500_spi_segment_reg, 1038 .adjust_decoded_sz = ast2500_adjust_decoded_size, 1039 .get_clk_setting = ast2500_get_clk_setting, 1040}; 1041 1042static const struct aspeed_spi_info ast2600_fmc_info = { 1043 .io_mode_mask = 0xf0000000, 1044 .max_bus_width = 4, 1045 .min_decoded_sz = 0x200000, 1046 .clk_ctrl_mask = 0x0f000f00, 1047 .set_4byte = ast2600_spi_chip_set_4byte, 1048 .segment_start = ast2600_spi_segment_start, 1049 .segment_end = ast2600_spi_segment_end, 1050 .segment_reg = ast2600_spi_segment_reg, 1051 .adjust_decoded_sz = ast2600_adjust_decoded_size, 1052 .get_clk_setting = ast2600_get_clk_setting, 1053}; 1054 1055static const struct aspeed_spi_info ast2600_spi_info = { 1056 .io_mode_mask = 0xf0000000, 1057 .max_bus_width = 4, 1058 .min_decoded_sz = 0x200000, 1059 .clk_ctrl_mask = 0x0f000f00, 1060 .set_4byte = ast2600_spi_chip_set_4byte, 1061 .segment_start = ast2600_spi_segment_start, 1062 .segment_end = ast2600_spi_segment_end, 1063 .segment_reg = ast2600_spi_segment_reg, 1064 .adjust_decoded_sz = ast2600_adjust_decoded_size, 1065 .get_clk_setting = ast2600_get_clk_setting, 1066}; 1067 1068static int aspeed_spi_claim_bus(struct udevice *dev) 1069{ 1070 struct udevice *bus = dev->parent; 1071 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 1072 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 1073 struct aspeed_spi_flash *flash = &priv->flashes[slave_plat->cs]; 1074 u32 clk_setting; 1075 1076 dev_dbg(bus, "%s: claim bus CS%u\n", bus->name, slave_plat->cs); 1077 1078 if (flash->max_freq == 0) { 1079 clk_setting = priv->info->get_clk_setting(dev, slave_plat->max_hz); 1080 flash->ce_ctrl_user &= ~(priv->info->clk_ctrl_mask); 1081 flash->ce_ctrl_user |= clk_setting; 1082 flash->ce_ctrl_read &= ~(priv->info->clk_ctrl_mask); 1083 flash->ce_ctrl_read |= clk_setting; 1084 } 1085 1086 return 0; 1087} 1088 1089static int aspeed_spi_release_bus(struct udevice *dev) 1090{ 1091 struct udevice *bus = dev->parent; 1092 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 1093 1094 dev_dbg(bus, "%s: release bus CS%u\n", bus->name, slave_plat->cs); 1095 1096 if (!aspeed_spi_get_flash(dev)) 1097 return -ENODEV; 1098 1099 return 0; 1100} 1101 1102static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 1103{ 1104 dev_dbg(bus, "%s: setting mode to %x\n", bus->name, mode); 1105 1106 return 0; 1107} 1108 1109static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 1110{ 1111 dev_dbg(bus, "%s: setting speed to %u\n", bus->name, hz); 1112 /* 1113 * ASPEED SPI controller supports multiple CS with different 1114 * clock frequency. We cannot distinguish which CS here. 1115 * Thus, the related implementation is postponed to claim_bus. 1116 */ 1117 1118 return 0; 1119} 1120 1121static int apseed_spi_of_to_plat(struct udevice *bus) 1122{ 1123 struct aspeed_spi_plat *plat = dev_get_plat(bus); 1124 struct aspeed_spi_priv *priv = dev_get_priv(bus); 1125 int ret; 1126 struct clk hclk; 1127 1128 priv->regs = devfdt_get_addr_index_ptr(bus, 0); 1129 if (!priv->regs) { 1130 dev_err(bus, "wrong ctrl base\n"); 1131 return -EINVAL; 1132 } 1133 1134 plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); 1135 if (!plat->ahb_base) { 1136 dev_err(bus, "wrong AHB base\n"); 1137 return -EINVAL; 1138 } 1139 1140 plat->max_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 1141 if (plat->max_cs > ASPEED_SPI_MAX_CS) 1142 return -EINVAL; 1143 1144 ret = clk_get_by_index(bus, 0, &hclk); 1145 if (ret < 0) { 1146 dev_err(bus, "%s could not get clock: %d\n", bus->name, ret); 1147 return ret; 1148 } 1149 1150 plat->hclk_rate = clk_get_rate(&hclk); 1151 1152 dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n", 1153 (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); 1154 dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n", 1155 plat->hclk_rate / 1000000, plat->max_cs); 1156 1157 return 0; 1158} 1159 1160static int aspeed_spi_probe(struct udevice *bus) 1161{ 1162 int ret; 1163 struct aspeed_spi_priv *priv = dev_get_priv(bus); 1164 struct udevice *dev; 1165 1166 priv->info = (struct aspeed_spi_info *)dev_get_driver_data(bus); 1167 1168 priv->num_cs = 0; 1169 for (device_find_first_child(bus, &dev); dev; 1170 device_find_next_child(&dev)) { 1171 priv->num_cs++; 1172 } 1173 1174 if (priv->num_cs > ASPEED_SPI_MAX_CS) 1175 return -EINVAL; 1176 1177 ret = aspeed_spi_ctrl_init(bus); 1178 1179 return ret; 1180} 1181 1182static const struct spi_controller_mem_ops aspeed_spi_mem_ops = { 1183 .supports_op = aspeed_spi_supports_op, 1184 .exec_op = aspeed_spi_exec_op_user_mode, 1185 .dirmap_create = aspeed_spi_dirmap_create, 1186 .dirmap_read = aspeed_spi_dirmap_read, 1187}; 1188 1189static const struct dm_spi_ops aspeed_spi_ops = { 1190 .claim_bus = aspeed_spi_claim_bus, 1191 .release_bus = aspeed_spi_release_bus, 1192 .set_speed = aspeed_spi_set_speed, 1193 .set_mode = aspeed_spi_set_mode, 1194 .mem_ops = &aspeed_spi_mem_ops, 1195}; 1196 1197static const struct udevice_id aspeed_spi_ids[] = { 1198 { .compatible = "aspeed,ast2400-fmc", .data = (ulong)&ast2400_fmc_info, }, 1199 { .compatible = "aspeed,ast2400-spi", .data = (ulong)&ast2400_spi_info, }, 1200 { .compatible = "aspeed,ast2500-fmc", .data = (ulong)&ast2500_fmc_info, }, 1201 { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, }, 1202 { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, }, 1203 { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, }, 1204 { } 1205}; 1206 1207U_BOOT_DRIVER(aspeed_spi) = { 1208 .name = "aspeed_spi_smc", 1209 .id = UCLASS_SPI, 1210 .of_match = aspeed_spi_ids, 1211 .ops = &aspeed_spi_ops, 1212 .of_to_plat = apseed_spi_of_to_plat, 1213 .plat_auto = sizeof(struct aspeed_spi_plat), 1214 .priv_auto = sizeof(struct aspeed_spi_priv), 1215 .probe = aspeed_spi_probe, 1216}; 1217