#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7d2bf7c2 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
spi: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c9309f40 |
|
16-Dec-2023 |
Sean Anderson <seanga2@gmail.com> |
treewide: Remove clk_free This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com |
#
8fa64bd1 |
|
12-Mar-2023 |
Johan Jonker <jbx6244@gmail.com> |
spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able to handle both sizes. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> |
#
d466f620 |
|
08-Dec-2022 |
Pengfei Fan <fanpengfei1@eswincomputing.com> |
drivers: spi: fix some typos Fix some typos in spi drivers Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9a163720 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Clock frequency adjustment support Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
dd29cee8 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support customized decoded address ranges If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
15a5c806 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Adjust decoded range size support There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
992d02ea |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: SPI dirmap read support From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
5150e908 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support AST2400 platform Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
4daa6bb6 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Add ASPEED SPI controller driver Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
7d2bf7c2 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
spi: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c9309f40 |
|
16-Dec-2023 |
Sean Anderson <seanga2@gmail.com> |
treewide: Remove clk_free This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com |
#
8fa64bd1 |
|
12-Mar-2023 |
Johan Jonker <jbx6244@gmail.com> |
spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able to handle both sizes. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> |
#
d466f620 |
|
08-Dec-2022 |
Pengfei Fan <fanpengfei1@eswincomputing.com> |
drivers: spi: fix some typos Fix some typos in spi drivers Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9a163720 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Clock frequency adjustment support Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
dd29cee8 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support customized decoded address ranges If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
15a5c806 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Adjust decoded range size support There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
992d02ea |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: SPI dirmap read support From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
5150e908 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support AST2400 platform Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
4daa6bb6 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Add ASPEED SPI controller driver Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
c9309f40 |
|
16-Dec-2023 |
Sean Anderson <seanga2@gmail.com> |
treewide: Remove clk_free This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com |
#
8fa64bd1 |
|
12-Mar-2023 |
Johan Jonker <jbx6244@gmail.com> |
spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able to handle both sizes. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> |
#
d466f620 |
|
08-Dec-2022 |
Pengfei Fan <fanpengfei1@eswincomputing.com> |
drivers: spi: fix some typos Fix some typos in spi drivers Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9a163720 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Clock frequency adjustment support Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
dd29cee8 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support customized decoded address ranges If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
15a5c806 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Adjust decoded range size support There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
992d02ea |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: SPI dirmap read support From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
5150e908 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support AST2400 platform Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
4daa6bb6 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Add ASPEED SPI controller driver Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
8fa64bd1 |
|
12-Mar-2023 |
Johan Jonker <jbx6244@gmail.com> |
spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able to handle both sizes. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> |
#
d466f620 |
|
08-Dec-2022 |
Pengfei Fan <fanpengfei1@eswincomputing.com> |
drivers: spi: fix some typos Fix some typos in spi drivers Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9a163720 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Clock frequency adjustment support Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
dd29cee8 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support customized decoded address ranges If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
15a5c806 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Adjust decoded range size support There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
992d02ea |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: SPI dirmap read support From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
5150e908 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support AST2400 platform Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
4daa6bb6 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Add ASPEED SPI controller driver Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
d466f620 |
|
08-Dec-2022 |
Pengfei Fan <fanpengfei1@eswincomputing.com> |
drivers: spi: fix some typos Fix some typos in spi drivers Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9a163720 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Clock frequency adjustment support Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
dd29cee8 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support customized decoded address ranges If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
15a5c806 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Adjust decoded range size support There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
992d02ea |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: SPI dirmap read support From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
5150e908 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support AST2400 platform Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
4daa6bb6 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Add ASPEED SPI controller driver Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
9a163720 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Clock frequency adjustment support Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
dd29cee8 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support customized decoded address ranges If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
15a5c806 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Adjust decoded range size support There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
992d02ea |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: SPI dirmap read support From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
5150e908 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Support AST2400 platform Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
#
4daa6bb6 |
|
19-Aug-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: aspeed: Add ASPEED SPI controller driver Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |