/freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
H A D | LiveRegMatrix.cpp | 72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 74 << " to " << PrintReg(PhysReg, TRI) << ':'); 76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 77 MRI->setPhysRegUsed(PhysReg); 78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 87 unsigned PhysReg = VRM->getPhys(VirtReg.reg); local 89 << " from " << PrintReg(PhysReg, TRI) << ':'); 91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 100 unsigned PhysReg) { 111 // The BitVector is indexed by PhysReg, no 99 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 117 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 138 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | RegAllocFast.cpp | 73 unsigned PhysReg; // Currently held here. member in struct:__anon2287::RAFast::LiveReg 78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {} 124 void markRegUsedInInstr(unsigned PhysReg) { argument 125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 130 bool isRegUsedInInstr(unsigned PhysReg) const { 131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 178 unsigned calcSpillCost(unsigned PhysReg) const; 179 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg); 186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg); 345 unsigned PhysReg = MO.getReg(); local 399 definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState) argument 490 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument 499 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument 539 unsigned PhysReg = *I; local 666 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument 740 unsigned PhysReg = LRI->PhysReg; local 763 unsigned PhysReg = LRI->PhysReg; local 968 unsigned PhysReg = LRI->PhysReg; local 1024 unsigned PhysReg = LRI->PhysReg; local [all...] |
H A D | InterferenceCache.h | 39 /// of PhysReg in all basic blocks. 41 /// PhysReg - The register currently represented. 42 unsigned PhysReg; member in class:llvm::InterferenceCache::Entry 63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg. 85 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have 96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {} 100 PhysReg = 0; 106 unsigned getPhysReg() const { return PhysReg; } 146 // get - Get a valid entry for PhysReg. 147 Entry *get(unsigned PhysReg); 192 setPhysReg(InterferenceCache &Cache, unsigned PhysReg) argument [all...] |
H A D | RegisterClassInfo.cpp | 97 unsigned PhysReg = RawOrder[i]; local 99 if (Reserved.test(PhysReg)) 101 unsigned Cost = TRI->getCostPerUse(PhysReg); 104 if (CSRNum[PhysReg]) 105 // PhysReg aliases a CSR, save it for later. 106 CSRAlias.push_back(PhysReg); 110 RCI.Order[N++] = PhysReg; 119 unsigned PhysReg = CSRAlias[i]; local 120 unsigned Cost = TRI->getCostPerUse(PhysReg); 123 RCI.Order[N++] = PhysReg; [all...] |
H A D | AllocationOrder.h | 77 /// Return true if PhysReg is a preferred register. 78 bool isHint(unsigned PhysReg) const { 79 return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
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H A D | RegisterCoalescer.h | 68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | VirtRegMap.cpp | 247 // assigned PhysReg must be marked as live-in to those blocks. 248 unsigned PhysReg = VRM->getPhys(VirtReg); local 249 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); 257 if (!LiveIn[i]->isLiveIn(PhysReg)) 258 LiveIn[i]->addLiveIn(PhysReg); 309 unsigned PhysReg = VRM->getPhys(VirtReg); local 310 assert(PhysReg != VirtRegMap::NO_PHYS_REG && 312 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); 320 SuperKills.push_back(PhysReg); 331 SuperDeads.push_back(PhysReg); [all...] |
H A D | RegAllocGreedy.cpp | 187 unsigned PhysReg; member in struct:__anon2289::RAGreedy::GlobalSplitCandidate 192 // Interference for PhysReg. 200 PhysReg = Reg; 220 /// Candidate info for for each PhysReg in AllocationOrder. 266 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg); 460 unsigned PhysReg; local 461 while ((PhysReg = Order.next())) 462 if (!Matrix->checkInterference(VirtReg, PhysReg)) 464 if (!PhysReg || Order.isHint()) 465 return PhysReg; 501 unsigned PhysReg; local 558 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument 640 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &NewVRegs) argument 1415 calcGapWeights(unsigned PhysReg, SmallVectorImpl<float> &GapWeight) argument [all...] |
H A D | InterferenceCache.cpp | 38 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { argument 39 unsigned E = PhysRegEntries[PhysReg]; 40 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { 56 Entries[E].reset(PhysReg, LIUArray, TRI, MF); 57 PhysRegEntries[PhysReg] = E; 71 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) 82 PhysReg = physReg; 88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 97 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { 168 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { [all...] |
H A D | RegAllocBasic.cpp | 113 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 165 // Spill or split all live virtual registers currently unified under PhysReg 168 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument 175 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 187 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << 191 // Spill each interfering vreg allocated to PhysReg or an alias. 229 while (unsigned PhysReg = Order.next()) { 230 // Check for interference in PhysReg 231 switch (Matrix->checkInterference(VirtReg, PhysReg)) { 233 // PhysReg i [all...] |
H A D | LiveRangeCalc.h | 113 /// PhysReg, when set, is used to verify live-in lists on basic blocks. 115 SlotIndex Kill, unsigned PhysReg); 161 /// PhysReg, when set, is used to verify live-in lists on basic blocks. 162 void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg = 0);
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H A D | LiveRangeCalc.cpp | 135 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) { argument 151 if (findReachingDefs(LR, *KillMBB, Kill, PhysReg)) 171 SlotIndex Kill, unsigned PhysReg) { 191 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) && 192 !MBB->isLiveIn(PhysReg)) { 170 findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, SlotIndex Kill, unsigned PhysReg) argument
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H A D | MachineRegisterInfo.cpp | 413 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, argument 415 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 419 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
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H A D | MachineBasicBlock.cpp | 346 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { argument 348 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); 353 bool LiveIn = isLiveIn(PhysReg); 361 if (I->getOperand(1).getReg() == PhysReg) { 371 .addReg(PhysReg, RegState::Kill); 373 addLiveIn(PhysReg);
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/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | LiveRegMatrix.h | 87 /// assigned to PhysReg or its aliases. This interference could be resolved 97 /// regmask operand that doesn't preserve PhysReg. This typically means 98 /// VirtReg is live across a call, and PhysReg isn't call-preserved. 102 /// Check for interference before assigning VirtReg to PhysReg. 103 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg). 106 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); 108 /// Assign VirtReg to PhysReg. 110 /// update VirtRegMap. The live range is expected to be available in PhysReg. 111 void assign(LiveInterval &VirtReg, unsigned PhysReg); 113 /// Unassign VirtReg from its PhysReg [all...] |
H A D | RegisterClassInfo.h | 109 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR. 110 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { 111 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 112 if (unsigned N = CSRNum[PhysReg])
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H A D | MachineRegisterInfo.h | 326 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 329 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 478 /// canReserveReg - Returns true if PhysReg can be used as a reserved 481 bool canReserveReg(unsigned PhysReg) const { 482 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 495 /// isReserved - Returns true when PhysReg is a reserved register. 500 bool isReserved(unsigned PhysReg) const { 501 return getReservedRegs().test(PhysReg); 504 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 510 bool isAllocatable(unsigned PhysReg) cons [all...] |
H A D | MachineOperand.h | 457 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 461 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { argument 463 assert(PhysReg < (1u << 30) && "Not a physical register"); 464 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); 467 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 468 bool clobbersPhysReg(unsigned PhysReg) const { 469 return clobbersPhysReg(getRegMask(), PhysReg);
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H A D | MachineBasicBlock.h | 299 /// Add PhysReg as live in to this block, and ensure that there is a copy of 300 /// PhysReg to a virtual register of class RC. Return the virtual register 301 /// that is a copy of the live in PhysReg. 302 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
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/freebsd-10.1-release/contrib/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 407 std::string PhysReg; 410 return PhysReg; 414 return PhysReg; 416 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue()) 418 PhysReg += "::"; 419 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 420 return PhysReg; 523 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 524 if (PhysReg.empty()) { 534 PhysRegInputs->push_back(PhysReg); [all...] |
/freebsd-10.1-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 113 unsigned &PhysReg, int &Cost) { 126 PhysReg = Reg; 473 unsigned PhysReg = 0; 476 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 477 assert((PhysReg == 0 || !isChain) && 485 PhysReg = 0; 494 : SDep(OpSU, SDep::Data, PhysReg); 110 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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H A D | FunctionLoweringInfo.cpp | 132 std::pair<unsigned, const TargetRegisterClass*> PhysReg = local 135 if (PhysReg.first == SP)
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H A D | SelectionDAGBuilder.cpp | 6102 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 6112 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 6116 MVT RegVT = *PhysReg.second->vt_begin(); 6141 if (unsigned AssignedReg = PhysReg.first) { 6142 const TargetRegisterClass *RC = PhysReg.second; 6174 if (const TargetRegisterClass *RC = PhysReg.second) {
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