1239310Sdim//===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===// 2239310Sdim// 3239310Sdim// The LLVM Compiler Infrastructure 4239310Sdim// 5239310Sdim// This file is distributed under the University of Illinois Open Source 6239310Sdim// License. See LICENSE.TXT for details. 7239310Sdim// 8239310Sdim//===----------------------------------------------------------------------===// 9239310Sdim// 10239310Sdim// This file implements the RegisterClassInfo class which provides dynamic 11239310Sdim// information about target register classes. Callee saved and reserved 12239310Sdim// registers depends on calling conventions and other dynamic information, so 13239310Sdim// some things cannot be determined statically. 14239310Sdim// 15239310Sdim//===----------------------------------------------------------------------===// 16239310Sdim 17239310Sdim#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H 18239310Sdim#define LLVM_CODEGEN_REGISTERCLASSINFO_H 19239310Sdim 20239310Sdim#include "llvm/ADT/ArrayRef.h" 21239310Sdim#include "llvm/ADT/BitVector.h" 22239310Sdim#include "llvm/ADT/OwningPtr.h" 23239310Sdim#include "llvm/Target/TargetRegisterInfo.h" 24239310Sdim 25239310Sdimnamespace llvm { 26239310Sdim 27239310Sdimclass RegisterClassInfo { 28239310Sdim struct RCInfo { 29239310Sdim unsigned Tag; 30239310Sdim unsigned NumRegs; 31239310Sdim bool ProperSubClass; 32249423Sdim uint8_t MinCost; 33249423Sdim uint16_t LastCostChange; 34249423Sdim OwningArrayPtr<MCPhysReg> Order; 35239310Sdim 36249423Sdim RCInfo() 37249423Sdim : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0), 38249423Sdim LastCostChange(0) {} 39249423Sdim 40249423Sdim operator ArrayRef<MCPhysReg>() const { 41239310Sdim return makeArrayRef(Order.get(), NumRegs); 42239310Sdim } 43239310Sdim }; 44239310Sdim 45239310Sdim // Brief cached information for each register class. 46239310Sdim OwningArrayPtr<RCInfo> RegClass; 47239310Sdim 48239310Sdim // Tag changes whenever cached information needs to be recomputed. An RCInfo 49239310Sdim // entry is valid when its tag matches. 50239310Sdim unsigned Tag; 51239310Sdim 52239310Sdim const MachineFunction *MF; 53239310Sdim const TargetRegisterInfo *TRI; 54239310Sdim 55239310Sdim // Callee saved registers of last MF. Assumed to be valid until the next 56239310Sdim // runOnFunction() call. 57239310Sdim const uint16_t *CalleeSaved; 58239310Sdim 59239310Sdim // Map register number to CalleeSaved index + 1; 60239310Sdim SmallVector<uint8_t, 4> CSRNum; 61239310Sdim 62239310Sdim // Reserved registers in the current MF. 63239310Sdim BitVector Reserved; 64239310Sdim 65263508Sdim OwningArrayPtr<unsigned> PSetLimits; 66263508Sdim 67239310Sdim // Compute all information about RC. 68239310Sdim void compute(const TargetRegisterClass *RC) const; 69239310Sdim 70239310Sdim // Return an up-to-date RCInfo for RC. 71239310Sdim const RCInfo &get(const TargetRegisterClass *RC) const { 72239310Sdim const RCInfo &RCI = RegClass[RC->getID()]; 73239310Sdim if (Tag != RCI.Tag) 74239310Sdim compute(RC); 75239310Sdim return RCI; 76239310Sdim } 77239310Sdim 78239310Sdimpublic: 79239310Sdim RegisterClassInfo(); 80239310Sdim 81239310Sdim /// runOnFunction - Prepare to answer questions about MF. This must be called 82239310Sdim /// before any other methods are used. 83239310Sdim void runOnMachineFunction(const MachineFunction &MF); 84239310Sdim 85239310Sdim /// getNumAllocatableRegs - Returns the number of actually allocatable 86239310Sdim /// registers in RC in the current function. 87239310Sdim unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 88239310Sdim return get(RC).NumRegs; 89239310Sdim } 90239310Sdim 91239310Sdim /// getOrder - Returns the preferred allocation order for RC. The order 92239310Sdim /// contains no reserved registers, and registers that alias callee saved 93239310Sdim /// registers come last. 94249423Sdim ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { 95239310Sdim return get(RC); 96239310Sdim } 97239310Sdim 98239310Sdim /// isProperSubClass - Returns true if RC has a legal super-class with more 99239310Sdim /// allocatable registers. 100239310Sdim /// 101239310Sdim /// Register classes like GR32_NOSP are not proper sub-classes because %esp 102239310Sdim /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb 103239310Sdim /// mode because the GPR super-class is not legal. 104239310Sdim bool isProperSubClass(const TargetRegisterClass *RC) const { 105239310Sdim return get(RC).ProperSubClass; 106239310Sdim } 107239310Sdim 108239310Sdim /// getLastCalleeSavedAlias - Returns the last callee saved register that 109239310Sdim /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR. 110239310Sdim unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { 111239310Sdim assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 112239310Sdim if (unsigned N = CSRNum[PhysReg]) 113239310Sdim return CalleeSaved[N-1]; 114239310Sdim return 0; 115239310Sdim } 116249423Sdim 117249423Sdim /// Get the minimum register cost in RC's allocation order. 118249423Sdim /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all 119249423Sdim /// the registers in getOrder(RC). 120249423Sdim unsigned getMinCost(const TargetRegisterClass *RC) { 121249423Sdim return get(RC).MinCost; 122249423Sdim } 123249423Sdim 124249423Sdim /// Get the position of the last cost change in getOrder(RC). 125249423Sdim /// 126249423Sdim /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the 127249423Sdim /// same cost according to TRI->getCostPerUse(). 128249423Sdim unsigned getLastCostChange(const TargetRegisterClass *RC) { 129249423Sdim return get(RC).LastCostChange; 130249423Sdim } 131263508Sdim 132263508Sdim /// Get the register unit limit for the given pressure set index. 133263508Sdim /// 134263508Sdim /// RegisterClassInfo adjusts this limit for reserved registers. 135263508Sdim unsigned getRegPressureSetLimit(unsigned Idx) const { 136263508Sdim if (!PSetLimits[Idx]) 137263508Sdim PSetLimits[Idx] = computePSetLimit(Idx); 138263508Sdim return PSetLimits[Idx]; 139263508Sdim } 140263508Sdim 141263508Sdimprotected: 142263508Sdim unsigned computePSetLimit(unsigned Idx) const; 143239310Sdim}; 144239310Sdim} // end namespace llvm 145239310Sdim 146239310Sdim#endif 147