1234353Sdim//===-- InterferenceCache.cpp - Caching per-block interference ---------*--===// 2221337Sdim// 3221337Sdim// The LLVM Compiler Infrastructure 4221337Sdim// 5221337Sdim// This file is distributed under the University of Illinois Open Source 6221337Sdim// License. See LICENSE.TXT for details. 7221337Sdim// 8221337Sdim//===----------------------------------------------------------------------===// 9221337Sdim// 10221337Sdim// InterferenceCache remembers per-block interference in LiveIntervalUnions. 11221337Sdim// 12221337Sdim//===----------------------------------------------------------------------===// 13221337Sdim 14221337Sdim#define DEBUG_TYPE "regalloc" 15221337Sdim#include "InterferenceCache.h" 16249423Sdim#include "llvm/CodeGen/LiveIntervalAnalysis.h" 17249423Sdim#include "llvm/Support/ErrorHandling.h" 18221337Sdim#include "llvm/Target/TargetRegisterInfo.h" 19221337Sdim 20221337Sdimusing namespace llvm; 21221337Sdim 22226633Sdim// Static member used for null interference cursors. 23226633SdimInterferenceCache::BlockInterference InterferenceCache::Cursor::NoInterference; 24226633Sdim 25221337Sdimvoid InterferenceCache::init(MachineFunction *mf, 26221337Sdim LiveIntervalUnion *liuarray, 27221337Sdim SlotIndexes *indexes, 28234353Sdim LiveIntervals *lis, 29226633Sdim const TargetRegisterInfo *tri) { 30221337Sdim MF = mf; 31221337Sdim LIUArray = liuarray; 32221337Sdim TRI = tri; 33221337Sdim PhysRegEntries.assign(TRI->getNumRegs(), 0); 34221337Sdim for (unsigned i = 0; i != CacheEntries; ++i) 35234353Sdim Entries[i].clear(mf, indexes, lis); 36221337Sdim} 37221337Sdim 38221337SdimInterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { 39221337Sdim unsigned E = PhysRegEntries[PhysReg]; 40221337Sdim if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { 41221337Sdim if (!Entries[E].valid(LIUArray, TRI)) 42239462Sdim Entries[E].revalidate(LIUArray, TRI); 43221337Sdim return &Entries[E]; 44221337Sdim } 45221337Sdim // No valid entry exists, pick the next round-robin entry. 46221337Sdim E = RoundRobin; 47221337Sdim if (++RoundRobin == CacheEntries) 48221337Sdim RoundRobin = 0; 49224145Sdim for (unsigned i = 0; i != CacheEntries; ++i) { 50224145Sdim // Skip entries that are in use. 51224145Sdim if (Entries[E].hasRefs()) { 52224145Sdim if (++E == CacheEntries) 53224145Sdim E = 0; 54224145Sdim continue; 55224145Sdim } 56224145Sdim Entries[E].reset(PhysReg, LIUArray, TRI, MF); 57224145Sdim PhysRegEntries[PhysReg] = E; 58224145Sdim return &Entries[E]; 59224145Sdim } 60224145Sdim llvm_unreachable("Ran out of interference cache entries."); 61221337Sdim} 62221337Sdim 63221337Sdim/// revalidate - LIU contents have changed, update tags. 64239462Sdimvoid InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray, 65239462Sdim const TargetRegisterInfo *TRI) { 66221337Sdim // Invalidate all block entries. 67221337Sdim ++Tag; 68221337Sdim // Invalidate all iterators. 69221337Sdim PrevPos = SlotIndex(); 70239462Sdim unsigned i = 0; 71239462Sdim for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) 72239462Sdim RegUnits[i].VirtTag = LIUArray[*Units].getTag(); 73221337Sdim} 74221337Sdim 75221337Sdimvoid InterferenceCache::Entry::reset(unsigned physReg, 76221337Sdim LiveIntervalUnion *LIUArray, 77221337Sdim const TargetRegisterInfo *TRI, 78221337Sdim const MachineFunction *MF) { 79224145Sdim assert(!hasRefs() && "Cannot reset cache entry with references"); 80221337Sdim // LIU's changed, invalidate cache. 81221337Sdim ++Tag; 82221337Sdim PhysReg = physReg; 83221337Sdim Blocks.resize(MF->getNumBlockIDs()); 84221337Sdim 85221337Sdim // Reset iterators. 86221337Sdim PrevPos = SlotIndex(); 87239462Sdim RegUnits.clear(); 88239462Sdim for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 89239462Sdim RegUnits.push_back(LIUArray[*Units]); 90239462Sdim RegUnits.back().Fixed = &LIS->getRegUnit(*Units); 91239462Sdim } 92221337Sdim} 93221337Sdim 94221337Sdimbool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray, 95221337Sdim const TargetRegisterInfo *TRI) { 96239462Sdim unsigned i = 0, e = RegUnits.size(); 97239462Sdim for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { 98239462Sdim if (i == e) 99221337Sdim return false; 100239462Sdim if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag)) 101221337Sdim return false; 102221337Sdim } 103221337Sdim return i == e; 104221337Sdim} 105221337Sdim 106221337Sdimvoid InterferenceCache::Entry::update(unsigned MBBNum) { 107221337Sdim SlotIndex Start, Stop; 108221337Sdim tie(Start, Stop) = Indexes->getMBBRange(MBBNum); 109221337Sdim 110221337Sdim // Use advanceTo only when possible. 111221337Sdim if (PrevPos != Start) { 112239462Sdim if (!PrevPos.isValid() || Start < PrevPos) { 113239462Sdim for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) { 114239462Sdim RegUnitInfo &RUI = RegUnits[i]; 115239462Sdim RUI.VirtI.find(Start); 116239462Sdim RUI.FixedI = RUI.Fixed->find(Start); 117239462Sdim } 118239462Sdim } else { 119239462Sdim for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) { 120239462Sdim RegUnitInfo &RUI = RegUnits[i]; 121239462Sdim RUI.VirtI.advanceTo(Start); 122239462Sdim if (RUI.FixedI != RUI.Fixed->end()) 123239462Sdim RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start); 124239462Sdim } 125239462Sdim } 126221337Sdim PrevPos = Start; 127221337Sdim } 128221337Sdim 129221337Sdim MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum); 130221337Sdim BlockInterference *BI = &Blocks[MBBNum]; 131234353Sdim ArrayRef<SlotIndex> RegMaskSlots; 132234353Sdim ArrayRef<const uint32_t*> RegMaskBits; 133221337Sdim for (;;) { 134221337Sdim BI->Tag = Tag; 135221337Sdim BI->First = BI->Last = SlotIndex(); 136221337Sdim 137239462Sdim // Check for first interference from virtregs. 138239462Sdim for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) { 139239462Sdim LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI; 140221337Sdim if (!I.valid()) 141221337Sdim continue; 142221337Sdim SlotIndex StartI = I.start(); 143221337Sdim if (StartI >= Stop) 144221337Sdim continue; 145221337Sdim if (!BI->First.isValid() || StartI < BI->First) 146221337Sdim BI->First = StartI; 147221337Sdim } 148221337Sdim 149239462Sdim // Same thing for fixed interference. 150239462Sdim for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) { 151239462Sdim LiveInterval::const_iterator I = RegUnits[i].FixedI; 152239462Sdim LiveInterval::const_iterator E = RegUnits[i].Fixed->end(); 153239462Sdim if (I == E) 154239462Sdim continue; 155239462Sdim SlotIndex StartI = I->start; 156239462Sdim if (StartI >= Stop) 157239462Sdim continue; 158239462Sdim if (!BI->First.isValid() || StartI < BI->First) 159239462Sdim BI->First = StartI; 160239462Sdim } 161239462Sdim 162234353Sdim // Also check for register mask interference. 163234353Sdim RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); 164234353Sdim RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum); 165234353Sdim SlotIndex Limit = BI->First.isValid() ? BI->First : Stop; 166234353Sdim for (unsigned i = 0, e = RegMaskSlots.size(); 167234353Sdim i != e && RegMaskSlots[i] < Limit; ++i) 168234353Sdim if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { 169234353Sdim // Register mask i clobbers PhysReg before the LIU interference. 170234353Sdim BI->First = RegMaskSlots[i]; 171234353Sdim break; 172234353Sdim } 173234353Sdim 174221337Sdim PrevPos = Stop; 175221337Sdim if (BI->First.isValid()) 176221337Sdim break; 177221337Sdim 178221337Sdim // No interference in this block? Go ahead and precompute the next block. 179221337Sdim if (++MFI == MF->end()) 180221337Sdim return; 181221337Sdim MBBNum = MFI->getNumber(); 182221337Sdim BI = &Blocks[MBBNum]; 183221337Sdim if (BI->Tag == Tag) 184221337Sdim return; 185221337Sdim tie(Start, Stop) = Indexes->getMBBRange(MBBNum); 186221337Sdim } 187221337Sdim 188221337Sdim // Check for last interference in block. 189239462Sdim for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) { 190239462Sdim LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI; 191221337Sdim if (!I.valid() || I.start() >= Stop) 192221337Sdim continue; 193221337Sdim I.advanceTo(Stop); 194221337Sdim bool Backup = !I.valid() || I.start() >= Stop; 195221337Sdim if (Backup) 196221337Sdim --I; 197221337Sdim SlotIndex StopI = I.stop(); 198221337Sdim if (!BI->Last.isValid() || StopI > BI->Last) 199221337Sdim BI->Last = StopI; 200221337Sdim if (Backup) 201221337Sdim ++I; 202221337Sdim } 203234353Sdim 204239462Sdim // Fixed interference. 205239462Sdim for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) { 206239462Sdim LiveInterval::iterator &I = RegUnits[i].FixedI; 207263508Sdim LiveRange *LR = RegUnits[i].Fixed; 208263508Sdim if (I == LR->end() || I->start >= Stop) 209239462Sdim continue; 210263508Sdim I = LR->advanceTo(I, Stop); 211263508Sdim bool Backup = I == LR->end() || I->start >= Stop; 212239462Sdim if (Backup) 213239462Sdim --I; 214239462Sdim SlotIndex StopI = I->end; 215239462Sdim if (!BI->Last.isValid() || StopI > BI->Last) 216239462Sdim BI->Last = StopI; 217239462Sdim if (Backup) 218239462Sdim ++I; 219239462Sdim } 220239462Sdim 221234353Sdim // Also check for register mask interference. 222234353Sdim SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start; 223234353Sdim for (unsigned i = RegMaskSlots.size(); 224234353Sdim i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) 225234353Sdim if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) { 226234353Sdim // Register mask i-1 clobbers PhysReg after the LIU interference. 227234353Sdim // Model the regmask clobber as a dead def. 228234353Sdim BI->Last = RegMaskSlots[i-1].getDeadSlot(); 229234353Sdim break; 230234353Sdim } 231221337Sdim} 232