1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2020 Cortina Access Inc. 4 * 5 * Configuration for Cortina-Access Presidio board 6 */ 7 8#ifndef __PRESIDIO_ASIC_H 9#define __PRESIDIO_ASIC_H 10 11/* Generic Timer Definitions */ 12#define CFG_SYS_TIMER_RATE 25000000 13#define CFG_SYS_TIMER_COUNTER 0xf4321008 14 15/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE 16 * does not yet support DT. Thus define it here. 17 */ 18#define GICD_BASE 0xf7011000 19#define GICC_BASE 0xf7012000 20 21#define CFG_SYS_TIMER_BASE 0xf4321000 22 23/* Use external clock source */ 24#define PRESIDIO_APB_CLK 125000000 25#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK 26 27/* Cortina Serial Configuration */ 28#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) 29#define CORTINA_SERIAL_PORTS {(void *)CFG_SYS_SERIAL0, \ 30 (void *)CFG_SYS_SERIAL1} 31 32#define CFG_SYS_SERIAL0 PER_UART0_CFG 33#define CFG_SYS_SERIAL1 PER_UART1_CFG 34 35/* SDRAM Bank #1 */ 36#define DDR_BASE 0x00000000 37#define PHYS_SDRAM_1 DDR_BASE 38#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ 39#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 40 41/* Console I/O Buffer Size */ 42 43#define KSEG1_ATU_XLAT(x) (x) 44 45/* HW REG ADDR */ 46#define NI_READ_POLL_COUNT 1000 47#define CA_NI_MDIO_REG_BASE 0xF4338 48#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010 49#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014 50#define NI_HV_PT_BASE 0x400 51#define NI_HV_XRAM_BASE 0x820 52#define GLOBAL_BLOCK_RESET_OFFSET 0x04 53#define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20 54#define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c 55 56/* max command args */ 57#define CFG_EXTRA_ENV_SETTINGS "silent=y\0" 58 59/* nand driver parameters */ 60#ifdef CONFIG_TARGET_PRESIDIO_ASIC 61 #define CFG_SYS_NAND_BASE CFG_SYS_FLASH_BASE 62 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 63#endif 64 65#endif /* __PRESIDIO_ASIC_H */ 66