1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2010 4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. 5 */ 6 7/* 8 * Designware ethernet IP driver for U-Boot 9 */ 10 11#include <common.h> 12#include <clk.h> 13#include <cpu_func.h> 14#include <dm.h> 15#include <errno.h> 16#include <eth_phy.h> 17#include <log.h> 18#include <miiphy.h> 19#include <malloc.h> 20#include <net.h> 21#include <pci.h> 22#include <reset.h> 23#include <phys2bus.h> 24#include <asm/cache.h> 25#include <dm/device_compat.h> 26#include <dm/device-internal.h> 27#include <dm/devres.h> 28#include <dm/lists.h> 29#include <linux/compiler.h> 30#include <linux/delay.h> 31#include <linux/err.h> 32#include <linux/kernel.h> 33#include <asm/io.h> 34#include <linux/printk.h> 35#include <power/regulator.h> 36#include "designware.h" 37 38static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 39{ 40 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 41 struct eth_mac_regs *mac_p = priv->mac_regs_p; 42 ulong start; 43 u16 miiaddr; 44 int timeout = CFG_MDIO_TIMEOUT; 45 46 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 47 ((reg << MIIREGSHIFT) & MII_REGMSK); 48 49 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 50 51 start = get_timer(0); 52 while (get_timer(start) < timeout) { 53 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 54 return readl(&mac_p->miidata); 55 udelay(10); 56 }; 57 58 return -ETIMEDOUT; 59} 60 61static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 62 u16 val) 63{ 64 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 65 struct eth_mac_regs *mac_p = priv->mac_regs_p; 66 ulong start; 67 u16 miiaddr; 68 int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT; 69 70 writel(val, &mac_p->miidata); 71 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 72 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 73 74 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 75 76 start = get_timer(0); 77 while (get_timer(start) < timeout) { 78 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 79 ret = 0; 80 break; 81 } 82 udelay(10); 83 }; 84 85 return ret; 86} 87 88#if CONFIG_IS_ENABLED(DM_GPIO) 89static int __dw_mdio_reset(struct udevice *dev) 90{ 91 struct dw_eth_dev *priv = dev_get_priv(dev); 92 struct dw_eth_pdata *pdata = dev_get_plat(dev); 93 int ret; 94 95 if (!dm_gpio_is_valid(&priv->reset_gpio)) 96 return 0; 97 98 /* reset the phy */ 99 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 100 if (ret) 101 return ret; 102 103 udelay(pdata->reset_delays[0]); 104 105 ret = dm_gpio_set_value(&priv->reset_gpio, 1); 106 if (ret) 107 return ret; 108 109 udelay(pdata->reset_delays[1]); 110 111 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 112 if (ret) 113 return ret; 114 115 udelay(pdata->reset_delays[2]); 116 117 return 0; 118} 119 120static int dw_mdio_reset(struct mii_dev *bus) 121{ 122 struct udevice *dev = bus->priv; 123 124 return __dw_mdio_reset(dev); 125} 126#endif 127 128#if IS_ENABLED(CONFIG_DM_MDIO) 129int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) 130{ 131 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); 132 133 return dw_mdio_read(pdata->mii_bus, addr, devad, reg); 134} 135 136int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) 137{ 138 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); 139 140 return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val); 141} 142 143#if CONFIG_IS_ENABLED(DM_GPIO) 144int designware_eth_mdio_reset(struct udevice *mdio_dev) 145{ 146 struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev); 147 struct udevice *dev = mdio_pdata->mii_bus->priv; 148 149 return __dw_mdio_reset(dev->parent); 150} 151#endif 152 153static const struct mdio_ops designware_eth_mdio_ops = { 154 .read = designware_eth_mdio_read, 155 .write = designware_eth_mdio_write, 156#if CONFIG_IS_ENABLED(DM_GPIO) 157 .reset = designware_eth_mdio_reset, 158#endif 159}; 160 161static int designware_eth_mdio_probe(struct udevice *dev) 162{ 163 /* Use the priv data of parent */ 164 dev_set_priv(dev, dev_get_priv(dev->parent)); 165 166 return 0; 167} 168 169U_BOOT_DRIVER(designware_eth_mdio) = { 170 .name = "eth_designware_mdio", 171 .id = UCLASS_MDIO, 172 .probe = designware_eth_mdio_probe, 173 .ops = &designware_eth_mdio_ops, 174 .plat_auto = sizeof(struct mdio_perdev_priv), 175}; 176#endif 177 178static int dw_mdio_init(const char *name, void *priv) 179{ 180 struct mii_dev *bus = mdio_alloc(); 181 182 if (!bus) { 183 printf("Failed to allocate MDIO bus\n"); 184 return -ENOMEM; 185 } 186 187 bus->read = dw_mdio_read; 188 bus->write = dw_mdio_write; 189 snprintf(bus->name, sizeof(bus->name), "%s", name); 190#if CONFIG_IS_ENABLED(DM_GPIO) 191 bus->reset = dw_mdio_reset; 192#endif 193 194 bus->priv = priv; 195 196 return mdio_register(bus); 197} 198 199#if IS_ENABLED(CONFIG_DM_MDIO) 200static int dw_dm_mdio_init(const char *name, void *priv) 201{ 202 struct udevice *dev = priv; 203 ofnode node; 204 int ret; 205 206 ofnode_for_each_subnode(node, dev_ofnode(dev)) { 207 const char *subnode_name = ofnode_get_name(node); 208 struct udevice *mdiodev; 209 210 if (strcmp(subnode_name, "mdio")) 211 continue; 212 213 ret = device_bind_driver_to_node(dev, "eth_designware_mdio", 214 subnode_name, node, &mdiodev); 215 if (ret) 216 debug("%s: not able to bind mdio device node\n", __func__); 217 218 return 0; 219 } 220 221 printf("%s: mdio node is missing, registering legacy mdio bus", __func__); 222 223 return dw_mdio_init(name, priv); 224} 225#endif 226 227static void tx_descs_init(struct dw_eth_dev *priv) 228{ 229 struct eth_dma_regs *dma_p = priv->dma_regs_p; 230 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 231 char *txbuffs = &priv->txbuffs[0]; 232 struct dmamacdescr *desc_p; 233 u32 idx; 234 235 for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) { 236 desc_p = &desc_table_p[idx]; 237 desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, 238 (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]); 239 desc_p->dmamac_next = dev_phys_to_bus(priv->dev, 240 (ulong)&desc_table_p[idx + 1]); 241 242#if defined(CONFIG_DW_ALTDESCRIPTOR) 243 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 244 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 245 DESC_TXSTS_TXCHECKINSCTRL | 246 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 247 248 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 249 desc_p->dmamac_cntl = 0; 250 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 251#else 252 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 253 desc_p->txrx_status = 0; 254#endif 255 } 256 257 /* Correcting the last pointer of the chain */ 258 desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); 259 260 /* Flush all Tx buffer descriptors at once */ 261 flush_dcache_range((ulong)priv->tx_mac_descrtable, 262 (ulong)priv->tx_mac_descrtable + 263 sizeof(priv->tx_mac_descrtable)); 264 265 writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), 266 &dma_p->txdesclistaddr); 267 priv->tx_currdescnum = 0; 268} 269 270static void rx_descs_init(struct dw_eth_dev *priv) 271{ 272 struct eth_dma_regs *dma_p = priv->dma_regs_p; 273 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 274 char *rxbuffs = &priv->rxbuffs[0]; 275 struct dmamacdescr *desc_p; 276 u32 idx; 277 278 /* Before passing buffers to GMAC we need to make sure zeros 279 * written there right after "priv" structure allocation were 280 * flushed into RAM. 281 * Otherwise there's a chance to get some of them flushed in RAM when 282 * GMAC is already pushing data to RAM via DMA. This way incoming from 283 * GMAC data will be corrupted. */ 284 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); 285 286 for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) { 287 desc_p = &desc_table_p[idx]; 288 desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, 289 (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]); 290 desc_p->dmamac_next = dev_phys_to_bus(priv->dev, 291 (ulong)&desc_table_p[idx + 1]); 292 293 desc_p->dmamac_cntl = 294 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 295 DESC_RXCTRL_RXCHAIN; 296 297 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 298 } 299 300 /* Correcting the last pointer of the chain */ 301 desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); 302 303 /* Flush all Rx buffer descriptors at once */ 304 flush_dcache_range((ulong)priv->rx_mac_descrtable, 305 (ulong)priv->rx_mac_descrtable + 306 sizeof(priv->rx_mac_descrtable)); 307 308 writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), 309 &dma_p->rxdesclistaddr); 310 priv->rx_currdescnum = 0; 311} 312 313static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 314{ 315 struct eth_mac_regs *mac_p = priv->mac_regs_p; 316 u32 macid_lo, macid_hi; 317 318 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 319 (mac_id[3] << 24); 320 macid_hi = mac_id[4] + (mac_id[5] << 8); 321 322 writel(macid_hi, &mac_p->macaddr0hi); 323 writel(macid_lo, &mac_p->macaddr0lo); 324 325 return 0; 326} 327 328static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, 329 struct phy_device *phydev) 330{ 331 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 332 333 if (!phydev->link) { 334 printf("%s: No link.\n", phydev->dev->name); 335 return 0; 336 } 337 338 if (phydev->speed != 1000) 339 conf |= MII_PORTSELECT; 340 else 341 conf &= ~MII_PORTSELECT; 342 343 if (phydev->speed == 100) 344 conf |= FES_100; 345 346 if (phydev->duplex) 347 conf |= FULLDPLXMODE; 348 349 writel(conf, &mac_p->conf); 350 351 printf("Speed: %d, %s duplex%s\n", phydev->speed, 352 (phydev->duplex) ? "full" : "half", 353 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 354 355#ifdef CONFIG_ARCH_NPCM8XX 356 /* Pass all Multicast Frames */ 357 setbits_le32(&mac_p->framefilt, BIT(4)); 358 359#endif 360 return 0; 361} 362 363static void _dw_eth_halt(struct dw_eth_dev *priv) 364{ 365 struct eth_mac_regs *mac_p = priv->mac_regs_p; 366 struct eth_dma_regs *dma_p = priv->dma_regs_p; 367 368 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 369 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 370 371 phy_shutdown(priv->phydev); 372} 373 374int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 375{ 376 struct eth_mac_regs *mac_p = priv->mac_regs_p; 377 struct eth_dma_regs *dma_p = priv->dma_regs_p; 378 unsigned int start; 379 int ret; 380 381 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 382 383 /* 384 * When a MII PHY is used, we must set the PS bit for the DMA 385 * reset to succeed. 386 */ 387 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII) 388 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf); 389 else 390 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf); 391 392 start = get_timer(0); 393 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 394 if (get_timer(start) >= CFG_MACRESET_TIMEOUT) { 395 printf("DMA reset timeout\n"); 396 return -ETIMEDOUT; 397 } 398 399 mdelay(100); 400 }; 401 402 /* 403 * Soft reset above clears HW address registers. 404 * So we have to set it here once again. 405 */ 406 _dw_write_hwaddr(priv, enetaddr); 407 408 rx_descs_init(priv); 409 tx_descs_init(priv); 410 411 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 412 413#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 414 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 415 &dma_p->opmode); 416#else 417 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 418 &dma_p->opmode); 419#endif 420 421 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 422 423#ifdef CONFIG_DW_AXI_BURST_LEN 424 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 425#endif 426 427 /* Start up the PHY */ 428 ret = phy_startup(priv->phydev); 429 if (ret) { 430 printf("Could not initialize PHY %s\n", 431 priv->phydev->dev->name); 432 return ret; 433 } 434 435 ret = dw_adjust_link(priv, mac_p, priv->phydev); 436 if (ret) 437 return ret; 438 439 return 0; 440} 441 442int designware_eth_enable(struct dw_eth_dev *priv) 443{ 444 struct eth_mac_regs *mac_p = priv->mac_regs_p; 445 446 if (!priv->phydev->link) 447 return -EIO; 448 449 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 450 451 return 0; 452} 453 454#define ETH_ZLEN 60 455 456static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 457{ 458 struct eth_dma_regs *dma_p = priv->dma_regs_p; 459 u32 desc_num = priv->tx_currdescnum; 460 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 461 ulong desc_start = (ulong)desc_p; 462 ulong desc_end = desc_start + 463 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 464 ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); 465 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 466 /* 467 * Strictly we only need to invalidate the "txrx_status" field 468 * for the following check, but on some platforms we cannot 469 * invalidate only 4 bytes, so we flush the entire descriptor, 470 * which is 16 bytes in total. This is safe because the 471 * individual descriptors in the array are each aligned to 472 * ARCH_DMA_MINALIGN and padded appropriately. 473 */ 474 invalidate_dcache_range(desc_start, desc_end); 475 476 /* Check if the descriptor is owned by CPU */ 477 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 478 printf("CPU not owner of tx frame\n"); 479 return -EPERM; 480 } 481 482 memcpy((void *)data_start, packet, length); 483 if (length < ETH_ZLEN) { 484 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length); 485 length = ETH_ZLEN; 486 } 487 488 /* Flush data to be sent */ 489 flush_dcache_range(data_start, data_end); 490 491#if defined(CONFIG_DW_ALTDESCRIPTOR) 492 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 493 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) | 494 ((length << DESC_TXCTRL_SIZE1SHFT) & 495 DESC_TXCTRL_SIZE1MASK); 496 497 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 498 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 499#else 500 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) | 501 ((length << DESC_TXCTRL_SIZE1SHFT) & 502 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 503 DESC_TXCTRL_TXFIRST; 504 505 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 506#endif 507 508 /* Flush modified buffer descriptor */ 509 flush_dcache_range(desc_start, desc_end); 510 511 /* Test the wrap-around condition. */ 512 if (++desc_num >= CFG_TX_DESCR_NUM) 513 desc_num = 0; 514 515 priv->tx_currdescnum = desc_num; 516 517 /* Start the transmission */ 518 writel(POLL_DATA, &dma_p->txpolldemand); 519 520 return 0; 521} 522 523static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 524{ 525 u32 status, desc_num = priv->rx_currdescnum; 526 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 527 int length = -EAGAIN; 528 ulong desc_start = (ulong)desc_p; 529 ulong desc_end = desc_start + 530 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 531 ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); 532 ulong data_end; 533 534 /* Invalidate entire buffer descriptor */ 535 invalidate_dcache_range(desc_start, desc_end); 536 537 status = desc_p->txrx_status; 538 539 /* Check if the owner is the CPU */ 540 if (!(status & DESC_RXSTS_OWNBYDMA)) { 541 542 length = (status & DESC_RXSTS_FRMLENMSK) >> 543 DESC_RXSTS_FRMLENSHFT; 544 545 /* Invalidate received data */ 546 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 547 invalidate_dcache_range(data_start, data_end); 548 *packetp = (uchar *)(ulong)dev_bus_to_phys(priv->dev, 549 desc_p->dmamac_addr); 550 } 551 552 return length; 553} 554 555static int _dw_free_pkt(struct dw_eth_dev *priv) 556{ 557 u32 desc_num = priv->rx_currdescnum; 558 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 559 ulong desc_start = (ulong)desc_p; 560 ulong desc_end = desc_start + 561 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 562 ulong data_start = desc_p->dmamac_addr; 563 ulong data_end = data_start + roundup(CFG_ETH_BUFSIZE, ARCH_DMA_MINALIGN); 564 565 /* Invalidate the descriptor buffer data */ 566 invalidate_dcache_range(data_start, data_end); 567 568 /* 569 * Make the current descriptor valid again and go to 570 * the next one 571 */ 572 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 573 574 /* Flush only status field - others weren't changed */ 575 flush_dcache_range(desc_start, desc_end); 576 577 /* Test the wrap-around condition. */ 578 if (++desc_num >= CFG_RX_DESCR_NUM) 579 desc_num = 0; 580 priv->rx_currdescnum = desc_num; 581 582 return 0; 583} 584 585static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 586{ 587 struct phy_device *phydev; 588 int ret; 589 590 if (IS_ENABLED(CONFIG_DM_ETH_PHY)) 591 eth_phy_set_mdio_bus(dev, NULL); 592 593#if IS_ENABLED(CONFIG_DM_MDIO) 594 phydev = dm_eth_phy_connect(dev); 595 if (!phydev) 596 return -ENODEV; 597#else 598 int phy_addr = -1; 599 600 if (IS_ENABLED(CONFIG_DM_ETH_PHY)) 601 phy_addr = eth_phy_get_addr(dev); 602 603#ifdef CONFIG_PHY_ADDR 604 phy_addr = CONFIG_PHY_ADDR; 605#endif 606 607 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface); 608 if (!phydev) 609 return -ENODEV; 610#endif 611 612 phydev->supported &= PHY_GBIT_FEATURES; 613 if (priv->max_speed) { 614 ret = phy_set_supported(phydev, priv->max_speed); 615 if (ret) 616 return ret; 617 } 618 phydev->advertising = phydev->supported; 619 620 priv->phydev = phydev; 621 phy_config(phydev); 622 623 return 0; 624} 625 626static int designware_eth_start(struct udevice *dev) 627{ 628 struct eth_pdata *pdata = dev_get_plat(dev); 629 struct dw_eth_dev *priv = dev_get_priv(dev); 630 int ret; 631 632 ret = designware_eth_init(priv, pdata->enetaddr); 633 if (ret) 634 return ret; 635 ret = designware_eth_enable(priv); 636 if (ret) 637 return ret; 638 639 return 0; 640} 641 642int designware_eth_send(struct udevice *dev, void *packet, int length) 643{ 644 struct dw_eth_dev *priv = dev_get_priv(dev); 645 646 return _dw_eth_send(priv, packet, length); 647} 648 649int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 650{ 651 struct dw_eth_dev *priv = dev_get_priv(dev); 652 653 return _dw_eth_recv(priv, packetp); 654} 655 656int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) 657{ 658 struct dw_eth_dev *priv = dev_get_priv(dev); 659 660 return _dw_free_pkt(priv); 661} 662 663void designware_eth_stop(struct udevice *dev) 664{ 665 struct dw_eth_dev *priv = dev_get_priv(dev); 666 667 return _dw_eth_halt(priv); 668} 669 670int designware_eth_write_hwaddr(struct udevice *dev) 671{ 672 struct eth_pdata *pdata = dev_get_plat(dev); 673 struct dw_eth_dev *priv = dev_get_priv(dev); 674 675 return _dw_write_hwaddr(priv, pdata->enetaddr); 676} 677 678static int designware_eth_bind(struct udevice *dev) 679{ 680 if (IS_ENABLED(CONFIG_PCI)) { 681 static int num_cards; 682 char name[20]; 683 684 /* Create a unique device name for PCI type devices */ 685 if (device_is_on_pci_bus(dev)) { 686 sprintf(name, "eth_designware#%u", num_cards++); 687 device_set_name(dev, name); 688 } 689 } 690 691 return 0; 692} 693 694int designware_eth_probe(struct udevice *dev) 695{ 696 struct eth_pdata *pdata = dev_get_plat(dev); 697 struct dw_eth_dev *priv = dev_get_priv(dev); 698 phys_addr_t iobase = pdata->iobase; 699 void *ioaddr; 700 int ret, err; 701 struct reset_ctl_bulk reset_bulk; 702#ifdef CONFIG_CLK 703 int i, clock_nb; 704 705 priv->clock_count = 0; 706 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 707 0); 708 if (clock_nb > 0) { 709 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), 710 GFP_KERNEL); 711 if (!priv->clocks) 712 return -ENOMEM; 713 714 for (i = 0; i < clock_nb; i++) { 715 err = clk_get_by_index(dev, i, &priv->clocks[i]); 716 if (err < 0) 717 break; 718 719 err = clk_enable(&priv->clocks[i]); 720 if (err && err != -ENOSYS && err != -ENOTSUPP) { 721 pr_err("failed to enable clock %d\n", i); 722 goto clk_err; 723 } 724 priv->clock_count++; 725 } 726 } else if (clock_nb != -ENOENT) { 727 pr_err("failed to get clock phandle(%d)\n", clock_nb); 728 return clock_nb; 729 } 730#endif 731 732#if defined(CONFIG_DM_REGULATOR) 733 struct udevice *phy_supply; 734 735 ret = device_get_supply_regulator(dev, "phy-supply", 736 &phy_supply); 737 if (ret) { 738 debug("%s: No phy supply\n", dev->name); 739 } else { 740 ret = regulator_set_enable(phy_supply, true); 741 if (ret) { 742 puts("Error enabling phy supply\n"); 743 return ret; 744 } 745 } 746#endif 747 748 ret = reset_get_bulk(dev, &reset_bulk); 749 if (ret) 750 dev_warn(dev, "Can't get reset: %d\n", ret); 751 else 752 reset_deassert_bulk(&reset_bulk); 753 754 /* 755 * If we are on PCI bus, either directly attached to a PCI root port, 756 * or via a PCI bridge, fill in plat before we probe the hardware. 757 */ 758 if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) { 759 u32 pcibase; 760 761 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &pcibase); 762 pcibase &= PCI_BASE_ADDRESS_MEM_MASK; 763 764 iobase = dm_pci_mem_to_phys(dev, pcibase); 765 pdata->iobase = iobase; 766 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 767 } 768 769 debug("%s, iobase=%pa, priv=%p\n", __func__, &iobase, priv); 770 ioaddr = phys_to_virt(iobase); 771 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; 772 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); 773 priv->interface = pdata->phy_interface; 774 priv->max_speed = pdata->max_speed; 775 776#if IS_ENABLED(CONFIG_DM_MDIO) 777 ret = dw_dm_mdio_init(dev->name, dev); 778#else 779 ret = dw_mdio_init(dev->name, dev); 780#endif 781 if (ret) { 782 err = ret; 783 goto mdio_err; 784 } 785 priv->bus = miiphy_get_dev_by_name(dev->name); 786 priv->dev = dev; 787 788 ret = dw_phy_init(priv, dev); 789 debug("%s, ret=%d\n", __func__, ret); 790 if (!ret) 791 return 0; 792 793 /* continue here for cleanup if no PHY found */ 794 err = ret; 795 mdio_unregister(priv->bus); 796 mdio_free(priv->bus); 797mdio_err: 798 799#ifdef CONFIG_CLK 800clk_err: 801 ret = clk_release_all(priv->clocks, priv->clock_count); 802 if (ret) 803 pr_err("failed to disable all clocks\n"); 804 805#endif 806 return err; 807} 808 809static int designware_eth_remove(struct udevice *dev) 810{ 811 struct dw_eth_dev *priv = dev_get_priv(dev); 812 813 free(priv->phydev); 814 mdio_unregister(priv->bus); 815 mdio_free(priv->bus); 816 817#ifdef CONFIG_CLK 818 return clk_release_all(priv->clocks, priv->clock_count); 819#else 820 return 0; 821#endif 822} 823 824const struct eth_ops designware_eth_ops = { 825 .start = designware_eth_start, 826 .send = designware_eth_send, 827 .recv = designware_eth_recv, 828 .free_pkt = designware_eth_free_pkt, 829 .stop = designware_eth_stop, 830 .write_hwaddr = designware_eth_write_hwaddr, 831}; 832 833int designware_eth_of_to_plat(struct udevice *dev) 834{ 835 struct dw_eth_pdata *dw_pdata = dev_get_plat(dev); 836#if CONFIG_IS_ENABLED(DM_GPIO) 837 struct dw_eth_dev *priv = dev_get_priv(dev); 838#endif 839 struct eth_pdata *pdata = &dw_pdata->eth_pdata; 840#if CONFIG_IS_ENABLED(DM_GPIO) 841 int reset_flags = GPIOD_IS_OUT; 842#endif 843 int ret = 0; 844 845 pdata->iobase = dev_read_addr(dev); 846 pdata->phy_interface = dev_read_phy_mode(dev); 847 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) 848 return -EINVAL; 849 850 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); 851 852#if CONFIG_IS_ENABLED(DM_GPIO) 853 if (dev_read_bool(dev, "snps,reset-active-low")) 854 reset_flags |= GPIOD_ACTIVE_LOW; 855 856 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, 857 &priv->reset_gpio, reset_flags); 858 if (ret == 0) { 859 ret = dev_read_u32_array(dev, "snps,reset-delays-us", 860 dw_pdata->reset_delays, 3); 861 } else if (ret == -ENOENT) { 862 ret = 0; 863 } 864#endif 865 866 return ret; 867} 868 869static const struct udevice_id designware_eth_ids[] = { 870 { .compatible = "allwinner,sun7i-a20-gmac" }, 871 { .compatible = "amlogic,meson6-dwmac" }, 872 { .compatible = "st,stm32-dwmac" }, 873 { .compatible = "snps,arc-dwmac-3.70a" }, 874 { .compatible = "sophgo,cv1800b-dwmac" }, 875 { } 876}; 877 878U_BOOT_DRIVER(eth_designware) = { 879 .name = "eth_designware", 880 .id = UCLASS_ETH, 881 .of_match = designware_eth_ids, 882 .of_to_plat = designware_eth_of_to_plat, 883 .bind = designware_eth_bind, 884 .probe = designware_eth_probe, 885 .remove = designware_eth_remove, 886 .ops = &designware_eth_ops, 887 .priv_auto = sizeof(struct dw_eth_dev), 888 .plat_auto = sizeof(struct dw_eth_pdata), 889 .flags = DM_FLAG_ALLOC_PRIV_DMA, 890}; 891 892static struct pci_device_id supported[] = { 893 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 894 { } 895}; 896 897U_BOOT_PCI_DEVICE(eth_designware, supported); 898